Schem, MLB - Kepler - 2phase, J31: Schematic / PCB #'S

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2012-02-15
www.qdzbwx.com SCHEM,MLB_KEPLER_2PHASE,J31
FRB & RISK RAMP 02/15/12
D (.csa) Date (.csa) Date (.csa) Date

D
Page Contents Sync Page Contents Sync Page Contents Sync
TABLE_TABLEOFCONTENTS_HEAD
1 MASTER TABLE_TABLEOFCONTENTS_HEAD
50 01/19/2012 TABLE_TABLEOFCONTENTS_HEAD
98 09/16/2011
1 Table of Contents MASTER 46 SMC Support J31_YONAS 91 PCH VCCIO (1.05V) POWER SUPPLY J31_JACK
2 04/19/2011 51 05/26/2011 99 09/19/2011
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
2 Revision History J31_MLB 47 LPC+SPI Debug Connector J5_MLB 92 Power Sequencing EG/PCH S0 J31_SREE
3 06/30/2009 52 04/27/2010 100 08/09/2010
3 Power Block Diagram K17_REF 48 SMBus Connections K18_MLB 93 CPU Constraints K92_MLB
TABLE_TABLEOFCONTENTS_ITEM
4 MASTER TABLE_TABLEOFCONTENTS_ITEM
53 01/19/2012 TABLE_TABLEOFCONTENTS_ITEM
101 06/25/2011
4 Revision History MASTER 49 Power Sensors: Load Side J31_YONAS 94 Memory Constraints K91_MLB
102 08/09/2010
5 BOM Configuration K17_REF 50 Power Sensors: High Side, CPU, AXG J31_YONAS 95 PCH Constraints 1 K92_MLB
7 04/27/2010 55 09/08/2011 103 05/05/2011
6 Functional / ICT Test K18_MLB 51 Thermal Sensors J31_YONAS 96 PCH Constraints 2 J31_YONAS
104 08/03/2010
7 Power Aliases J31_MLB 52 Fan Connectors K18_MLB 97 Ethernet/FW Constraints K91_ERIC
9 04/27/2010 57 06/10/2011 105 06/14/2011
8 Signal Aliases K18_MLB 53 WELLSPRING 1 J30_MLB 98 Thunderbolt Constraints T29_REF

10 03/11/2011 58 07/01/2011 106 08/11/2011
9 CPU DMI/PEG/FDI/RSVD J5_MLB 54 WELLSPRING 2 J31_LINDA 99 SMC Constraints J31_YONAS

11 08/03/2010 59 08/11/2011 107 08/09/2010
10 CPU CLOCK/MISC/JTAG K92_MLB 55 Digital Accelerometer J31_YONAS 100 GPU (Kepler) CONSTRAINTS K92_MLB
108 04/27/2010
11 CPU DDR3 INTERFACES K92_SUMA 56 SPI ROM K91_BEN 101 Project Specific Constraints K18_MLB
109 04/27/2010
12 CPU POWER K92_MLB 57 AUDIO: CODEC/REGULATOR J31_AUDIO 102 PCB Rule Definitions K18_MLB
14 06/15/2010 63 10/26/2011 130 09/12/2011
13 CPU POWER AND GND K92_SUMA 58 AUDIO: LINE INPUT FILTER J31_AUDIO 103 Power Sensors: SMC Extended J31_YONAS
131 09/12/2011
14 CPU DECOUPLING-I K92_MLB 59 AUDIO: DETECT/MIC BIAS J31_AUDIO 104 Power Sensors: Debug ADC J31_YONAS
17 08/19/2010 65 10/26/2011 132 08/24/2011
15 CPU DECOUPLING-II K92_MLB 60 AUDIO: HEADPHONE FILTER J31_AUDIO 105 Power Sensors: CPU Ripple J31_YONAS
16 PCH SATA/PCIe/CLK/LPC/SPI J31_ANNE 61 AUDIO: SPEAKER AMP J31_AUDIO
C
17
19
20
PCH DMI/FDI/PM/Graphics J5_MLB
05/26/2011
06/02/2011
62
67
68
AUDIO: JACKS J31_AUDIO
10/26/2011
10/26/2011
C
18 PCH PCI/USB/TP/RSVD J31_ANNE 63 AUDIO: JACK TRANSLATORS J31_AUDIO
69 09/02/2011
19 PCH GPIO/MISC/NCTF J31_ANNE 64 DC-In & Battery Connectors J31_JACK
22 03/21/2011 70 11/14/2011
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
20 PCH POWER J5_MLB 65 PBus Supply & Battery Charger J31_JACK

23 03/21/2011 71 09/14/2011
21 PCH GROUNDS J5_MLB 66 System Agent Supply J31_JACK

24 05/26/2011 72 11/09/2011
22 PCH DECOUPLING J5_MLB 67 5V / 3.3V Power Supply J31_JACK

25 06/09/2011 73 07/07/2011
23 CPU & PCH XDP J31_ANNE 68 1.5V DDR3 Supply J31_JACK

74 11/11/2011
24 Chipset Support K92_MLB 69 CPU IMVP7 & AXG VCore Regulator J31_JACK
27 09/16/2011 75 11/11/2011
25 USB HUB & MUX J31_LINDA 70 CPU IMVP7 & AXG VCore Output J31_JACK
28 04/27/2010 76 09/19/2011
26 CPU Memory S3 Support K18_MLB 71 CPU VCCIO (1V0R1V05 S0) POWER SUPPLY J31_JACK
29 06/23/2010 77 06/10/2011
27 DDR3 SO-DIMM Connector A K92_SUMA 72 Misc Power Supplies J31_JACK

30 05/10/2010 78 05/05/2011
28 DDR3 Byte/Bit Swaps K92_SUMA 73 Power FETs J31_MARY

31 06/23/2010 79 06/06/2011
29 DDR3 SO-DIMM Connector B K92_SUMA 74 Power Control 1/ENABLE J31_MARY

33 10/25/2011 80 10/25/2011
30 SD Card Connector J31_YONAS 75 KEPLER PCI-E J31_SREE

34 06/09/2011 81 01/18/2012
31 DDR3/FRAMEBUF VREF MARGINING J31_ANNE 76 KEPLER CORE/FB POWER D2_MLB_2P

35 11/11/2011 82 10/25/2011
32 X19/ALS/CAMERA CONNECTOR J30_MLB 77 KEPLER FRAME BUFFER I/F J31_SREE

36 06/14/2011 83 11/16/2011
33 Thunderbolt Host (1 of 2) T29_REF 78 1V05 GPU / 1V35 FB POWER SUPPLY J31_JACK

37 06/14/2011 84 10/25/2011
34 79
B TABLE_TABLEOFCONTENTS_ITEM
35
38
Thunderbolt Host (2 of 2)
Thunderbolt Power Support
T29_REF
T29_REF
06/22/2011
80
85
GDDR5 Frame Buffer A
GDDR5 Frame Buffer B
J31_SREE
J31_SREE
10/25/2011 B
39 10/11/2010 86 10/25/2011
36 ETHERNET PHY (CAESAR IV) K91_ERIC 81 KEPLER LVDS/DP/GPIO J31_SREE

87 11/16/2011
37 Ethernet Connector K91_TRINHNI 82 KEPLER GPIOS,CLK & STRAPS J31_SREE
41 04/27/2010 88 10/31/2011
38 FireWire LLC/PHY (FW643) K18_MLB 83 KEPLER PEX PWR/GNDS J31_SREE

42 06/17/2011 89 01/18/2012
39 FireWire Port & PHY Power K91_MLB 84 GFX IMVP VCore Regulator D2_MLB_2P
43 06/10/2010 90 04/27/2010
40 FireWire Connector T27_REF 85 LVDS Display Connector K18_MLB

92 11/21/2010
41 SATA Redriver/Conn, IR, SIL J31_YONAS 86 Muxed Graphics Support K92_MLB
46 09/21/2011 93 06/20/2011
42 External A USB3 Connector J31_LINDA 87 Thunderbolt MUXing A J31_WILL

94 06/14/2011
43 External B USB3 Connector J30_MLB 88 Thunderbolt Connector A T29_REF
96 08/03/2010
44 Front Flex Support K18_MLB 89 Graphics MUX (GMUX) K91_MARY
49 12/19/2011 97 03/21/2011
45 SMC J31_YONAS
90 LCD Backlight Driver J31_KIRAN
A A
DRAWING TITLE
SCHEM,MLB_KEPLER,J31
DRAWING NUMBER SIZE
Schematic / PCB #’s Apple Inc. 051-9585 D
REVISION
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R
3.0.0
051-9585 1 SCHEM,MLB_KEPLER_2PHASE,J31 SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
820-3330 1 PCBF,MLB_KEPLER_2PHASE,J31 PCB CRITICAL PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
ABBREV=DRAWING
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 132
TITLE=MLB III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
LAST_MODIFIED=Wed Feb 15 20:30:03 2012 IV ALL RIGHTS RESERVED 1 OF 105
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J2500,J2550
U8000 INTEL CPU

GRAPHICS XDP CONN
2.X GHZ
PG 23
NVIDIA KEPLER IVY BRIDGE
J2900
PG 9
J3100
PG 73
2 DIMMS
DDR3-1067/1333MHZ
DIMM
D J6950
D
POWER SUPPLY
PG 27,29
DC/BATT
PG 63
GPIO FDI DMI RTC

ALS SENSOR
PG 19 PG 17 PG 17 PG 16 PG 32
U6100
SPI U5920
SMS SENSOR
PG 50
Boot ROM
U3600
Misc PG 55
THERMAL SENSOR
PG 50
T29 CLK
PG 19
PG 33/34
BUFFER POWER SENSE
PG 48
PG 16
J5650,5660
SPI FAN CONN AND CONTROL

J4500
PG 51
5
PG 16
ODD SATA
CONN
4
PG 41
SATA INTEL
DP/T29 J5100 Ser
B,0 BSB I2C I2C ADC Fan
LPC + SPI CONN Prt
MUX
3
PANTHER-POINT SMC
PG 85 J4501
PG 16 Port80,serial
LPC PG 46 PG 44
MOBILE
C
U4900
2
HDD SATA
CONN PG 16
U1800
1
PG 41
0
PWR
CTRL
PG 17
U9220
U2700 J3501
DP DDC MUX LVDS BLUETOOTH PG 32
10 11 12 13
J4501/U4800
IR PG 41/43
PG 84 USB HUB
J5713/U5701 PG 52
TRACKPAD/KEYBOARD
9
(UP TO 14 DEVICES)
J4600
8
J9400 SMC DEBUG PORT PG 42
7
PG 25
PG 18
USB
PG 17
6
MINI DP PORT
5
4
PG 84 J4600 EXTERNAL A
PCI PG 42
3
2
PG 18
1
J4610 PG 42
0
EXTERNAL B
B
U9270
B JTAG
LVDS DDC MUX SMB
PG 16 SMBUS
PG 16
PG 84
CONNECTION
PCI-E HDA PG 47
PEG
(UP TO 16 LINES)
PG 16
PG 16 PG 16
DIMM
J9000
LVDS CONN PG 27,29
PG 83
U9600
U6201
AUDIO
GMUX
CODEC
PG 86
PG 56
www.qdzbwx.com U4100
U3900
U6610,6620,6630
A FW643
ETHERNET
LINE INPUT HEADPHONE SPEATKER
SYNC_MASTER=J31_MLB SYNC_DATE=04/19/2011 A
J3501 FILTER FILTER AMP PAGE TITLE
BCM57765B0
PG 38 PG 36
PG 57 PG 58 PG 59 Revision History
AirPort DRAWING NUMBER SIZE
Apple Inc. 051-9585 D

J4310
J4000 J3300 REVISION
PG 32
FIREWIRE
J6781,J6782
R
3.0.0
ETHERNET SDCARD READER J6700,J6750
NOTICE OF PROPRIETARY PROPERTY: BRANCH
AUDIO
CONN CONN CONN THE INFORMATION CONTAINED HEREIN IS THE
CONN SPEATKER PROPRIETARY PROPERTY OF APPLE INC.
PG 40 PG 37 PG 30
PG 60 PG 60
2 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 105
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D6990
J31 POWER SYSTEM ARCHITECTURE
VIN SMC RESET SMC_RESET_L
J6900 F6905 RESET
R6990 ENABLE SMC_TPAD_RST_L SMC AVREF SUPPLY
6A FUSE
AC 3.425V G3HOT PP3V42_G3H MR1
SN0903048 PP3V3_S5_AVREF_SMC
PP18V5_DCIN_CONN PM6640
ADAPTER SMC_ONOFF_L U5010
PPBUS_G3H REFOUT
Q5300 U6990
IN V MR2
(PAGE 46) U3815 & U3816
SMC_PBUS_VSENSE (PAGE 63)
DCIN(18.5V) F7040
Q5310 1V05 T29 PP1V05_T29_FET
R7020
U7000 VIN VOUT
SMC_DCIN_VSENSE SWITCH
ISL6259HRTZ V
VOUT PPVBUS_G3H PPBUS_G3H U5310 (PAGE 35)
VIN PP5V_S0_CPUVCCIOS0
A PBUS SUPPLY/ 8A FUSE
PPBUS_G3H EN
(R7640)
D SMC_DCIN_ISENSE
SMC_RESET_L
BATTERY CHARGER
SMB_RST_N
R7050
A A
CPU VCCIO
VIN VOUT
A
PPCPUVCCIO_S0_REG TBT_PWR_EN
D
J6950 PPVBAT_G3H_CONN 1V0 /
(PAGE 64) U5400
Q7055 SMC_BMON_ISENSE 1.05V SMC_CPUVCCIO_ISENSE TPS22924
SMC_CPU_HI_ISENSE PP1V0_FW_FET_R
ISL95870 U4202
CPUVCCIOS0_PGOOD VIN VOUT
(9 TO 12.6V)
PPVBAT_G3H_CHGR_R PGOOD (PAGE 39)

U7600
PPBUS_G3H CPUVCCIOS0_EN EN
EN
3S2P
PM_S0_PGOOD
(PAGE 70)
Q7840 FW_PWR_EN
CHGR_BGATE
A U5450
PP5V_SUS_FET U9950 PM_PCH_SYS_PWROK
PP5V_S5_P5VSUSFET V
U5410 SMC_CPU_VSENSE
SMC_GPU_HI_ISENSE PPVCORE_S0_CPU
CPU/AXG VCORE
A
PP5V_S5_LDO CPU VOUT
PPDDR_S3_REG
P5VSUS_EN SMC_CPU_ISENSE
Q7801 MAX15119GTM PM_PCH_PWROK
VIN VREG5 P1V5CPU_EN SMC_AXG_VSENSE
P5VS3_EN VIN PP1V5_S3RS0_FET VIN U5460 U9950
VOUT1 PP5V_S3_REG V
EN1 5V ON G
(L/H) SLG5AP020 PPVCORE_S0_AXG_REG
U7801 U7400 A CPUIMVP_VR_ON
USB PORT
P3V3S5_EN VOUT2 (PAGE 72)
EN2 3.3V POWER SWITCH PP5V_S3_RTUSB_A_ILIM COUGAR_POINT
PP5V_S5_LDO 5V CPUIMVP_VR_ON SMC_AXG_ISENSE
(R/H) PP3V3_S5_REG P1V5S3RS0FET_GATE VOUT1 PWRBTN# PM_PWRBTN_L
VIN EN
U4600 PP5V_S3_RTUSB_B_ILIM PGOKA CPUIMVP_PGOOD (E20)
TPS51980 VIN PP18V5_S4
VOUT (PAGE 42) VOUT2 SYS_RERST# PM_SYSRST_L
U7201 CPUIMVP_AXG_PGOOD
TPS61045 EN1 EN2 PGOKB (K3)
(PAGE 66) U5805 USB_PWR_EN PM_DSW_PWRGD
(PAGE 68) DPWROK
PGOOD1 PGOOD2 (E22)
P3V3S5_PGOOD (PAGE 54) SMC_ADAPTER_EN
SMC_SYS_KBDLED PP5V_S3_DDRREG ACPRESENT/GPIQ31
Q7860 VIN
CTRL LED (H20) PLT RESET L
P5VS3_PGOOD PP3V3_S5 P1V5S0_PGOOD PLTRST#
PP5V_S0_FET KB_BL (C6)
C SMC Q7870
LT3491
U5850
VIN VLDOIN
U5360
(R7350)
P1V8S0_PGOOD
SYS_PWROK
(AY11)
CPU_PWRGD C
H10 SMC_BATLOW_L PP3V3_S0GPU_FET (PAGE 54) PROCPWRGD
DDRREG_EN 1.5V PP1V5_S3 P5VS3_PGOOD
PPDDR_S3_REG DRAMPWROK PM_MEM_PWRGD
U4900 S5 VOUT1
P5VS0_EN 4.5V AUDIO A CPUVCCIOS0_PGOOD RSMRST#
PP4V5_AUDIO_ANALOG (C21)
M2 SMC_PM_G2_EN RC P3V3S5_EN MAX8840 DDRVTT_EN SMC_DDR3_ISENSE
VIN S3 U1800 PM_RSMRST_L
(PAGE 45) VOUT 0.75V PPVTT_S0_DDR_LDO PCHVCCIOS0_PGOOD
DELAY U6200 VOUT2 (PAGE 16~21)
P3V3GPU_EN PP3V3_S0_AUDIO
SHND (PAGE 57)
RC PVCCSA_PGOOD
P3V3S3_EN
COUGAR-POINT Q7810 TPS51916 DDRREG_PGOOD
DELAY T29 15V BOOST ALL_SYS_PWRGD_R 3V3 SUS DETECT
PP3V3_S3_FET U7300 PGOOD
Q7922 U5360
MOBILE RC DDRREG_EN PP15V_T29_REG U7930 RESET
PP3V3_ENET_FET (PAGE 67) (R7140)
LT3957
DELAY VIN U3890 SYSTEM AGENT PPVCCSA_S0_REG (PAGE 73)
U1800 VOUT
P5VS3_EN (PAGE 35) VOUT
VIN A
P3V3S3_EN T29_A_HV_EN EN PM_MEM_PWRGD
PM_SLP_S4_L FIREWIRE PORT ISL95870A SMC_CPUVCCSA_ISENSE CPU
Q7830 PM_SLP_S3_L & WOL_EN & SMC_ADAPTER_EN
PVCCSA_EN PP3V3_S0_VMON SM_DRAMPWROK
POWER SWITCH PPBUS_FW_FET U7100 (AY25)
SLP_S4#(H4) T29 SWITCH PVCCSA_PGOOD
PM_SLP_SUS_L PP3V3_S0_FET EN PGOOD CPU_PWRGD
VIN U4260
SLP_SUS 3.3V PP3V3_T29_FET (PAGE 39) VOUT
(PAGE 65) VCC UNCOREPWRGOOD
R7916 TPS22924 PP5V_S0_VMON (C60)
SLP_S5*(D10) PM_SLP_S5_L P3V3S4_EN VIN U3810 VOUT FWPORT_PWR_EN EN V2MON CPU_RESET_L
$CDS_IMAGE|R.jpg|272|166 U7960 U1000
P3V3S0_EN (PAGE 35) GPU VDDCI
VIN VOUT PPVDDCI_S0_REG RESET*
R2526 Q7800 0V9~1V15 PP1V5_S3RS0_VMON ISL88042IRTEZ (PAGE 9~13)
TBT_PWR_EN EN (K51)
(D14) XDP_DB2_WOL_EN WOL_EN PP3V3_S4_FET ISL95870A V3MON
$CDS_IMAGE|R.jpg|272|166 RST*
U9800
U2150 PVDDCI_EN EN
(V13) FW_PWR_EN_PCH FW_PWR_EN (PAGE 90) PGOOD PVDDCI_PGOOD PP1V05_S0_VMON SMC
(A2) (Y2) TPS22924 V4MON
PP3V3_FW_FET (PAGE 73)
(PAGE 24) VIN U4201 VOUT T1CCP1/PJ1
P3V3S4_EN UD141 SMC_ADAPTER_EN
(PAGE 39) TRST = 200mS
(RD145) ALL_SYS_PWRGD WT2CCP0/PH0(K3) (B9)
AUD_IPHS_SWITCH_EN_PCH U2152 TBT_PWR_EN
(U2) EN FPF1009 PP1V0_S0GPU_REG
(A2) (Y1) S5_PWRGD
P1V0GPU_EN VIN SSIOFSS/PA3
VIN U9000 VOUT PP3V3_SW_LCD_UF EN1 VOUT1
B SLP_S3#(F4) PM_SLP_S3_L
(PAGE 24) FW_PWR_EN
(PAGE 84) 1V0GPU/1V5 FB
A
SMC_ONOFF_L
S5_PWRGD(L9)
(M3) PM_DSW_PWRGD
B
EN 1.003V(L/H) SMC_GPU_1V0_ISENSE PQ7/IRQ131(L6)
(PAGE 16~21) LCD_PWR_EN UD120
Q9706 VOUT2 PP1V5_GPU_REG
R7978 F9700 P1V5FB_EN WT3CCP1/PH5
PPBUS_SW_BKL EN2 PM_SYSRST_L
GMUX LCD_PWR_EN (H4)
VIN
U9600(N8) PP1V5_S0_REG 1.503V(R/H)
P1V5S0_EN EN TPS62201 VOUT A PP3V3_S0_PWRCTL WT3CCP0/PH4
(PAGE 88)
PM_SLP_S3_R_L U7710 3A 32V FUSE P1V0GPU_PGOOD PM_PWRBTN_L
T29_A_HV_EN_R SMC_LCDBKLT_ISENSE ISL6236 POK1 (J3)
(PAGE 71) LCD_BKLT_EN
PORT A MCU R9334 U8300 PM_SLP_S5_L PP3V3_S5_AVREF_SMC
T29_A_HV_EN POK2 P1V5FB_PGOOD
U9330 $CDS_IMAGE|R.jpg|272|166 VIN && PQ6/IRQ130(M6) VREFA+
(18) P1V2S0_EN 1V2_S0(GMUX) (PAGE 77)
RC P1V8S0_EN PP1V2_S0_REG PM_SLP_S4_L (D2)
(PAGE 86) EN TPS62201 VOUT BKLT_PLT_RST_L
DELAY PQ5/IRQ129(K5)
U7760 R9990
PM_SLP_S3_L RST* SMC_RESET_L
SMC_BATLOW_L 3.3V/5.0V (PAGE 71) PQ4/IRQ128(N6)
(A) RC P1V2S0_EN Q7820 GPUVCORE_PGOOD (G10)
(Y) P5VSUS_EN DELAY VIN
SUS ENABLE PP3V3_SUS_FET LP8550 PM_ALL_GPU_PGOOD LM4FSXAH5BB
PM_SLP_SUS_L
(C) U7940 PPBUS_SW_LCDBKLT_PWR U9701 P1V5FB_PGOOD U4900
P3V3SUS_EN WHISTLER PCI-E
(PAGE 73) EN PPVOUT_SW_LCDBKLT (PAGE 44)
RC CPUVCCIOS0_EN PP3V3_SUS_P1V05SUSLDO VOUT PWRGOOD
DELAY P1V0GPU_PGOOD (AH16)
(PAGE 89) U8000
PB7A LCD_BKLT_EN (PAGE 74)
GMUX
P3V3SUS_EN
PB16B EG_RAIL1_EN P3V3GPU_EN
U9600 RC P1V5S0_EN VIN GRAPHICS MUX
ALL_EG_PGOOD
DELAY PP1V05_SUS_LDO
PB17A EG_RAIL2_EN GPUVCORE_EN EN TPS720105 VOUT V PL25A
U7740 (N1) U9600
XP25-5
EG_RAIL3_EN P1V0GPU_EN SMC_LCDBKLT_VSENSE (PAGE 88)
PB17B RC PVCCSA_EN (PAGE 71)
DELAY P1V8S0_EN U5310
PB18A EG_RAIL4_EN P1V5FB_EN VIN PP1V8_S0_REG SMC_GPU_VSENSE
VOUT
RC PCHVCCIOS0_EN EN ISL8014A VIN V
(PAGE 88) P1V8GPU_EN PPVCORE_GPU_REG
DELAY U7720 PP5V_S3_GPUVCORE
PL25A P1V8S0_PGOOD VDD/PVCC VOUT A
ALL_EG_PGOOD PM_ALL_GPU_PGOOD PGOOD
(PAGE 71)
GPU VCORE
A UD180 ISL6263C
SMC_GPU_ISENSE
SYNC_MASTER=K17_REF SYNC_DATE=06/30/2009 A
PAGE TITLE
P1V8GPU_EN VIN (RD186) U8900
ISOLATE_CPU_MEM_L
EN 1V8GPU FET PP1V8_GPU_FET
PP1V8_S0GPU_ISNS
Power Block Diagram
$CDS_IMAGE|O.jpg|416|272 VR_ON PGOOD
P5VS0_EN NCP4543IMN5RG-A GPUVCORE_EN DRAWING NUMBER SIZE
GPUVCORE_PGOOD
PM_SLP_S3_L P1V5CPU_EN U7880 VOUT A (PAGE 83) Apple Inc. 051-9585 D
PM_SLP_S4_L (PAGE 72) REVISION
SMC_GPU_1V8_ISENSE
PLT_RST_L $CDS_IMAGE|O_0.jpg|416|272 P3V3S0_EN R5388/U5388
R
3.0.0
MEMVTT_EN
PROPRIETARY PROPERTY OF APPLE INC.
PM_SLP_S3_L
PBUSVSENS_EN
www.qdzbwx.com THE POSESSOR AGREES TO THE FOLLOWING: PAGE
CPU_MEM_RESET_L
$CDS_IMAGE|O_1.jpg|416|272 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
3 OF 132
MEM_RESET_L SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
B B
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Revision History
DRAWING NUMBER SIZE

REVISION
R
3.0.0
4 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM VARIANTS - FSB
BOM NUMBER BOM NAME BOM OPTIONS
TABLE_BOMGROUP_HEAD
- Bar Code Labels / EEEE #’s

|
TABLE_BOMGROUP_ITEM
639-3860 PCBA,MLB_2P,FSB,2.3,FOX,512_HYN,REN,J31,F327 J31_CMNPTS,SODIMM:FOXCONN,CPU:2_3GHZ,FB_512_HYNIX,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F327 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
TABLE_BOMGROUP_ITEM
639-3861 PCBA,MLB_2P,FSB,2.3,MOL,512_SAM,FAIR,J31,F32C J31_CMNPTS,SODIMM:MOLEX,CPU:2_3GHZ,FB_512_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F32C 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F327] CRITICAL EEEE:F327

TABLE_BOMGROUP_ITEM
639-3862 PCBA,MLB_2P,FSB,2.6,MOL,1G_HY,FAIR,J31,F325 J31_CMNPTS,SODIMM:MOLEX,CPU:2_6GHZ,FB_1G_HYNIX_A_DIE,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F325 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F32C] CRITICAL EEEE:F32C

TABLE_BOMGROUP_ITEM
639-3863 PCBA,MLB_2P,FSB,2.6,FOX,1G_SAM,REN,J31,F324 J31_CMNPTS,SODIMM:FOXCONN,CPU:2_6GHZ,FB_1G_SAMSUNG,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F324 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F325] CRITICAL EEEE:F325

TABLE_BOMGROUP_ITEM
639-3864 PCBA,MLB_2P,FSB,2.7,FOX,1G_HY,REN,J31,F328 J31_CMNPTS,SODIMM:FOXCONN,CPU:2_7GHZ,FB_1G_HYNIX_A_DIE,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F328 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F324] CRITICAL EEEE:F324

TABLE_BOMGROUP_ITEM
639-3865 PCBA,MLB_2P,FSB,2.7,MOL,1G_SAM,FAIR,J31,F329 J31_CMNPTS,SODIMM:MOLEX,CPU:2_7GHZ,FB_1G_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F329 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F328] CRITICAL EEEE:F328
D 607-9557 CMN PTS,PCBA,MLB_KEPLER,J31 J31_COMMON

TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F329] CRITICAL EEEE:F329 D
085-4620 J31 MLB_KEP_2P DEVELOPMENT BOM J31_DEVEL:PVT
SUB BOMS
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
085-4620 1 J31 MLB_KEP_2P DEVELOPMENT BOM DEVEL CRITICAL DEVEL_BOM
607-9557 1 CMN PTS,PCBA,MLB_KEP_2P,J31 CMNPTS CRITICAL J31_CMNPTS
BOM GROUPS
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM
J31_COMMON ALTERNATE,COMMON,J31_COMMON1,J31_COMMON2,J31_PROGPARTS,J31_PROGPARTS1,UVGLUE_J31,J31_PVT
TABLE_BOMGROUP_ITEM
J31_COMMON1 CPUMEM_S0,RAMCFG_SLOT,USBHUB2513B,HUB_3NONREM,SMC_PACKAGE:PROD,MOJO:YES,TBTHV:P15V,SKIP_5V3V3:AUDIBLE
TABLE_BOMGROUP_ITEM
Alternate Parts
J31_COMMON2 BTPWR:S4,TPAD:Z2,T29:YES,TBTBST:Y,SDRV_PD,SDRVI2C:MCU,T29_DP_HPD:ALL_OR,LPCPLUS_R:YES,MEM_VDD_SEL:GPIO15,GPU:2P (Alternate) (Primary)
TABLE_BOMGROUP_ITEM TABLE_ALT_HEAD
J31_PROGPARTS GMUX_PROG,IR_PROG,TPAD_PROG:FSB,ENETROM_PROG:FSB,T29ROM:PROG,T29MCU:PROG
TABLE_BOMGROUP_ITEM
PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS:
Programmables - All Builds
J31_PROGPARTS1 SMC_PROG:RR,BOOTROM_PROG:FSB TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
157S0058 157S0055 ALL Delta alt to TDK Magnetics
J31_PVT VREF:PROD,XDP,XDP_CPU:BPM,BKLT:PROD,LOADISNS:NO,XWLOADISNS:NO TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
152S0896 152S0518 ALL MAG LAYERS ALT TO CYNTEC
J31_DEVEL:ENG DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,GMUX_JTAG_CONN,LPCPLUS_CONN:YES,BKLT:ENG,S0PGOOD_ISL,CPURIPPLE_ENG,LOADISNS:YES,XWLOADISNS:YES,DEBUG_ADC TABLE_ALT_ITEM
PSOC
TABLE_BOMGROUP_ITEM
155S0457 155S0329 ALL MAG LAYERS ALT TO MURATA
J31_DEVEL:FSB DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,LPCPLUS_CONN:YES,BKLT:PROD,S0PGOOD_ISL,LOADISNS:YES,XWLOADISNS:NO TABLE_ALT_ITEM
341S3099 1 IC,TP PSOC,K9x,DVT,PVT,J31 U5701 CRITICAL TPAD_PROG:PROTO0

TABLE_BOMGROUP_ITEM
353S2805 353S2603 ALL Fairchild wafer option
C J31_DEVEL:PVT
IVB_PPT_XDP
LPCPLUS_CONN:YES,XDP_CONN_CPU
XDP,XDP_CONN_PCH,XDP_CONN_CPU,XDP_CPU:BPM,XDP_PCH
TABLE_BOMGROUP_ITEM
128S0264 128S0257 ALL Sanyo alt to Kemet
TABLE_ALT_ITEM
TABLE_ALT_ITEM
341S3351
341S3227
1
1
IC,TP PSOC,PROTO1,J31
IC,TP PSOC,PROTO2,PROTO3-Z2,J31
U5701
U5701
CRITICAL
CRITICAL
TPAD_PROG:PROTO1
TPAD_PROG:PROTO3
C
128S0303 128S0282 ALL Panasonic alt to Sanyo
TABLE_ALT_ITEM
341S3489 1 IC,TP PSOC,PIB,J31 U5701 CRITICAL TPAD_PROG:PIB

353S3085 353S1658 ALL ST Micro alt to LT
341S3522 1 U5701 CRITICAL TPAD_PROG:FSB

TABLE_ALT_ITEM
IC,TP PSOC,FSB,J31
376S0972 376S0612 ALL ROHM alt to Toshiba N-FET
TABLE_ALT_ITEM
376S0855 376S0613 ALL Diodes alt to Toshiba dual N-FET
TABLE_ALT_ITEM
138S0676 138S0691 ALL Murata alt to Samsung cap
TABLE_ALT_ITEM
138S0652 138S0648 ALL Samsung / Murata alt for Taiyo Yuden 341S2830 1 IC,CPLD,LATTICE,GMUX,K91/K91F,J31 U9600 CRITICAL GMUX_PROG
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
138S0681 138S0638 ALL Taiyo Yuden alt for Samsung 336S0042 1 IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA U9600 CRITICAL GMUX_BLANK
BOM GROUP BOM OPTIONS TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
152S0685 152S0796 ALL Dale/Vishay/TDK alt for Cyntec 341S2384 1 IR,ENCORE II,CY7C63833-LFXC U4800 CRITICAL IR_PROG
VREF:PROD VREFDQ:M1_M3,VREFCA:LDO TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S0977 376S0859 ALL Diodes alt for Rohm 341S3430 1 IC,T29 EEPROM,LR,J30/J31 U3690 CRITICAL T29ROM:PROG
VREF:ENG_M3 VREFDQ:M1_M3,VREFCA:LDO_DAC TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
353S2592 353S3199 ALL U6201 AUDIO CODEC OLD REV IS ALTERNATE FOR NEW REV 335S0777 1 IC,EEPROM,SERIAL,8KB,SOIC U3690 CRITICAL T29ROM:BLANK
VREF:ENG_LDO VREFDQ:M1_DAC,VREFCA:LDO_DAC TABLE_ALT_ITEM
335S0550 335S0777 ALL add 4K byte as alternative to 2K 341S3365 1 IC,PROGRMD,LPC1112A,T29 PORT MCU,PVT,HVQFN25,J31 U9330 CRITICAL T29MCU:PROG
TABLE_ALT_ITEM
371S0709 371S0652 ALL NXP alternate for pin diodes 337S3997 1 IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25 U9330 CRITICAL T29MCU:BLANK
Module Parts 138S0671 138S0673 ALL Taiyo Yuden alt for Murata 10 uF caps
TABLE_ALT_ITEM
335S0852 1 IC,GPUROM,J31,BLANK U8701 CRITICAL GPUROM:BLANK
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION TABLE_ALT_ITEM
514-0788 514-0671 ALL Acon (with liteon) alt to Acon
337S4266 1 IC,CPU,IVB,S,R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA U1000 CRITICAL CPU:2_3GHZ

TABLE_ALT_ITEM
ETHERNET ROM
155S0578 155S0367 ALL Tayo Yuden alt to Murata inductors
337S4267 1 IC,CPU,IVB,S,R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA U1000 CRITICAL CPU:2_6GHZ

TABLE_ALT_ITEM
335S0663 1 IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC U3990 CRITICAL ENETROM_BLANK

138S0681 138S0638 ALL Tayo Yuden alt to Samsung caps
337S4268 1 IC,CPU,IVB,S,R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA U1000 CRITICAL CPU:2_7GHZ

TABLE_ALT_ITEM
341S3096 1 IC,ENET ROM,1MBIT,DVT,PVT,K90i/K91x,J31 U3990 CRITICAL ENETROM_PROG:PROTO3
B 337S4269 1 IC,PCH,PPT,C1,SLJ8C,PRQ,BD82HM77 U1800 CRITICAL

138S0671
155S0625
138S0673
155S0559
ALL
ALL
Tayo Yuden alt to Murata caps
Murata alt to TDK cm mode filter

TABLE_ALT_ITEM
341S3492 1 IC,PRGRMD,ENET,SPI ROM,FSB,J30/J31 U3990 CRITICAL ENETROM_PROG:FSB B

337S4239 1 IC,GPU,NV GK107-GTX-QS-A2 U8000 CRITICAL
TABLE_ALT_ITEM
SMC
376S0777 376S0761 ALL AON alternate to Siliconix
338S1072 1 IC,ASSP,LIGHTRIDGE,PRQ,S LJJY,FCBGA,15X15MM,C1 U3600 CRITICAL T29:YES

TABLE_ALT_ITEM
338S0895 1 IC,SMC,HS8/2117,9MMX9MM,TLP U4900 CRITICAL SMC_BLANK

157S0084 157S0055 ALL TDK alternate for ethernet transformer
338S0753 1 U4100 CRITICAL 341S3258 1 U4900 CRITICAL SMC_PROG:PROTO0

TABLE_ALT_ITEM
IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12 IC,SMC,DEVELOPMENT-PROTO0,J31

353S3312 353S3055 ALL NXP alternate to Pericom DP mux
353S3055 1 U9390 CRITICAL 341S3294 1 U4900 CRITICAL SMC_PROG:PROTO1

TABLE_ALT_ITEM
IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN IC,SMC,DEVELOPMENT-PROTO1,J31

376S0958 376S0953 ALL For Q7260, Fairchild alt to Ren.
333S0619 4 CRITICAL FB_512_SAMSUNG 341S3401 1 U4900 CRITICAL SMC_PROG:PROTO3

TABLE_ALT_ITEM
IC,SGRAM,GDDR5,32MX32.1.25GHz,G-DIE,HF U8400,U8450,U8500,U8550 IC,EXTERNAL,PROTO2,PROTO3,J31

376S1053 376S0604 ALL Radar 10562726
333S0620 4 IC,SDRAM,GDDR5,32MX32,1.5GHz,VEGA 44NM,B-DIE U8400,U8450,U8500,U8550 CRITICAL FB_512_HYNIX

TABLE_ALT_ITEM
341S3481 1 IC,SMC,EXTERNAL,PIB,V2.1A83,A3,J31 U4900 CRITICAL SMC_PROG:A3_PIB

371S0713 371S0558 ALL Radar 10562508
333S0631 4 CRITICAL FB_1G_SAMSUNG 341S3296 1 U4900 CRITICAL SMC_PROG:FSB

TABLE_ALT_ITEM
IC,SGRAM,GDDR5,64MX32,5GBPS,D-DIE,HF U8400,U8450,U8500,U8550 IC,SMC,EXTERNAL,FSB,V2.1A143,J31

128S0311 128S0329 ALL Radar 10257464
333S0630 4 IC,SGRAM,GDDR5,64MX32,5GBPS,A-DIE,HF U8400,U8450,U8500,U8550 CRITICAL FB_1G_HYNIX_A_DIE

TABLE_ALT_ITEM
341S3297 1 IC,SMC,EXTERNAL,RISKRAMP,J31 U4900 CRITICAL SMC_PROG:RR

127S0134 127S0111 ALL Radar 10360888
EFI ROM
333S0609 4 IC,SGRAM,GDDR5,64MX32,4.2GBPS,M-DIE,HF U8400,U8450,U8500,U8550 CRITICAL FB_1G_HYNIX_M_DIE
TABLE_ALT_ITEM
127S0127 127S0090 ALL Radar 10382328

335S0740 1 64 MBIT SPI SERIAL DUAL I/O FLASH U6100 CRITICAL BOOTROM_BLANK
725-1479 1 CRITICAL UVGLUE_J31
TABLE_ALT_ITEM
MLB LOCTITE UV EB CPU,PCH,T29,GPU,K91 UV_GLUE_J31

197S0431 197S0432 ALL RADAR 10670230
341S3257 1 IC,EFI,ROM,PROTO0, J31 U6100 CRITICAL BOOTROM_PROG:PROTO0
516S0806 1 CRITICAL SODIMM:FOXCONN
TABLE_ALT_ITEM
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN J3100
197S0434 197S0343 ALL RADAR 10739227
341S3344 1 IC,EFI,ROM,PROTO1, J31 U6100 CRITICAL BOOTROM_PROG:PROTO1
516-0246 1 CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN J2900 CRITICAL SODIMM:FOXCONN
TABLE_ALT_ITEM
197S0435 197S0343 ALL RADAR 10739227

341S3419 1 IC,EFI,ROM,PROTO2,J31 U6100 CRITICAL BOOTROM_PROG:PROTO2
516S0805 1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX J3100 CRITICAL SODIMM:MOLEX
341S3454 1 IC,EFI,ROM,PROTO3,J31 U6100 CRITICAL BOOTROM_PROG:PROTO3

516-0245 1 CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,MOLEX J2900 CRITICAL SODIMM:MOLEX
341S3510 1 IC,EFI,ROM,POST-PIB,J31 U6100 CRITICAL BOOTROM_PROG:PIB2

516S0805 1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX J3100 CRITICAL SODIMM:HYBRID
341S3476 1 IC,EFI,ROM,FSB,J31 U6100 CRITICAL BOOTROM_PROG:FSB

516-0246 1 CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN J2900 CRITICAL SODIMM:HYBRID
PD Parts
A 376S0964 2 RJK0225 Q7330,Q8360 CRITICAL FET:REN
SYNC_MASTER=K17_REF SYNC_DATE=05/28/2009 A
376S0965 2 RJK0225 Q7335,Q8361 CRITICAL FET:REN PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PAGE TITLE
376S0979 2 FDMC0225 Q7330,Q8360 CRITICAL FET:FAIR 452-1708 2 SCR,M1.6X0.35X6.0,D4,HO.3,BLK,M97 SODIMM_SCREW1,SODIMM_SCREW2 CRITICAL

BOM Configuration
DRAWING NUMBER SIZE
376S0874 2 FDMC0202S Q7335,Q8361 CRITICAL FET:FAIR 452-1708 2 SCR,M1.6X0.35X6.0,D4,HO.3,BLK,M97 SODIMM_SCREW3,SODIMM_SCREW4 CRITICAL
REVISION
376S0826 1 FET,N-CH,30V,3.6MOHM,LF,HF,RJK0332DPB Q7030 CRITICAL FET:REN 725-1607 1 INSULATOR,GPU,J31 GPU_INSULATOR CRITICAL R
3.0.0
376S0617 1 FET,N-CH,30V,30A,6.7MOHM,RJK0305DPB Q7035 CRITICAL FET:REN NOTICE OF PROPRIETARY PROPERTY: BRANCH
376S0917 1 FET,N-CH,30V,3.6MOHM,LF,HF,FDMS0355S Q7030 CRITICAL FET:FAIR PROPRIETARY PROPERTY OF APPLE INC.
376S1018 1 FET,N-CH,30V,14A,13MOHM,FDMS0349 Q7035 CRITICAL FET:FAIR
5 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NO_TEST=TRUE
J5713 (KEY BOARD CONN)
PP3V3_S4
FUNC_TEST
BKLT_EN
ICT Test Points NC NO_TESTs CHGR_BOOT
Functional Test Points I1103 TRUE
TRUE PP3V42_G3H
6 7
6 7
I720 TRUE
TRUE ISSP_SCLK_P1_1 8
NO_TEST
TRUE NC_SMC_FAN_3_TACH
I1693 TRUE
TRUE CHGR_ICOMP_RC
I1102
WS_KBD1
I722
ISSP_SDATA_P1_0
CPU NO_TESTs I1297
NC_SMC_FAN_3_CTL
I1694
CHGR_LGATE
I1104 TRUE 53 I724 TRUE 8 I761 TRUE I1695 TRUE
J5650 (LEFT FAN CONN)
I1105 TRUE WS_KBD2 53 I723 TRUE LCD_BKLT_PWM 89 90 NO_TEST I762 TRUE NC_SMC_FAN_2_TACH I1696 TRUE CHGR_PHASE
FUNC_TEST
I1107 TRUE WS_KBD3 53 I725 TRUE LPCPLUS_GPIO 19 47 I763 TRUE NC_SMC_FAN_2_CTL TRUE CHGR_UGATE
TRUE PP5V_S0 6 7 TP_CPU_RSVD<65..62> TRUE NC_TP_CPU_RSVD<65..62> I1697
TRUE CPUIMVP_BOOT2
I1106 TRUE WS_KBD4 53 I726 TRUE LPCPLUS_RESET_L 24 47 MAKE_BASE=TRUE I764 TRUE NC_FW2_TPBP 40 I1699 TRUE CHGR_VCOMP I1743
TRUE CPUIMVP_BOOT2_RC
TRUE FAN_LT_PWM 52 I1108 TRUE WS_KBD5 53 I727 TRUE LPC_AD<0..3> 16 45 47 89 96 TP_CPU_RSVD<58..45> TRUE NC_TP_CPU_RSVD<58..45> I765 TRUE NC_FW2_TPBN 40 I1698 TRUE CPU_VCCSASENSE_DIV I1742
MAKE_BASE=TRUE TRUE CPUIMVP_BOOT2G

TRUE FAN_LT_TACH 52 TRUE WS_KBD6 53 TRUE
LPC_CLK33M_LPCPLUS 24 47 96 TRUE NC_FW2_TPBIAS 40 TRUE CPUIMVP_AXG1_SNUB I1744
I1109 I729 I767
TP_CPU_RSVD<43..32> TRUE NC_TP_CPU_RSVD<43..32> I1700
TRUE CPUIMVP_BOOT2G_RC
TRUE GND TRUE WS_KBD7 53 TRUE
LPC_FRAME_L 16 45 47 89 96 MAKE_BASE=TRUE TRUE NC_FW2_TPAP 40 TRUE CPUIMVP_AXG2_SNUB I1745
I1110 I728 I766 I1702
TRUE CPUIMVP_BOOT3
I1111 TRUE WS_KBD8 53 I730 TRUE LPC_PWRDWN_L 17 45 47 TP_CPU_RSVD<27..26> TRUE NC_TP_CPU_RSVD<27..26> I769 TRUE NC_FW2_TPAN 40 I1701 TRUE CPUIMVP_BOOT1 I1739
MAKE_BASE=TRUE TRUE CPUIMVP_BOOT3_RC

I1112 TRUE WS_KBD9 53 I732 TRUE LPC_SERIRQ 16 45 47 I768 TRUE NC_FW0_TPBP 40 TRUE CPUIMVP_BOOT1_RC I1738
J5660 (RIGHT FAN CONN) TP_CPU_RSVD<24..15> NC_TP_CPU_RSVD<24..15> I1703
D
TRUE
WS_KBD10 NC_FW0_TPBN CPUIMVP_BOOT1G
D TRUE 53 TRUE PM_CLKRUN_L 17 45 47 MAKE_BASE=TRUE TRUE 40 TRUE
I1113 I731 I770 I1704
I1114 TRUE WS_KBD11 53 I734 TRUE PM_SYSRST_L 17 24 45 TP_CPU_RSVD<2..1> TRUE NC_TP_CPU_RSVD<2..1> I772 TRUE NC_FW0_TPAP 40 TRUE CPUIMVP_BOOT1G_R
I1493
TRUE PP5V_S0 6 7 MAKE_BASE=TRUE
I1705
TRUE CPUIMVP_UGATE1
I1115 TRUE WS_KBD12 53 TRUE SMC_ONOFF_L 45 46 53 I771 TRUE NC_ESTARLDO_EN TRUE CPUIMVP_LGATE1 I1746
TRUE FAN_RT_PWM 52
I1668
TP_CPU_RSVD_NCTF<8..5> TRUE NC_TP_CPU_RSVD_NCTF<8..5> I1707
TRUE CPUIMVP_UGATE1G
I1117 TRUE WS_KBD13 53 I737 TRUE SMC_RESET_L 45 46 47 65 MAKE_BASE=TRUE I774 TRUE NC_ALS_GAIN TRUE CPUIMVP_LGATE1G I1749
TRUE FAN_RT_TACH 52
I1706
TRUE CPUIMVP_UGATE2
TRUE WS_KBD14 53 TRUE SMC_RX_L 45 46 47 TRUE CPUIMVP_LGATE2 I1748
TRUE GND I1116

WS_KBD15_CAP
I739
SMC_TCK NC NO_TESTs 38 TP_FW643_AVREG TRUE NC_FW643_AVREG I1708
CPUIMVP_LGATE2G I1750 TRUE CPUIMVP_UGATE2G

I1118 TRUE 53 I738 TRUE 45 46 47 MAKE_BASE=TRUE TRUE
SMC_TDI NO_TEST 38 TP_FW643_TDI TRUE NC_FW643_TDI I1710
TRUE CPUIMVP_UGATE3
J6780 (MIC CONN) I1119 TRUE WS_KBD16_NUM 53 I740 TRUE 45 46 47 MAKE_BASE=TRUE TRUE CPUIMVP_LGATE3 I1751
17 TP_CRT_IG_BLUE TRUE NC_CRT_IG_BLUE I1709
J3501 & J3502 (AIRPORT/BT/CAMERA CONN) I1120 TRUE WS_KBD17 53 I741 TRUE SMC_TDO 45 46 47 MAKE_BASE=TRUE TP_DP_IG_C_HPD TRUE NC_DP_IG_C_HPD TRUE CPUIMVP_PH1_SNUB
17 TP_CRT_IG_GREEN TRUE NC_CRT_IG_GREEN MAKE_BASE=TRUE
I1711
TRUE DDRREG_TRIP
I557
TRUE BI_MIC_N 62 63 101 I1122 TRUE WS_KBD18 53 I742 TRUE SMC_TMS 45 46 47 MAKE_BASE=TRUE TP_DP_IG_C_CTRL_CLK TRUE NC_DP_IG_C_CTRL_CLK TRUE CPUIMVP_PH2_SNUB I1752
17 TP_CRT_IG_RED TRUE NC_CRT_IG_RED MAKE_BASE=TRUE

I1713
TRUE GFXIMVP_LGATE
I558 TRUE BI_MIC_SHIELD 62 63 I1121 TRUE WS_KBD19 53 I743 TRUE SMC_ROMBOOT 46 47 MAKE_BASE=TRUE TP_DP_IG_C_CTRL_DATA TRUE NC_DP_IG_C_CTRL_DATA I1712 TRUE CPUIMVP_PH3_SNUB I1753
MAKE_BASE=TRUE TRUE GFXIMVP_LL_RC

I559 TRUE BI_MIC_P 62 63 101 I1053 TRUE PCIE_AP_R2D_P 32 96 I1123 TRUE WS_KBD20 53 I744 TRUE SMC_TX_L 45 46 47 17 TP_DP_IG_C_MLP<3..0> TRUE NC_DP_IG_C_MLP<3..0> TRUE CPUIMVP_PHASE1 I1754
17 TP_CRT_IG_DDC_CLK TRUE NC_CRT_IG_DDC_CLK MAKE_BASE=TRUE

I1714
TRUE GFXIMVP_PHASE
TRUE GND 2 TPs I1052 TRUE PCIE_AP_R2D_N 32 96 I1124 TRUE WS_KBD21 53 I751 TRUE SPIROM_USE_MLB 19 47 56 MAKE_BASE=TRUE 17 TP_DP_IG_C_MLN<3..0> TRUE NC_DP_IG_C_MLN<3..0> TRUE CPUIMVP_PHASE1G I1755
17 TP_CRT_IG_DDC_DATA TRUE NC_CRT_IG_DDC_DATA MAKE_BASE=TRUE

I1716
TRUE GFXIMVP_PHASE_L
I1054 TRUE PCIE_CLK100M_AP_CONN_P 32 101 I1125 TRUE WS_KBD22 53 I752 TRUE SPI_ALT_CLK 47 MAKE_BASE=TRUE TP_DP_IG_C_AUXP TRUE NC_DP_IG_C_AUXP I1715 TRUE CPUIMVP_PHASE2 I1756
MAKE_BASE=TRUE TRUE GFXIMVP_UGATE

I1056 TRUE PCIE_CLK100M_AP_CONN_N 32 101 I1127 TRUE WS_KBD23 53 I760 TRUE SPI_ALT_CS_L 47 TP_DP_IG_C_AUXN TRUE NC_DP_IG_C_AUXN TRUE CPUIMVP_PHASE2G I1757
17 TP_CRT_IG_HSYNC TRUE NC_CRT_IG_HSYNC MAKE_BASE=TRUE

I1717
TRUE GFXIMVP_UGATE_R
J5100 I1055 TRUE AP_CLKREQ_Q_L 32 I1126 TRUE WS_KBD_ONOFF_L 53 I756 TRUE SPI_ALT_MISO 47 MAKE_BASE=TRUE TRUE CPUIMVP_PHASE3 I1759
17 TP_CRT_IG_VSYNC TRUE NC_CRT_IG_VSYNC 17 TP_DP_IG_D_HPD TRUE NC_DP_IG_D_HPD I1718

TRUE GFXIMVP_VBST
TRUE GND 6 TPs I1058 TRUE PCIE_WAKE_L 17 24 32 I1128 TRUE WS_LEFT_SHIFT_KBD 53 I1292 TRUE SPI_ALT_MOSI 47 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE CPUIMVP_SKIP I1758
17 TP_DP_IG_D_CTRL_CLK TRUE NC_DP_IG_D_CTRL_CLK I1719

TRUE GFXIMVP_VBST_R
I1672 TRUE PP5V_S0 6 7 I1496 TRUE WIFI_EVENT_L 32 45 46 I1129 TRUE WS_LEFT_OPTION_KBD 53 I1288 TRUE SYS_LED_ANODE_R 41 MAKE_BASE=TRUE TRUE CPUIMVP_SLEW I1760
17 TP_LVDS_IG_CTRL_CLK TRUE NC_LVDS_IG_CTRL_CLK 17 TP_DP_IG_D_CTRL_DATA TRUE NC_DP_IG_D_CTRL_DATA I1720

TRUE GPUFB_BOOT_RC
I1671
TRUE PP3V42_G3H 6 7 I1057 TRUE AP_RESET_CONN_L 32 I1130 TRUE WS_CONTROL_KBD 53 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE CPUIMVP_TONA I1762
17 TP_LVDS_IG_CTRL_DATA TRUE NC_LVDS_IG_CTRL_DATA 17 TP_DP_IG_D_MLP<3..0> TRUE NC_DP_IG_D_MLP<3..0> I1721

TRUE GPUFB_DRVH
I1059 TRUE PP3V3_WLAN 32 46 6 TPs TRUE GND MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE CPUIMVP_TONB I1761
17 TP_PCH_LVDS_VBG TRUE NC_PCH_LVDS_VBG 17 TP_DP_IG_D_MLN<3..0> TRUE NC_DP_IG_D_MLN<3..0> I1722

TRUE GPUFB_DRVL
J6781 & J6782 (SPEAKERS CONN) I1061 TRUE PP5V_S3_ALSCAMERA_F 32 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE CPUIMVP_VSWG1 I1764
17 TP_DP_IG_D_AUXP TRUE NC_DP_IG_D_AUXP I1723

TRUE GPUFB_LL
I1060 TRUE SMBUS_SMC_2_S3_SDA 6 45 48 99 J6950 (BIL CABLE CONN) MAKE_BASE=TRUE TRUE CPUIMVP_VSWG2 I1763
I989 TRUE SPKRCONN_L_OUT_P 61 62 101 17 TP_DP_IG_D_AUXN TRUE NC_DP_IG_D_AUXN I1724

TRUE GPUFB_VBST
I1063 TRUE SMBUS_SMC_2_S3_SCL 6 45 48 99 16 TP_HDA_SDIN1 TRUE NC_HDA_SDIN1 MAKE_BASE=TRUE TRUE CPUVCCIOS0_BOOT_RC I1765
I990 TRUE SPKRCONN_L_OUT_N 61 62 101 I1150 TRUE PP5V_S3_IR_R 6 41 MAKE_BASE=TRUE

I1725
TRUE P1V05_GPU_DRVL
I1062 TRUE USB_CAMERA_CONN_P 32 95 16 TP_HDA_SDIN2 TRUE NC_HDA_SDIN2 TRUE CPUVCCIOS0_DRVH I1767
I992 TRUE SPKRCONN_R_OUT_P 61 62 101 I1149 TRUE SMC_LID_R 6 64 MAKE_BASE=TRUE 17 TP_SDVO_TVCLKINN TRUE NC_SDVO_TVCLKINN I1726
TRUE P1V05_GPU_DRVH
I1064 TRUE USB_CAMERA_CONN_N 32 95 16 TP_HDA_SDIN3 TRUE NC_HDA_SDIN3 MAKE_BASE=TRUE TRUE CPUVCCIOS0_DRVL I1766
I991 TRUE SPKRCONN_R_OUT_N 61 62 101 I1151 TRUE IR_RX_OUT 6 41 44 MAKE_BASE=TRUE 17 TP_SDVO_TVCLKINP TRUE NC_SDVO_TVCLKINP I1727
TRUE P1V05_GPU_LL
TRUE GND 10 TPs MAKE_BASE=TRUE TRUE CPUVCCIOS0_FB I1768
I994 TRUE SPKRCONN_S_OUT_P 61 62 101 I1152 TRUE SYS_LED_ANODE 41 46 NO_TEST=TRUE 33 6 TP_DP_TBTSRC_AUXCH_CP TP_DP_TBTSRC_AUXCH_CP 17 TP_SDVO_STALLN NC_SDVO_STALLN
I1728
CPUVCCIOS0_LL I1770 TRUE P1V05_GPU_VBST

TRUE 6 33 TRUE TRUE
I993 TRUE SPKRCONN_S_OUT_N 61 62 101 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1730
TRUE P1V05_GPU_BOOT_RC
TRUE GND 33 6 TP_DP_TBTSRC_AUXCH_CN TRUE TP_DP_TBTSRC_AUXCH_CN 6 33 17 TP_SDVO_STALLP TRUE NC_SDVO_STALLP TRUE CPUVCCIOS0_OCSET I1769
C GND TBT_R2D_C_P<1..0>
C
I1729
TRUE 4 TPs I1481 TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE P1V8S0_FB
33 6 TP_TBT_PCIE_RESET0_L TRUE NC_TBT_PCIE_RESET0_L TRUE CPUVCCIOS0_RTN I1772
J9000 (LVDS CONN) I1483 TRUE TBT_R2D_C_N<1..0> MAKE_BASE=TRUE 17 TP_SDVO_INTN TRUE NC_SDVO_INTN I1731
TRUE P1V8S0_SW
33 6 TP_TBT_PCIE_RESET1_L TRUE NC_TBT_PCIE_RESET1_L MAKE_BASE=TRUE TRUE CPUVCCIOS0_VBST I1771
I1663 TRUE PP3V3_S3RS4_BT_F 32 MAKE_BASE=TRUE 17 TP_SDVO_INTP TRUE NC_SDVO_INTP I1732

TRUE P3V3S5_CSP2_R
33 6 TP_TBT_PCIE_RESET2_L TRUE NC_TBT_PCIE_RESET2_L MAKE_BASE=TRUE TRUE DC_TEST_B3_C2 I1773
TRUE USB_BT_CONN_P 32 95 MAKE_BASE=TRUE

I1734
TRUE P3V3S5_DRVH
I995 TRUE PP3V3_SW_LCD 85 2 TP needed
I1664
33 6 TP_TBT_PCIE_RESET3_L TRUE NC_TBT_PCIE_RESET3_L TRUE DDRREG_DRVH I1775
TRUE USB_BT_CONN_N 32 95 TRUE TBTDPA_ML_P<3..0> MAKE_BASE=TRUE TP_GPU_BUFRST_L TRUE NC_GPU_BUFRST_L I1735

TRUE P3V3S5_DRVL
I996 TRUE PP3V3_S0 6 7 101
I1665
POWER RAILS I1486
TBTDPA_ML_N<3..0> TP_TBT_MONDC0 NC_TBT_MONDC0 TP_GPU_GSTATE<0> MAKE_BASE=TRUE

NC_GPU_GSTATE<0> I1736 TRUE DDRREG_DRVL I1774
P3V3S5_LL
TRUE 33 TRUE TRUE TRUE
I997 TRUE PPVOUT_S0_LCDBKLT 8 85 104 3 TP needed FUNC_TEST
I1485
MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE DDRREG_FB I1776
I1488 TRUE DP_TBTSNK0_AUXCH_C_P 33 81 98 33 TP_TBT_MONDC1 TRUE NC_TBT_MONDC1 TP_GPU_GSTATE<1> TRUE NC_GPU_GSTATE<1> I1733
I1777 TRUE P3V3S5_SNUBR
I998 TRUE LVDS_DDC_CLK 85 86 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE DDRREG_LL
J6950 (BAT CONN) TRUE PM_SLP_S3_L 17 26 45 TRUE DP_TBTSNK0_AUXCH_C_N 33 81 98 33 TP_TBT_MONOBSP TRUE NC_TBT_MONOBSP TP_GPU_MIOA_D<9..0> TRUE NC_GPU_MIOA_D<9..0> I1737
TRUE P3V3S5_TG
I1000 TRUE LVDS_DDC_DATA 85 86
I640
74 I1487
MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE P3V3S5_VBST I1778
TRUE PP0V75_S0_DDRVTT 7 TRUE DP_TBTSNK0_AUXCH_P 33 98 33 TP_TBT_MONOBSN TRUE NC_TBT_MONOBSN TP_GPU_MIOA_DE TRUE NC_GPU_MIOA_DE I1779
TRUE P5V5G3H_BOOST
I1001 TRUE LVDS_CONN_A_DATA_P<0> 85 86 100 I1510
TRUE SYS_DETECT_L 6 64
I602 I1489
MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE P3V3S5_VFB2 I1805
TRUE PP1V05_S0 7 TRUE DP_TBTSNK0_AUXCH_N 33 98 33 6 TP_DP_TBTSRC_ML_CP<0..3> TRUE NC_DP_TBTSRC_ML_CP<0..3> I1785

TRUE P5V5G3H_SW
I1002 TRUE LVDS_CONN_A_DATA_N<0> 85 86 100
I604 I1491
MAKE_BASE=TRUE TRUE P3V42G3H_SW I1806
TRUE PP1V05_S0GPU 7 TRUE DP_TBTSNK0_ML_C_P<3..0> 33 81 98 33 6 TP_DP_TBTSRC_ML_CN<0..3> TRUE NC_DP_TBTSRC_ML_CN<0..3> I1787
I1004 TRUE LVDS_CONN_A_DATA_P<1> 85 86 100

I605 I1490
MAKE_BASE=TRUE TRUE P5VS3_CSP1_R
J5800 (IPD FLEX CONN) TRUE PP1V0_FW_FWPHY 7 TRUE DP_TBTSNK0_ML_C_N<3..0> 33 81 98
I1786
I1003 TRUE LVDS_CONN_A_DATA_N<1> 85 86 100

I606 I1492
NO_TEST TP_LVDS_EG_BKL_PWM TRUE NC_LVDS_EG_BKL_PWM TRUE P5VS3_DRVH
TRUE PP1V2_ENET 7 TRUE DP_TBTSNK0_ML_P<3..0> 33 98 MAKE_BASE=TRUE
I1789
TRUE DMI_S2N_N<3>
I1005 TRUE LVDS_CONN_A_DATA_P<2> 85 86 100 I1659
TRUE PP18V5_Z2 54
I610 I1563
TRUE TP_AUD_GPIO_2 8 TP_LVDS_IG_B_CLKN TRUE NC_LVDS_IG_B_CLKN TRUE P5VS3_DRVL I1807
TRUE PP1V2_S0 7 TRUE DP_TBTSNK0_ML_N<3..0> 33 98

I1632
MAKE_BASE=TRUE
I1788
TRUE DMI_S2N_P<3>
I1007 TRUE LVDS_CONN_A_DATA_N<2> 85 86 100 I1660
TRUE PP3V3_S4 6 7
I612 I1562
TRUE TP_AUD_GPIO_1 8 TP_LVDS_IG_B_CLKP TRUE NC_LVDS_IG_B_CLKP TRUE P5VS3_LL I1809
TRUE PP1V5_S3 7 TRUE DP_TBTSNK1_AUXCH_C_P 33 81 98

I1634
MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM
I1784
TRUE DMI_S2N_N<1..0>
I1006 TRUE LVDS_CONN_A_CLK_F_P 85 100 I1509 TRUE PP5V_S5_CUMULUS 54
I611 I1564
TRUE TP_AUD_LO1_L_N 8 TP_LVDS_IG_BKL_PWM TRUE TRUE P5VS3_SNUBR I1808
TRUE DP_TBTSNK1_AUXCH_C_N 33 81 98
I1633
MAKE_BASE=TRUE
I1782
TRUE DMI_S2N_P<1..0>
I1009 TRUE LVDS_CONN_A_CLK_F_N 85 100 I1086 TRUE Z2_HOST_INTN 53 54
I1566
TRUE TP_AUD_LO1_L_P TRUE P5VS3_TG I1810
TRUE PP1V8_S0 7 TRUE DP_TBTSNK1_AUXCH_P 33 98

I1636 I1783
TRUE DMI_N2S_N<3..1>
I1008 TRUE LVDS_CONN_B_DATA_P<0> 85 86 100 I1508 TRUE Z2_MOSI 53 54
I623 I1565
TRUE TP_BKL_FAULT 90 TRUE P5VS3_VBST I1812
TRUE PP3V3_ENET 7 TRUE DP_TBTSNK1_AUXCH_N 33 98

I1635 I1781
TRUE DMI_N2S_P<3..1>
I1010 TRUE LVDS_CONN_B_DATA_N<0> 85 86 100 I1273 TRUE Z2_CS_L 53 54
I620 I1567
TRUE TP_SPI_DESCRIPTOR_OVERRIDE_L TRUE P5VS3_VFB1 I1811
TRUE PP3V3_FW_FWPHY 7 TRUE DP_TBTSNK1_ML_C_P<3..0> 33 81 98

I1637
TRUE MEM_A_BA<2..0> 11 27 94 TRUE MEM_B_BA<2..0> 11 29 94
I1780
I1011 TRUE LVDS_CONN_B_DATA_P<1> 85 86 100 I1089 TRUE Z2_DEBUG3 53 54

I621 I1569
TRUE TP_XDPPCH_HOOK2 23
I1513 I1524
TRUE PCHVCCIOS0_BOOT_RC
TRUE PP3V3_S0 6 7 101 TRUE DP_TBTSNK1_ML_C_N<3..0> 33 81 98
I1638
TRUE MEM_A_CKE<1..0> 11 27 94 TRUE MEM_B_CKE<1..0> 11 29 94
I1790
I1012 TRUE LVDS_CONN_B_DATA_N<1> 85 86 100 I1088 TRUE Z2_MISO 53 54

I618 I1568
I1639 TRUE TP_XDPPCH_HOOK3 23
I1514 I1523
TRUE DP_TBTSNK1_ML_P<3..0> 33 98 TRUE MEM_A_CLK_N<1..0> 11 27 94 TRUE MEM_B_CLK_N<1..0> 11 29 94 TRUE PCHVCCIOS0_DRVH

TRUE LVDS_CONN_B_DATA_P<2> 85 86 100 TRUE Z2_BOOST_EN 54
I1570
TRUE TP_GMUX_PL6B 89
I1515 I1522 I1793
I1014 I1090
TRUE PP3V3_S3 7 TRUE DP_TBTSNK1_ML_N<3..0> 33 98
I1641
TRUE MEM_A_CLK_P<1..0> 11 27 94 TRUE MEM_B_CLK_P<1..0> 11 29 94 TRUE PCHVCCIOS0_DRVL
TRUE LVDS_CONN_B_DATA_N<2> 85 86 100 TRUE Z2_SCLK 53 54
I615 I1571 I1516 I1521 I1792
I1013 I1464
TRUE PP3V3_S5 7 101 TRUE TP_DP_TBTSRC_AUXCH_CN 6 33 TRUE MEM_A_CS_L<1..0> 11 27 94 TRUE MEM_B_CS_L<1..0> 11 29 94 TRUE PCHVCCIOS0_FB
I1015 TRUE LVDS_CONN_B_CLK_F_P 85 100 I1098 TRUE Z2_CLKIN 53 54
I616 I1572
TRUE CPUIMVP_BOOT1 6 69 70
I1517 I1525 I1794
TRUE PP3V3_S5_AVREF_SMC 45 46 TRUE TP_DP_TBTSRC_AUXCH_CP 6 33

I1642
TRUE MEM_A_ODT<1..0> 11 27 94 TRUE MEM_B_ODT<1..0> 11 29 94 TRUE PCHVCCIOS0_LL
I1016 TRUE LVDS_CONN_B_CLK_F_N 85 100 I1097 TRUE Z2_KEY_ACT_L 53 54
I614 I1573
TRUE CPUIMVP_BOOT2 6 69 70
I1518 I1526 I1795
TRUE PP3V42_G3H 6 7 TRUE TP_DP_TBTSRC_ML_CP<3..0> 6 33

I1644
TRUE MEM_A_SA<1..0> 27 TRUE MEM_B_SA<1..0> 29 TRUE PCHVCCIOS0_OCSET
I1017 TRUE LED_RETURN_1 85 90 I1095 TRUE Z2_RESET 53 54
I627 I1574
TRUE CPUIMVP_UGATE2 6 69 70
I1519 I1527 I1796
TRUE PP5V_S0 6 7 TRUE TP_DP_TBTSRC_ML_CN<3..0> 6 33

I1643
TRUE MEM_A_DQ<63..0> 11 28 94 TRUE MEM_B_DQ<63..0> 11 28 94 TRUE PCHVCCIOS0_VBST
I1018 TRUE LED_RETURN_2 85 90 I1096 TRUE PSOC_F_CS_L 53 54
I626 I1575
TRUE TP_1V05_S0_PCH_VCCAPLLEXP 20
I1520 I1528 I1797
PP5V_S3 DP_SDRVA_ML_C_P<0> I1645

MEM_A_DQS_N<7..0> MEM_B_DQS_N<7..0> PPVCORE_S0_CPU_PH1_L
B B
TRUE 7 TRUE 87 98 TRUE 11 28 94 TRUE 11 28 94 TRUE
I1019 TRUE LED_RETURN_3 85 90 I1092 TRUE PICKB_L 53 54
I639 I1576 I1529 I1531 I1798
TRUE DP_SDRVA_ML_C_N<0> 87 98 18 TP_PCI_PME_L TRUE NC_PCI_PME_L TRUE MEM_A_DQS_P<7..0> 11 28 94 TRUE MEM_B_DQS_P<7..0> 11 28 94 TRUE PPVCORE_S0_CPU_PH2_L
I1020 TRUE LED_RETURN_4 85 90 I1093 TRUE PSOC_MISO 53 54
I1577
MAKE_BASE=TRUE
I1530 I1532 I1800
TRUE PPBUS_G3H 7 TRUE DP_SDRVA_ML_C_P<2> 87 98 18 TP_PCI_CLK33M_OUT3 TRUE NC_PCI_CLK33M_OUT3 TRUE PPVCORE_S0_CPU_PH3_L

I1022 TRUE LED_RETURN_5 85 90 I1094 TRUE PSOC_MOSI 53 54
I637 I1578
MAKE_BASE=TRUE TRUE FB_A0_DQ<31..0> 77 79 100 TRUE FB_B0_DQ<31..0> 77 80 100
I1799
TRUE PPDCIN_G3H 7 TRUE DP_SDRVA_ML_C_N<2> 87 98

I1536 I1546
TRUE VCCSAS0_B00T_RC
I1021 TRUE LED_RETURN_6 85 90 I1099 TRUE PSOC_SCLK 53 54
I636 I1579
16 TP_PCIE_CLK100M_PE4N TRUE NC_PCIE_CLK100M_PE4N I1535 TRUE FB_A0_A<8..0> 77 79 100 I1547 TRUE FB_B0_A<8..0> 77 80 100
I1801
TRUE PPVCORE_GPU 7 TRUE DP_SDRVA_ML_P<0> 87 98 MAKE_BASE=TRUE TRUE VCCSAS0_DRVL

TRUE GND 8 TPs I1100 TRUE SMBUS_SMC_2_S3_SCL 6 45 48 99
I709 I1580
16 TP_PCIE_CLK100M_PE4P TRUE NC_PCIE_CLK100M_PE4P I1534 TRUE FB_A0_ABI_L 77 79 100 I1548 TRUE FB_B0_ABI_L 77 80 100
I1803
I714 TRUE PPVCORE_S0_CPU 7 TRUE DP_SDRVA_ML_N<0> 87 98 MAKE_BASE=TRUE TRUE VCCSAS0_LL

I1101 TRUE SMBUS_SMC_2_S3_SDA 6 45 48 99
I1581
16 TP_PCIE_CLK100M_PE5N TRUE NC_PCIE_CLK100M_PE5N TRUE FB_A0_EDC<3..0> 77 79 100 TRUE FB_B0_EDC<3..0> 77 80 100
I1802
I1160 TRUE PPVP_FW 7 TRUE DP_SDRVA_ML_P<2> 87 98 MAKE_BASE=TRUE

I1533 I1549
TRUE VCCSAS0_VBST
TRUE GND I1583
16 TP_PCIE_CLK100M_PE5P TRUE NC_PCIE_CLK100M_PE5P TRUE FB_A0_WCLK_N<1..0> 77 79 100 TRUE FB_B0_WCLK_N<1..0> 77 80 100
I1804
J4500 (SATA ODD CONN) 2 TPs needed I1161 TRUE PPVTTDDR_S3 7 I1582 TRUE DP_SDRVA_ML_N<2> 87 98 MAKE_BASE=TRUE
I1537 I1550
TP_PCIE_CLK100M_PE6N TRUE NC_PCIE_CLK100M_PE6N TRUE FB_A0_WCLK_P<1..0> 77 79 100 TRUE FB_B0_WCLK_P<1..0> 77 80 100

I1024 TRUE PP5V_SW_ODD 41 4 TPs I1584 TRUE TP_TBT_PCIE_RESET0_L 6 33 MAKE_BASE=TRUE
I1539 I1551
TRUE USB3_EXTB_RX_N
TP_PCIE_CLK100M_PE6P TRUE NC_PCIE_CLK100M_PE6P TRUE FB_A0_DBI_L<3..0> 77 79 100 TRUE FB_B0_DBI_L<3..0> 77 80 100 TRUE USB3_EXTA_RX_N I1823
I1026 TRUE SMC_ODD_DETECT 41 45 I1585 TRUE TP_TBT_PCIE_RESET1_L 6 33 MAKE_BASE=TRUE

I1558 I1559 I1813
TRUE USB3_EXTB_RX_P
TP_PCIE_CLK100M_PE7N TRUE NC_PCIE_CLK100M_PE7N TRUE FB_A1_DQ<31..0> 77 79 100 TRUE FB_B1_DQ<31..0> 77 80 100 TRUE USB3_EXTA_RX_P I1825
I1025 TRUE SATA_ODD_D2R_C_P 41 95 I1587 TRUE TP_TBT_PCIE_RESET2_L 6 33 MAKE_BASE=TRUE

I1540 I1552 I1814
TRUE USB3_EXTB_RX_F_N
TP_PCIE_CLK100M_PE7P TRUE NC_PCIE_CLK100M_PE7P TRUE FB_A1_A<8..0> 77 79 100 TRUE FB_B1_A<8..0> 77 80 100 TRUE USB3_EXTA_RX_F_N I1824
I1028 TRUE SATA_ODD_D2R_C_N 41 95 I1588 TRUE TP_TBT_PCIE_RESET3_L 6 33 MAKE_BASE=TRUE

I1541 I1554 I1815
TRUE USB3_EXTB_RX_F_P
53 TP_PSOC_P1_3 TRUE NC_PSOC_P1_3 TRUE FB_A1_ABI_L 77 79 100 TRUE FB_B1_ABI_L 77 80 100 TRUE USB3_EXTA_RX_F_P I1826
I1027 TRUE SATA_ODD_R2D_P 41 95 I1589 TRUE PEG_D2R_C_P<7..0> 75 93 MAKE_BASE=TRUE

I1542 I1553 I1816
TRUE USB3_EXTB_TX_N
J6900 (DC POWER CONN) TP_SATA_B_D2RN TRUE NC_SATA_B_D2RN TRUE FB_A1_EDC<3..0> 77 79 100 TRUE FB_B1_EDC<3..0> 77 80 100 TRUE USB3_EXTA_TX_N I1827
I1029 TRUE SATA_ODD_R2D_N 41 95 TRUE PEG_D2R_C_N<7..0> 75 93 MAKE_BASE=TRUE

I1543 I1555 I1818
TRUE USB3_EXTB_TX_C_N
I1131 TRUE ADAPTER_SENSE 64
I1586
TP_SATA_B_D2RP TRUE NC_SATA_B_D2RP TRUE FB_A1_WCLK_N<1..0> 77 79 100 TRUE FB_B1_WCLK_N<1..0> 77 80 100 TRUE USB3_EXTA_TX_C_N I1828
TRUE GND 7 TPs TRUE PEG_R2D_P<7..0> 75 92 93 MAKE_BASE=TRUE

I1544 I1557 I1817
TRUE USB3_EXTB_TX_F_N
I1132 TRUE PP18V5_DCIN_FUSE 64 2 TPs
I1590
TP_SATA_B_R2D_CN TRUE NC_SATA_B_R2D_CN TRUE FB_A1_WCLK_P<1..0> 77 79 100 TRUE FB_B1_WCLK_P<1..0> 77 80 100 TRUE USB3_EXTA_TX_F_N I1830
TRUE PEG_R2D_N<7..0> 75 92 93 MAKE_BASE=TRUE

I1545 I1556 I1819
TRUE USB3_EXTB_TX_P
J4501 (SATA HDD CONN)
GND
NC NO_TESTs I1833
TP_SATA_B_R2D_CP TRUE
MAKE_BASE=TRUE
NC_SATA_B_R2D_CP I1560
TRUE FB_A1_DBI_L<3..0> 77 79 100 I1561
TRUE FB_B1_DBI_L<3..0> 77 80 100 I1820
TRUE USB3_EXTA_TX_P I1829
USB3_EXTB_TX_C_P
TRUE 2 TPs TRUE
4 TPs NO_TEST 16 TP_SATA_D_D2RN TRUE NC_SATA_D_D2RN TRUE USB3_EXTA_TX_C_P I1831
I1032 TRUE PP5V_S0_HDD_FLT 41 MAKE_BASE=TRUE

I1821
TRUE USB3_EXTB_TX_F_P
16 TP_SATA_D_D2RP TRUE NC_SATA_D_D2RP TRUE USB3_EXTA_TX_F_P I1832
I1031 TRUE SATA_HDD_R2D_P 41 95 J6950 (MAIN BATT CONN) MAKE_BASE=TRUE TRUE MEM_A_A<15..0> 11 27 94
I1822
3 TPs 16 TP_SATA_D_R2D_CN TRUE NC_SATA_D_R2D_CN I1436
I1033 TRUE SATA_HDD_R2D_N 41 95 I1134 TRUE PPVBAT_G3H_CONN 64 I1598

TRUE TP_FW643_VAUX_ENABLE 38 MAKE_BASE=TRUE TRUE MEM_A_CAS_L 11 27 94
65 16 TP_SATA_D_R2D_CP TRUE NC_SATA_D_R2D_CP I1437
I1035 TRUE SATA_HDD_D2R_C_N 41 95 I1136 TRUE SMBUS_SMC_5_G3_SCL 6 45 48 99 I1600

TRUE TP_FW643_VBUF 38 MAKE_BASE=TRUE TRUE MEM_A_RAS_L 11 27 94
16 TP_SATA_E_D2RN TRUE NC_SATA_E_D2RN I1438
I1034 TRUE SATA_HDD_D2R_C_P 41 95 I1135 TRUE SMBUS_SMC_5_G3_SDA 6 45 48 99 I1613

TRUE TP_FW643_SCIFCLK 38 I1601
TRUE TP_FW643_TCK 38 MAKE_BASE=TRUE TRUE MEM_A_WE_L 11 27 94
16 TP_SATA_E_D2RP TRUE NC_SATA_E_D2RP I1439
TRUE SYS_DETECT_L 6 64 TRUE TP_FW643_SCIFDAIN 38 TRUE TP_FW643_TDO 38 MAKE_BASE=TRUE TRUE MEM_B_A<15..0> 11 29 94

TRUE GND 8 TPs
I1669 I1612 I1602
16 TP_SATA_E_R2D_CN TRUE NC_SATA_E_R2D_CN I1440
TRUE GND 7 TPs I1614

TRUE TP_FW643_SCIFDOUT 38 I1599
TRUE TP_FW643_TMS 38 MAKE_BASE=TRUE TRUE MEM_B_CAS_L 11 29 94
16 TP_SATA_E_R2D_CP TRUE NC_SATA_E_R2D_CP I1441
TRUE TP_FW643_SCIFMC 38 TRUE TP_SMC_P10 MAKE_BASE=TRUE TRUE MEM_B_RAS_L 11 29 94

I1689 TRUE IR_RX_OUT 6 41 44
I1615 I1603
16 TP_SATA_F_D2RN TRUE NC_SATA_F_D2RN I1442
TRUE TP_FW643_SDA 38 TRUE TP_P7_7 53 MAKE_BASE=TRUE TRUE MEM_B_WE_L 11 29 94

TRUE PP5V_S3_IR_R 6 41
I1592 I1605
16 TP_SATA_F_D2RP TRUE NC_SATA_F_D2RP I1443
A
I1690
A
TRUE TP_FW643_SE 38 TRUE TP_PSOC_SCL 53 MAKE_BASE=TRUE
I1691 TRUE SSD_OOBD2R_L 41
I1591 I1604
16 TP_SATA_F_R2D_CN TRUE NC_SATA_F_R2D_CN
TRUE TP_FW643_SM 38 TRUE TP_PSOC_SDA 53 MAKE_BASE=TRUE SYNC_MASTER=K18_MLB SYNC_DATE=04/27/2010
TRUE SSD_OOBR2D_L 41
I1593 I1606
16 TP_SATA_F_R2D_CP TRUE NC_SATA_F_R2D_CP
I1692
TRUE TP_FW643_CE 38 TRUE TP_SMC_P24 MAKE_BASE=TRUE
PAGE TITLE
I1594 I1607
J6955 (BAT LED CONN)

3 TPs
I1595 TRUE TP_FW643_FW620_L 38 I1631 TRUE DC_TEST_BH1_BG2 12 TP_SMC_P41 TRUE
MAKE_BASE=TRUE
NC_SMC_P41 Functional / ICT Test
I1140 TRUE PP3V42_G3H 6 I1596 TRUE TP_FW643_JASI_EN 38 I1630 TRUE DC_TEST_BH3_BJ2 12 PCH ALIASES DRAWING NUMBER SIZE
7
I1142 TRUE SMBUS_SMC_5_G3_SDA 6 45 48 99 I1617 TRUE DMI_S2N_N<1> I1624 TRUE TP_USB_HUB1_OCS1 NC_LPC_DREQ0_L
MAKE_BASE=TRUE
TP_LPC_DREQ0_L 16
93
J5815 (KBD BACKLIGHT CONN) I1141 TRUE SMBUS_SMC_5_G3_SCL 6 45 48 99 I1616
TRUE DMI_S2N_P<1> 6 9 I1623 TRUE TP_USB_HUB1_PRTPWR1 REVISION
17 TP_CLINK_CLK NC_CLINK_CLK
TRUE KBDLED_ANODE 54
2 TPs I1143 TRUE SMC_BIL_BUTTON_L 45 46 64 I1618
TRUE FDI_DATA_N<1> 9
17
I1625
TRUE TP_USB_HUB2_OCS1
16
16 TP_CLINK_DATA
TRUE
MAKE_BASE=TRUE
TRUE NC_CLINK_DATA
R
3.0.0
I1145
SMC_KDBLED_PRESENT_L I1673 TRUE SMC_LID_R 6 64 I1619 TRUE FDI_DATA_P<1> 93
93 I1626 TRUE TP_USB_HUB2_PRTPWR1
TP_CLINK_RESET_L
MAKE_BASE=TRUE
NC_CLINK_RESET_L
I1146 TRUE 54 17 16 TRUE
TRUE FDI_FSYNC<1..0> 9 TRUE TP_DC_TEST_A62 12 MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
TRUE GND 7 TPs
I1620
93
I1627
TRUE GND I1622 TRUE FDI_LSYNC<1..0> 9 I1629 TRUE TP_DC_TEST_D65 12 16 TP_PCIE_CLK100M_PEBN TRUE NC_PCIE_CLK100M_PEBN THE POSESSOR AGREES TO THE FOLLOWING: PAGE
17
I1621 TRUE FDI_INT 9 17 93 16 TP_PCIE_CLK100M_PEBP
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PEBP I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
7 OF 132
TRUE FDI_DATA_N<7..4> 9 17 93 SHEET
I1834 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I1835
TRUE FDI_DATA_P<7..4> 9 17 93 IV ALL RIGHTS RESERVED 6 OF 105
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
65 64 =PPBUS_G3H PPBUS_G3H 6 67 =PP3V3_S5_REG PP3V3_S5 6 101 1.8V/1.5V/1.2V/1.05V Rails
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE 72 =PP1V8_S0_REG PP1V8_S0 6 "GPU" Rails
G3H Rails =PPBUS_S0_LCDBKLT =PP3V3_GPU_P3V3GPUFET
MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V
90 73 2A max supply MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
73 =PP3V3_S0GPU_FET PP3V3_S0GPU_FET
=PPBUS_S5_FWPWRSW 39 =PP3V3_S0_P3V3S0FET 73 =PP1V8_S0_GMUX 89 MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM
=PPVIN_S5_HS_OTHER_ISNS_R 50 =PP3V3_S3_P3V3S3FET 73 =PP1V8_S0_GPUFET 73 VOLTAGE=3.3V
MAKE_BASE=TRUE
=PPVIN_S5_HS_COMPUTING_ISNS_R 50 =PP3V3_S4_P3V3S4FET 73 =PP1V8_S0_PCH_VCCTX_LVDS 22
=PP3V3_S0GPU_ISNS_R 104
=PPVIN_S5_HS_GPU_ISNS_R 50 =PP3V3_S5_SYSCLK 24 =PP1V8_S0_PCH_VCC_DFTERM 19 20 22
104 =PP3V3_S0GPU_ISNS PP3V3_S0GPU
=PPVIN_SW_TBTBST 8 35 =PP3V3_S5_LCD 85 =PP1V8_S0_CPU_VCCPLL 14 MIN_LINE_WIDTH=0.3 MM
=PPBUS_S0_VSENSE 49 =PP3V3_FW_P3V3FWFET 39 =PP1V8R1V5_S0_PCH_VCCVRM 20 VOLTAGE=3.3V
MAKE_BASE=TRUE
50 =PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS =PP3V3_S5_P1V2P1V8 72 =PPVDDIO_S0_SBCLK 24
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE =PP3V3_GPU_IFPX_PLLVDD 81
=PP3V3_S5_PCH 17 14 12 =PP1V8_S0_CPU_VCCPLL_R PP1V8_S0_CPU_VCCPLL_R
=PPVIN_S0_CPUIMVP 69 70 MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.8V =PP3V3_GPU_LVDS_DDC 86
=PP3V3_S5_PCHPWRGD 92 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PPVIN_S3_DDRREG =PP3V3_S0_GFX3V3BIAS
D =PPVIN_S0_CPUVCCIOS0
68
71
=PP3V3_S5_PCH_GPIO
=PP3V3_S5_CPU_VCCDDR
19
26
68 =PPDDR_S3_REG PP1V5_S3_REG
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP3V3_GPU_VDD33
84
75 81 82 83 D
=PPVIN_S0_CPUAXG 70 =PP3V3_GPU_OSC
=PP3V3_S5_MEMVDDSEL =PP1V5_S3_ISNS_R 103
=PPVIN_S0_VCCSAS0 66
=PP3V3_S5_PCH_VCCDSW 20 22 103 =PP1V5_S3_ISNS PP1V5_S3 6
=PPVIN_S0_PCHVCCIOS0 MIN_LINE_WIDTH=0.8 MM VOLTAGE=1.5V
=PP3V3_S5_VMON 74 MIN_NECK_WIDTH=0.1 MM MAKE_BASE=TRUE
50 =PPVIN_S5_HS_GPU_ISNS PPVIN_S5_HS_GPU_ISNS 73 =PP1V8_GPU_FET PP1V8_S0GPU
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V =PP3V3_S5_XDP 23 =PP1V5_S3_DDR_ISNS_R 49 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE MIN_NECK_WIDTH=0.15 MM
=PP3V3_S5_P3V3SUSFET 73 =PPVIN_S3_P1V5S3RS0_FET 73 VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP3V3_S5_PWRCTL 74 73 =PP1V5_S3RS0_FET PP1V5_S3RS0 101
=PPVIN_S0GPU_P1V5 78 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V =PP1V8_GPU_IFPAB_IOVDD 81
=PP3V3_S5_P1V5S0 72 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PPVIN_S0_GFXIMVP 84
=PP3V3_S5_SMCBATLOW 46 =PP1V5_S3_CPU_VCCDDR 10 13 15 26
=PPVIN_S0GPU_P1V05 78
=PP3V3_S4_TBTAPWRSW 88
49 =PP1V5_S3_DDR_ISNS PP1V5_S3_DDR
50 =PPVIN_S5_HS_OTHER_ISNS PPVIN_S5_HS_OTHER_ISNS MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V 73 =PP3V3_S3_FET PP3V3_S3_FET MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE =PP1V5_S3_MEMRESET 26
=PPVIN_S5_P5VP3V3 67
=PP3V3_S3_ISNS_R 104 =PP1V5_S3_MEM_A 27
64 =PP18V5_DCIN_CONN PPDCIN_G3H 6
MIN_LINE_WIDTH=0.6 MM VOLTAGE=18.5V =PP1V5_S3_MEM_B 29
MIN_NECK_WIDTH=0.25 MM MAKE_BASE=TRUE 104 103 49 7 =PP3V3_S3_ISNS PP3V3_S3 6
MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V =PPVIN_S0_DDRREG_LDO 68
=PPDCIN_S5_CHGR 65 MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE
=PPDDR_S3_MEMVREF 31 103 78 =PP1V5R1V35_GPU_REG PPGPUFB_S0
=PPDCIN_S5_VSENSE 49 =PP3V3_S3_BT MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
64 =PP3V42_G3H_REG PP3V42_G3H 6 =PP3V3_S3_GMUX 89 72 =PP1V5_S0_REG PP1V5_S0
MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V MIN_LINE_WIDTH=0.6 MM =PP1V35_GPU_FBVDDQ 76 79 80
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S3_MEMRESET 26 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V =PP1V35_GPU_S0_FB 77
=PP3V3_S5_LPCPLUS 47 =PP3V3_S3_P3V3ENETFET 74 MAKE_BASE=TRUE
=PP3V3_S5_SMC 45 46 82 =PP3V3_S3_SMBUS_SMC_2_S3 48 =PP1V5_S0_RDRVR 41
=PP3V42_G3H_BIL 64 =PP3V3_S3_SMBUS_SMC_3 48 =PP1V5_S0_AUDIO 57
=PP3V42_G3H_CHGR 65 74 =PP3V3_S3_SMS 55 =PP3V3R1V5_S0_PCH_VCCSUSHDA 20 22 24
=PP3V42_G3H_ONEWIREPROT 64 =PP3V3_S3_USB_HUB 25 =PP1V5_S0_VMON 74

78 =PP1V05_S0GPU_REG PP1V05_S0GPU 6
=PP3V42_G3H_PWRCTL 74 =PP3V3_S3_USB_RESET 25 MIN_LINE_WIDTH=0.9 MM VOLTAGE=1.05V
68 31 =PPVTT_S3_DDR_BUF PPVTTDDR_S3 6 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PP3V42_G3H_SMBUS_SMC_5 48 =PP3V3_S3_VREFMRGN 31 MIN_LINE_WIDTH=0.3 MM
C =PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
42
53
=PP3V3_S3_WLAN
=PP3V3_S3_ISNS
32
7 49 103 104
VOLTAGE=0.75V
MAKE_BASE=TRUE
=PP1V05_GPU_IFPAB_PLLVDD
=PP1V05_GPU_IFPCD_IOVDD
81
81
C
=PP1V05_GPU_IFPEF_IOVDD 81
=PPVIN_S5_SMCVREF 46 =PP3V3_S3_PCH_GPIO 18 24 68 =PPVTT_S0_DDR_LDO PP0V75_S0_DDRVTT 6
MIN_LINE_WIDTH=2 mm =PP1V05_GPU_PEX_IOVDD 77 83
=PPVBAT_G3_SYSCLK 24 =PP3V3_S3_USBMUX 25 MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V =PP1V05_GPU_PEX_PLLVDD 81 83
For PCH RTC Power =PP3V42_G3H_AUDIO 59 =PP3V3_S3_SDBUF 24 MAKE_BASE=TRUE
24 =PPVRTC_G3_OUT PPVRTC_G3H 73 =PP3V3_S0_FET PP3V3_S0 6 101 =PP0V75_S0_MEM_VTT_A 27

MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE MIN_NECK_WIDTH=0.075 mm MAKE_BASE=TRUE =PP0V75_S0_MEM_VTT_B 29
5V Rails =PPVRTC_G3_PCH 16 17 20 =PP3V3_S0_XDP 23 =PPVTT_S0_VTTCLAMP 26
67 =PP5V_S5_LDO PP5V_S5 =PP3V3_S0_ENETPHY 36

MIN_LINE_WIDTH=0.5 MM VOLTAGE=5V 84 =PPVCORE_S0_GFX_REG PPVCORE_GPU 6
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S0_AUDIO 57 62 63 72 =PP1V2_S0_REG PP1V2_S0 6 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.0V
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PP5V_S5_P1V5S3RS0FET 73 =PP3V3_S0_BKL_VDDIO 90 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V =PPVCORE_GPU 76 83
=PP5V_S5_P5VSUSFET 73 =PP3V3_S0_DPSDRVA 87 MAKE_BASE=TRUE
=PPVCORE_GPU_REG 49
=PP5V_S5_TPAD 54 =PP3V3_S0_HS_ISNS =PP1V2_S0_GMUX 89
=PP5V_S5_ISNS =PP3V3_S0_CPUTHMSNS 51
73 =PP5V_SUS_FET PP5V_SUS =PP3V3_S0_DDC_LCD 85 72 =PP1V05_SUS_LDO PP1V05_SUS

MIN_LINE_WIDTH=0.6 MM VOLTAGE=5V MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S0_ISNS 49 50 103 104 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
=PP5V_SUS_PCH 22 =PP3V3_S0_TBTPWRCTL 35 MAKE_BASE=TRUE
67 =PP5V_S3_REG PP5V_S3 6 =PP3V3_S0_DPMUX 86 =PP1V05_SUS_PCH_JTAG 23
MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE =PP3V3_S0_FAN_LT 52
=PP5V_S3_ALSCAMERA 32 =PP3V3_S0_FAN_RT 52 71 =PPCPUVCCIO_S0_REG PP1V05_S0 6

=PP5V_S3_DDRREG 68 =PP3V3_S0_FWPWRCTL 39 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PP5V_S5_DEBUG_ADC_AVDD 104 =PP3V3_S0_FWLATEVG 39 40 =PP1V05_S0_CPU_VCCIO 9 10 12 13 14 Chipset "VCore" Rails
=PP5V_S5_DEBUG_ADC_DVDD 104 =PP3V3_S0_CPU_VCCIO_SEL 12 =PPVCCIO_S0_XDP 23 70 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 6
MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE
=PP5V_S3_AUDIO =PP3V3_S0_GMUX 86 89 =PPVCCIO_S0_CPUIMVP 69 MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V
=PP5V_S3_IR 41 44 =PP3V3_S0_P3V3TBTFET 35 =PPVCCIO_S0_SMC 46 =PPVCORE_S0_CPU 12 14 49

105
=PP5V_S3_MEMRESET 26 =PP3V3_S0_GPUTHMSNS 51 =PP1V05_S0_RMC 105
=PPVCORE_S0_AXG_REG PPVCORE_S0_AXG
B =PP5V_S3_ODD
=PP5V_S3_P5VS0FET
41
73
=PP3V3_S0_LVDSDDCMUX
=PP3V3_S0_ODD
86
41
=PP1V05_S0_FWPWRCTL
=PP1V05_FW_P1V0FWFET
39
39
70 49
MAKE_BASE=TRUE
VOLTAGE=1.05V B
=PPVCORE_S0_CPU_VCCAXG 12 13 15
=PP5V_S3_USB 42 =PP3V3_S0_PCH 16 22 =PP1V05_S0_VMON 74
=PP5V_S3_SYSLED 46 =PP3V3_S0_PCH_GPIO 16 17 18 19 30 =PP1V05_S0_P1V05TBTFET 35 15 12 =PP1V5_S3_CPU_VCCDQ PP1V5_S3_CPU_VCCDQ

=PP5V_S3_P5VS0SW =PP3V3_S0_PCH_VCC3_3_CLK 22 =PP1V05_S0_PCH_VCCIO_PLLPCIE 20 MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V
=PP5V_S3_P3V3S0SW =PP3V3_S0_PCH_VCC3_3_GPIO 20 22 =PP1V05_S0_PCH_VCCADPLL 22

14 12 8 =PP1V05_S0_CPU_VCCPQE PP1V05_S0_CPU_VCCPQE
=PP5V_S3_GFXIMVP 84 =PP3V3_S0_PCH_VCC3_3_HVCMOS 20 22 =PP1V05_S0_PCH_VCCIO 20 22 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V
=PP3V3_S0_PCH_VCC3_3_PCI 20 22 =PP1V05_S0_PCH_VCCIO_PCIE 17
66 49 =PPVCCSA_S0_REG PPVCCSA_S0_REG
73 =PP5V_S0_FET PP5V_S0 6 =PP3V3_S0_PCH_VCC3_3_SATA 20 22 =PP1V05_S0_PCH_VCCIO_SATA 16 20 22 MIN_LINE_WIDTH=0.6 MM VOLTAGE=0.9V
MIN_LINE_WIDTH=0.4 MM VOLTAGE=5V MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S0_PCH_VCCADAC 22 =PP1V05_S0_PCH_VCCIO_CLK 7 20 22
103 =PP5V_S0_ISNS =PPVCCSA_S0_CPU 12 15
=PP5V_S0_BKL 90 =PP3V3_S0_PCH_VCCA_LVDS 20 =PP1V05_S0_PCH_VCCIO_USB 20 22
=PP5V_S0_CPUIMVP 69 70 =PP3V3_S0_PWRCTL 74 92 =PP1V05_S0_PCH_VCC_CORE 20 22 FireWire Rails

=PP5V_S0_CPUVCCIOS0 71 =PP3V3_S0_RSTBUF 24 =PP1V05_S0_PCH_VCCASW 20 22
39 =PPBUS_FW_FET PPVP_FW 6
=PP5V_S0_FAN_LT 52 =PP3V3_S0_SB_PM 24 92 =PP1V05_S0_PCH_VCCIO_CLK 7 20 22 MIN_LINE_WIDTH=0.4 MM VOLTAGE=12.8V
=PP5V_S0_FAN_RT 52 =PP3V3_S0_SDCARD 30 =PP1V05_S0_PCH_VCCDIFFCLK 16 20 22
=PP5V_S0_VCCSAS0 66 =PP3V3_S0_SMBUS_PCH 48 =PP1V05_S0_PCH 16 22

=PPVP_FW_PORT1 40
=PP5V_S0_VMON =PP3V3_S0_SMBUS_SMC_0_S0 =PP1V05_S0_PCH_VCCSSC =PPVP_FW_PHY_CPS_FET

74 48 20 22 40
=PP5V_S0_HDD 41 =PP3V3_S0_SMBUS_SMC_1_S0 48 =PP1V05_S0_PCH_V_PROC_IO 20 22

39 =PP3V3_FW_FET PP3V3_FW_FWPHY 6
=PP5V_S0_KBDLED 54 =PP3V3_S0_SMC 41 =PP1V05_S0_PCH_VCCIO_PLLUSB 20 MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V
=PP5V_S0_LPCPLUS 47 =PP3V3_S0_TPAD 54 =PP1V05_S0_PCH_VCC_DMI 20 22
=PP3V3_FW_FWPHY 38 39 40
=PP5V_S0_PCH 22 24 =PP3V3_S0_VMON 74 =PP1V05_S0_PCH_VCCIO_PLLFDI 20
=PP5V_S0GPU_P1V05 78 =PPSPD_S0_MEM_A 27 =PP1V05_S0_PCH_VCCDMI_FDI 20
=PP5V_S0_AUDIO_XW 8 =PPSPD_S0_MEM_B 29 39 =PP1V0_FW_FET_R PP1V0_FW_FWPHY 6

=PPPCHVCCIO_S0_REG 91 MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.0V
=PP5V_S0_RMC 105 =PP3V3_S0_HDD 41 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
3.3V Rails =PP5V_S0GPU_P1V5 78 =PP3V3_S0_P1V8GPUFET 73
=PP3V3_S4_FET PP3V3_S4 =PP3V3_S0_IMVPISNS

Backlight Rails =PP1V0_FW_FWPHY 38 39
73 6 50
A 30
32
=PP3V3_S4_SD_HPD
=PP3V3_S4_BT
=PP3V3_S4_TPAD
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE VOLTAGE=3.3V
53 54
T29 Rails
=PP3V3_S0_T29I2C
=PP3V3_S0_TBT_HPD_GPU
48 104 90 =PPBUS_SW_BKL PPBUS_SW_BKL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE
VOLTAGE=12.8V
=PP3V3_S4_SMC 46
PAGE TITLE
=PP3V3_TBT_FET PP3V3_TBT =PP3V3_ENET_FET PP3V3_ENET
73 =PP3V3_SUS_FET PP3V3_SUS
35
MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
74
VOLTAGE=3.3V
MAKE_BASE=TRUE
6
Power Aliases
=PP3V3_T29_PCH_GPIO 16 19 DRAWING NUMBER SIZE
ENET Rails
MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V
=PP3V3_ENET_PHY
=PP3V3_SUS_P1V05SUSLDO 72 =PPVDDIO_T29_CLK 24
=PPVDDIO_ENET_CLK
24 36 72
24 Apple Inc. 051-9585 D

=PP3V3_SUS_PCH_VCCSUS 20 22 =PP3V3_TBT_RTR 33 34 35 REVISION
=PP3V3_ENET_SYSCLK
=PP3V3_SUS_PCH_VCCSUS_GPIO 20 22 =PP3V3_T29_JTAG 89
72 =PP1V2_S3_ENET_PHY PP1V2_ENET
24
6
R
3.0.0
=PP3V3_SUS_PCH_GPIO 16 17 18 19 35 =PP1V05_TBT_FET PP1V05_TBT 35 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.2V NOTICE OF PROPRIETARY PROPERTY: BRANCH
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PP3V3_SUS_PCH_VCCSUS_USB 20 22 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
=PP1V2_ENET_PHY 36 PROPRIETARY PROPERTY OF APPLE INC.
=PP3V3_SUS_CNTRL 74 =PP1V05_TBT_RTR_R 104 TBT Rails THE POSESSOR AGREES TO THE FOLLOWING: PAGE
=PP3V3_SUS_SMC 46 35 8 =PP15V_TBT_REG PP15V_TBT
MIN_LINE_WIDTH=0.4 MM VOLTAGE=15V 104 34 =PP1V05_TBT_RTR PP1V05_TBT_RTR
8 OF 132
=PP3V3_SUS_ROM 56 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V SHEET
PPVIN_SW_TBTBST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
=PP3V3_SUS_PCH_VCC_SPI 20 22 =PPHV_SW_TBTAPWRSW 88
I1658
VOLTAGE=12.8V
35 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Thermal Module Holes Fan Holes USB Signals
ZT0984 T29 / GMUX JTAG Signals
NC_USB_EXTD_EHCIN USB_EXTD_EHCI_N
95 32 USB_BT_N USBHUB_DN1_N 25
18 MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH ZT0981 ZT0930 MAKE_BASE=TRUE NO_TEST=TRUE
JTAG_GMUX_TCK 89 95 32 USB_BT_P USBHUB_DN1_P 25
1 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH NC_USB_EXTD_EHCIP USB_EXTD_EHCI_P 18 MAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE
1 1 23 19
JTAG_ISP_TCK JTAG_TBT_TCK 33 95 53 USB_TPAD_N USBHUB_DN3_N 25
MAKE_BASE=TRUE NC_USB3_EXTC_RXN USB3_EXTC_RX_N 18 MAKE_BASE=TRUE
ZT0987 MAKE_BASE=TRUE NO_TEST=TRUE
USB_TPAD_P USBHUB_DN3_P
95 53 25
STDOFF-4.5OD.98H-1.1-3.48-TH ZT0985 ZT0988 89 19 JTAG_ISP_TDI JTAG_TBT_TDI 19 33 NC_USB3_EXTC_RXP USB3_EXTC_RX_P 18 MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
1 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH 95 44 USB_IR_N USBHUB_DN2_N 25
NC_USB3_EXTC_TXN USB3_EXTC_TX_N 18 MAKE_BASE=TRUE
1 1 89 19 JTAG_ISP_TDO JTAG_TBT_TDO 33 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE 95 44 USB_IR_P USBHUB_DN2_P 25
ZT0980 NC_USB3_EXTC_TXP USB3_EXTC_TX_P 18 MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH ZT0986 ZT0989 33 TBT_LSOE<3> T29_LSEO_LSOE3 TBT_LSEO<3> 33 95 USB_SMC_N USBHUB_DN4_N 25
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
1 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH Unused PEG signals
33 TBT_LSOE<2> T29_LSEO_LSOE2 TBT_LSEO<2> 33 95 USB_SMC_P USBHUB_DN4_P 25
NC_PEG_D2RP<15..12> =PEG_D2R_P<15..12>
D
1 1 MAKE_BASE=TRUE 9 MAKE_BASE=TRUE
D Frame Holes ZT0991

GMUX ALIASES
NO_TEST=TRUE MAKE_BASE=TRUE
NC_PEG_D2RN<15..12>
MAKE_BASE=TRUE
NO_TEST=TRUE
=PEG_D2R_N<15..12> 9 NC_ADC_CH6
MAKE_BASE=TRUE
ADC_CH6 104
ZT0915 NO_TEST=TRUE NO_TEST=TRUE
3R2P5 STDOFF-4.5OD.98H-1.1-3.48-TH 89 GMUX_INT DPMUX_UC_IRQ 19 NC_PEG_R2D_CP<15..12> =PEG_R2D_C_P<15..12> 9 NC_ADC_CH7 ADC_CH7 104

MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
1 GND_BATT_CHGND 1
92 PM_ALL_GPU_PGOOD ALL_EG_PGOOD 89 NC_PEG_R2D_CN<15..12> =PEG_R2D_C_N<15..12> 9
MAKE_BASE=TRUE MAKE_BASE=TRUE TP_LVDS_IG_B_CLKP LVDS_IG_B_CLK_P
ZT0940 NO_TEST=TRUE 6
MAKE_BASE=TRUE
17
3R2P5 T29 Signals Through PEG

GND_CHASSIS_LVDS TP_LVDS_MUX_SEL_EG LVDS_MUX_SEL_EG 89
1 MAKE_BASE=TRUE NO_TEST=TRUE 6 TP_LVDS_IG_B_CLKN LVDS_IG_B_CLK_N 17
MAKE_BASE=TRUE
ZT0950 89 EG_RESET_L GPU_RESET_L 75 82 96 33 PCIE_TBT_D2R_P<3..0> =PEG_D2R_P<11..8> 9
TH 6 TP_LVDS_IG_BKL_PWM LVDS_IG_BKL_PWM 17
1 GND_CHASSIS_FAN Left Speaker Holes 17 LVDS_IG_BKL_ON IG_BKLT_EN 89 96 33 PCIE_TBT_D2R_N<3..0> =PEG_D2R_N<11..8> 9 MAKE_BASE=TRUE
SL-3.1X2.7-6CIR-NSP LVDS_IG_PANEL_PWR IG_LCD_PWR_EN PCIE_TBT_R2D_C_P<3..0> =PEG_R2D_C_P<11..8> NC_GPU_XTALOUT GPU_XTALOUT
17 89 96 33 9
ZT0960 ZT0934 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
3R2P5 STDOFF-4.0OD3.0H-TH 104 85 6 PPVOUT_S0_LCDBKLT PPVOUT_SW_LCDBKLT 90 96 33 PCIE_TBT_R2D_C_N<3..0> =PEG_R2D_C_N<11..8> 9 NC_LVDS_IG_A_DATAP<3> LVDS_IG_A_DATA_P<3> 17 95

MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
1 GND_CHASSIS_SATA 1
NC_LVDS_IG_A_DATAN<3> LVDS_IG_A_DATA_N<3> 17 95
GPU signals MAKE_BASE=TRUE
ZT0990 NO_TEST=TRUE
3R2P5 GND_CHASSIS_BATTCONN
ZT0935 PEX_CLKREQ_L EG_CLKREQ_IN_L 82 89
PEG_D2R_P<7..0> =PEG_D2R_P<7..0>
MAKE_BASE=TRUE 93 75 9
1 STDOFF-4.0OD3.0H-TH MAKE_BASE=TRUE NO_TEST=TRUE NC_LVDS_IG_B_DATAP<3> LVDS_IG_B_DATA_P<3> 17
16 PEG_CLKREQ_L EG_CLKREQ_OUT_L 89 MAKE_BASE=TRUE NO_TEST=TRUE
1 MAKE_BASE=TRUE 93 75 PEG_D2R_N<7..0> =PEG_D2R_N<7..0> 9
MAKE_BASE=TRUE NO_TEST=TRUE NC_LVDS_IG_B_DATAN<3> LVDS_IG_B_DATA_N<3> 17
PM_ENET_EN =P1V2ENET_EN MAKE_BASE=TRUE NO_TEST=TRUE
Tall EMI pogo pins MAKE_BASE=TRUE 93 75 PEG_R2D_C_P<7..0> =PEG_R2D_C_P<7..0> 9
NOSTUFF MAKE_BASE=TRUE NO_TEST=TRUE
SH0930 SH0934 Unused eDP signals 93 75 PEG_R2D_C_N<7..0> =PEG_R2D_C_N<7..0> 9

NOSTUFF MAKE_BASE=TRUE NO_TEST=TRUE
POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 93 9 DP_INT_IG_ML_P<3..0> NC_DP_INT_IG_MLP<3..0>
SM SH0932 SM
Unused T29 Ports
POGO-2.0OD-3.5H-K86-K87 93 9 DP_INT_IG_ML_N<3..0> NC_DP_INT_IG_MLN<3..0>
1
SM
1 MAKE_BASE=TRUE NO_TEST=TRUE 98 33 TBT_D2R_P<3..2> NC_T29_D2RP<3..2>
93 9 DP_INT_IG_AUX_P NC_DP_INT_IG_AUXP NC_USB_EXTCN USB_EXTC_N 18 95
1 MAKE_BASE=TRUE NO_TEST=TRUE 98 33 TBT_D2R_N<3..2> NC_T29_D2RN<3..2> MAKE_BASE=TRUE NO_TEST=TRUE
SH0931 SH0935 NOSTUFF MAKE_BASE=TRUE NO_TEST=TRUE
93 9 DP_INT_IG_AUX_N NC_DP_INT_IG_AUXN NC_USB_EXTCP USB_EXTC_P 18 95
POGO-2.0OD-3.5H-K86-K87 POGO-2.0OD-3.5H-K86-K87 MAKE_BASE=TRUE 98 33 TBT_R2D_C_P<3..2> NC_T29_R2D_CP<3..2> MAKE_BASE=TRUE
C
NO_TEST=TRUE NO_TEST=TRUE
C NOSTUFF SM
1
SH0933 NOSTUFF
POGO-2.0OD-3.5H-K86-K87 1
SM
9 DP_INT_IG_HPD NC_DP_INT_IG_HPD
MAKE_BASE=TRUE NO_TEST=TRUE 98 33 TBT_R2D_C_N<3..2>
MAKE_BASE=TRUE
NC_T29_R2D_CN<3..2>
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE NC_USB3_EXTD_RXN USB3_EXTD_RX_N 18

SM MAKE_BASE=TRUE NO_TEST=TRUE
1 CPU signals NC_USB3_EXTD_RXP USB3_EXTD_RX_P 18
FW_PLUG_DET_L FW_PME_L
SH0902 MAKE_BASE=TRUE
19 39 MAKE_BASE=TRUE NO_TEST=TRUE
POGO-2.0OD-3.5H-K86-K87 NC_USB3_EXTD_TXN USB3_EXTD_TX_N 18
SH0900 Keyboard / IPD Conn Protect 26 MEMVTT_EN =DDRVTT_EN 26 68 MAKE_BASE=TRUE NO_TEST=TRUE
SM
39 FW643_WAKE_L =FW_PME_L 38 39 MAKE_BASE=TRUE
1
POGO-2.0OD-3.5H-K86-K87 ZT0952 MAKE_BASE=TRUE NC_USB3_EXTD_TXP USB3_EXTD_TX_P 18
SM 4.0OD1.85H-M1.6X0.35
TP_SMC_EXCARD_PWR_EN SMC_EXCARD_PWR_EN
1 1 MAKE_BASE=TRUE TALL POGO PINS for BT NF
SH0903
POGO-2.0OD-3.5H-K86-K87 16 PCIE_EXCARD_D2R_N TRUE NC_PCIE_EXCARD_D2RN
SM SH0916 ZT0953 PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2RP
DP_EG_AUXCH_N DP_EG_AUX_CH_N 81 86 100
SH0939
16 TRUE MAKE_BASE=TRUE
POGO-2.0OD-3.5H-K86-K87 4.0OD1.85H-M1.6X0.35 POGO-2.0OD-3.5H-K86-K87
1 16 PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
TRUE NC_PCIE_EXCARD_R2D_CN DP_EG_AUXCH_P DP_EG_AUX_CH_P 81 86 100
SH0941
SM SM
1
PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_CP
MAKE_BASE=TRUE POGO-2.0OD-3.5H-K86-K87
16 TRUE
1 1 SM
MAKE_BASE=TRUE
NC_DPB_EG_AUX_CHN DPB_EG_AUX_CH_N
SH0904 MAKE_BASE=TRUE NO_TEST=TRUE 1
POGO-2.0OD-3.5H-K86-K87 NC_DPB_EG_AUX_CHP DPB_EG_AUX_CH_P
SH0937 NOSTUFF SH0940
SM
R0921 96 16 PCIE_CLK100M_EXCARD_N TRUE NC_PCIE_CLK100M_EXCARDN MAKE_BASE=TRUE NO_TEST=TRUE
POGO-2.0OD-3.5H-K86-K87 MAKE_BASE=TRUE POGO-2.0OD-3.5H-K86-K87 SH0942
1 51 NC_DPB_EG_DDC_CLK DPB_EG_DDC_CLK
SM
8 T29_A_BIAS_R 1 2 TBT_A_BIAS0P 87 96 16 PCIE_CLK100M_EXCARD_P TRUE NC_PCIE_CLK100M_EXCARDP MAKE_BASE=TRUE NO_TEST=TRUE
SM
POGO-2.0OD-3.5H-K86-K87
MAKE_BASE=TRUE
1 5% NC_DPB_EG_DDC_DATA DPB_EG_DDC_DATA 1 SM
SH0936 NOSTUFF 1/20W

MF
1
C0901 MAKE_BASE=TRUE NO_TEST=TRUE
1
POGO-2.0OD-3.5H-K86-K87 201 0.01UF NC_DPB_EG_MLN<3..0> DPB_EG_ML_N<3..0>
10%
SM SH0938 NOSTUFF 2
10V
TP_PEG_B_CLKRQ_L_GPIO56 TRUE
MAKE_BASE=TRUE
NC_PEG_B_CLKRQ_L_GPIO56 MAKE_BASE=TRUE NO_TEST=TRUE
X5R NC_DPB_EG_MLP<3..0> DPB_EG_ML_P<3..0>
1
POGO-2.0OD-3.5H-K86-K87 201 TP_PCIECLKRQ4_L_GPIO26 NC_PCIECLKRQ4_L_GPIO26
TRUE MAKE_BASE=TRUE NO_TEST=TRUE
SM
MAKE_BASE=TRUE
1
TP_ISSP_SCLK_P1_1 ISSP_SCLK_P1_1 R0926 R0927
R0922 53
MAKE_BASE=TRUE
6
51 51
51 8 T29_A_BIAS_R 1 2 TBT_A_BIAS1P 88 8 T29_A_BIAS_R 1 2 TBT_A_BIAS1N 88
8 T29_A_BIAS_R 1 2 TBT_A_BIAS0N 87 53 TP_ISSP_SDATA_P1_0 ISSP_SDATA_P1_0 6
5% 5%
Short (IO Row) EMI pogo pins SH0911 MAKE_BASE=TRUE
1
C0906 1
C0907
B B
5% 1/20W 1/20W
1.4DIA-SHORT-SILVER-K99 1/20W
MF
1
C0902 TP_GMUX_PT20A
MF
201 0.01UF
MF
201 0.01UF
SH0910 SM 201 0.01UF 89
10%
10V
10%
10V
1.4DIA-SHORT-SILVER-K99 10%
10V 89 TP_GMUX_PT20B 2 X5R 2 X5R
1 2
SM X5R TP_GMUX_PT32A 201 201
201 89
1 89 TP_GMUX_PT32B
SH0913 PLACE_NEAR=C9361.1:2 mm
1.4DIA-SHORT-SILVER-K99 =PP1V05_S0M_PCH_VCC_LAN R9363

SH0912 SM 51
1.4DIA-SHORT-SILVER-K99 R0923 2 1 87 DP_A_BIAS2
1 51 16 TP_PCH_CLKOUT_DPN TRUE NC_PCH_CLKOUT_DPN
SM
8 T29_A_BIAS_R 1 2 TBT_A_BIAS2P 87 MAKE_BASE=TRUE 5%
DP_A_BIAS 1/20W
1 5% MAKE_BASE=TRUE MF
SH0917 1/20W
MF
1
C0903 16 TP_PCH_CLKOUT_DPP TRUE NC_PCH_CLKOUT_DPP
87 =DP_A_BIAS R9362 201
MAKE_BASE=TRUE
1.4DIA-SHORT-SILVER-K99 201 0.01UF 51
SH0901 SM
10%
10V
2 1 87 DP_A_BIAS0
2 X5R PLACE_NEAR=C9361.1:2 mm
1.4DIA-SHORT-SILVER-K99 16 TP_PCH_GPIO64_CLKOUTFLEX0 TRUE NC_PCH_GPIO64_CLKOUTFLEX0 5%
SM
1 201
TP_PCH_GPIO65_CLKOUTFLEX1
MAKE_BASE=TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
1/20W
MF
1
C0908
16 TRUE
MAKE_BASE=TRUE 201 0.01UF
1 16 TP_PCH_GPIO66_CLKOUTFLEX2 TRUE NC_PCH_GPIO66_CLKOUTFLEX2
NC_DP_IG_MLP<3..0> TP_DP_IG_B_MLP<3..0>
1
C0905 10%
10V
MAKE_BASE=TRUE 17
0.01UF 2 X5R
TP_PCH_GPIO67_CLKOUTFLEX3 NC_PCH_GPIO67_CLKOUTFLEX3
SH0918 16 TRUE MAKE_BASE=TRUE NO_TEST=TRUE 10% 201
1.4DIA-SHORT-SILVER-K99 R0924 MAKE_BASE=TRUE
NC_DP_IG_MLN<3..0> TP_DP_IG_B_MLN<3..0> 17 2
10V
X5R
SM
51 MAKE_BASE=TRUE NO_TEST=TRUE 201
8 T29_A_BIAS_R 1 2 TBT_A_BIAS2N 87
95 86 DP_IG_AUX_CH_P DPA_IG_AUX_CH_P 17
SH0914 1 5% NC_FSB_CLK133M_PCHP FSB_CLK133M_PCH_P 90 89 LCD_BKLT_EN MAKE_BASE=TRUE
1/20W 1
C0904 MAKE_BASE=TRUE NO_TEST=TRUE
DP_IG_AUX_CH_N DPA_IG_AUX_CH_N GND
1.4DIA-SHORT-SILVER-K99 MF
0.01UF 95 86 17
SM
201
10%
NC_FSB_CLK133M_PCHN FSB_CLK133M_PCH_N MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm
10V MAKE_BASE=TRUE NO_TEST=TRUE MIN_NECK_WIDTH=0.095 mm
1
1 GND_CHASSIS_AUDIO_JACK 62
2 X5R R0901 86 DP_IG_DDC_CLK DPA_IG_DDC_CLK 17
VOLTAGE=0V
201 NC_LT_GAIN_TP LT_GAIN_TP 4.7K MAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE 5%
1/16W 86 DP_IG_DDC_DATA DPA_IG_DDC_DATA 17
10 DPLL_REF_CLK_P NC_RT_GAIN_TP RT_GAIN_TP MF-LF MAKE_BASE=TRUE
93 DPLL_REF_CLKP
MAKE_BASE=TRUE =PP1V05_S0_CPU_VCCPQE 14
7
MAKE_BASE=TRUE
NC_SW_GAIN_TP
NO_TEST=TRUE
SW_GAIN_TP
2
402
86 DP_IG_HPD
MAKE_BASE=TRUE
DPA_IG_HPD 17 Digital Ground
12 MAKE_BASE=TRUE NO_TEST=TRUE
A R9490
51
1
R0941
1K
1
R0940 XW0901
SYNC_MASTER=K18_MLB SYNC_DATE=04/27/2010 A
T29_A_BIAS 1 2 T29_A_BIAS_R 8 5% 1K SM
PAGE TITLE
MAKE_BASE=TRUE
1
C9490
5%
1/20W
VOLTAGE=3.3V 1/16W
MF-LF
402
5%
1/16W
MF-LF
7 =PP5V_S0_AUDIO_XW 1 2 PP5V_S0_AUDIO
MAKE_BASE=TRUE NC_DPB_IG_AUX_CHP DPB_IG_AUX_CH_P 17
Signal Aliases
MF 2
0.1UF 402 MAKE_BASE=TRUE TRUE DRAWING NUMBER SIZE
=TBT_A_BIAS 201 2
=PP5V_S0_AUDIO
87
2
10%
6.3V
PLACE_NEAR=C9490.1:2 mm
10 DPLL_REF_CLK_N DPLL_REF_CLKN 93 XW0902

57
NC_DPB_IG_AUX_CHN
MAKE_BASE=TRUE TRUE
DPB_IG_AUX_CH_N 17
X5R
201 MAKE_BASE=TRUE SM REVISION
Unused eDP CLK
TBTBST:N
1 2 PP5V_S0_AUDIO_AMP_L
MIN_LINE_WIDTH=0.50MM
61 NC_DPB_IG_DDC_CLK
MAKE_BASE=TRUE TRUE
DPB_IG_DDC_CLK 17
R
3.0.0
NC_DPB_IG_DDC_DATA DPB_IG_DDC_DATA
R0950 XW0903
VOLTAGE=5V
MAKE_BASE=TRUE TRUE
17
0 SM PROPRIETARY PROPERTY OF APPLE INC.
35 7 =PPVIN_SW_TBTBST 1 2 =PP15V_TBT_REG 7 35 NC_DPB_IG_HPD DPB_IG_HPD 17 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1 2 PP5V_S0_AUDIO_AMP_R
5%
1/8W
61 MAKE_BASE=TRUE TRUE I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
9 OF 132
MF-LF VOLTAGE=5V SHEET
805 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V05_S0_CPU_VCCIO 7 9 10 12 13 14
1
R1010
U1000 24.9
1%
IVY-BRIDGE 1/16W
MF-LF
BGA
OMIT_TABLE 2
402
93 17 6 DMI_S2N_N<0> N10 DMI_RX0* (1 OF 11) PEG_ICOMPI G2 93 CPU_PEG_COMP

IN
93 17 6 DMI_S2N_N<1> R10 DMI_RX1* PEG_ICOMPO H1
IN
93 17 DMI_S2N_N<2> R8 DMI_RX2* PEG_RCOMPO F3
IN
93 17 6 DMI_S2N_N<3> U10 DMI_RX3*
93 23 9 CPU_CFG<0> B57 (IPU) U1000 BB57
NC
IN
F23
93 23 9 CPU_CFG<1> D57 (IPU) IVY-BRIDGE BB43
NC
PEG_RX0* =PEG_D2R_N<0>
IN 8
B55 BGA BB25
CPU_CFG<2>
93 17 6 IN DMI_S2N_P<0> N8 DMI_RX0 PEG_RX1* H23 =PEG_D2R_N<1>
IN 8
93 23 9 (IPU) OMIT_TABLE
NC
CPU_CFG<3> A54 (5 OF 11) BB17
T9 DMI_RX1 PEG_RX2* H21
93 23 9 (IPU)
RESERVED NC
D
93 17 6 DMI_S2N_P<1> =PEG_D2R_N<2> 8
IN IN A58 BB15
D
CPU_CFG<4>
93 17 IN DMI_S2N_P<2> R6 DMI_RX2 PEG_RX3* H19 =PEG_D2R_N<3> IN 8
93 23 9 (IPU)
NC
CPU_CFG<5> D55 BB13
93 17 6 IN DMI_S2N_P<3> U8 DMI_RX3 PEG_RX4* J20 =PEG_D2R_N<4>
IN 8
93 23 9 (IPU)
NC
CPU_CFG<6> C56 BA48
PEG_RX5* G18 =PEG_D2R_N<5>
93 23 9 (IPU)
NC
DMI
IN 8
CPU_CFG<7> E54 BA16
93 17 OUT DMI_N2S_N<0> N4 DMI_TX0* PEG_RX6* K17 =PEG_D2R_N<6> IN 8
93 23 9 (IPU)
NC
CPU_CFG<8> J54 AY45
93 17 6 OUT DMI_N2S_N<1> R4 DMI_TX1* PEG_RX7* F15 =PEG_D2R_N<7>
IN 8
93 23 (IPU)
NC
CPU_CFG<9> G56 AY41
93 17 6 OUT DMI_N2S_N<2> P1 DMI_TX2* PEG_RX8* H15 =PEG_D2R_N<8>
IN 8
93 23 (IPU)
CFG NC
CPU_CFG<10> F55 AY17
93 17 6 OUT DMI_N2S_N<3> U6 DMI_TX3* PEG_RX9* H13 =PEG_D2R_N<9>
IN 8
93 23 (IPU)
NC
CPU_CFG<11> K55 AY15
PEG_RX10* H11 =PEG_D2R_N<10> IN 8
93 23 (IPU)
NC
CPU_CFG<12> F57 AY13
93 17 OUT DMI_N2S_P<0> N2 DMI_TX0 PEG_RX11* J12 =PEG_D2R_N<11>
IN 8
93 23 (IPU)
NC
CPU_CFG<13> E58 AW50
93 17 6 OUT DMI_N2S_P<1> R2 DMI_TX1 PEG_RX12* E8 =PEG_D2R_N<12>
IN 8
93 23 (IPU)
NC
CPU_CFG<14> H57 AW46
93 17 6 OUT DMI_N2S_P<2> P3 DMI_TX2 PEG_RX13* G10 =PEG_D2R_N<13> IN 8
93 23 (IPU)
NC
CPU_CFG<15> H55 AW42
93 17 6 OUT DMI_N2S_P<3> T5 DMI_TX3 PEG_RX14* J8 =PEG_D2R_N<14> IN 8
93 23 (IPU)
NC
CPU_CFG<16> D53 AW14
PEG_RX15* F7 =PEG_D2R_N<15> 8
93 23 9 (IPU)
NC
IN CPU_CFG<17> K57 AJ10
93 17 OUT FDI_DATA_N<0> V7 FDI0_TX0*
93 23 (IPU)
NC
AJ6
93 17 6 OUT FDI_DATA_N<1> W8 FDI0_TX1* PEG_RX0 G22 =PEG_D2R_P<0> IN 8
NC
G64 AH5
93 17 FDI_DATA_N<2> AA8 FDI0_TX2* PEG_RX1 K23 =PEG_D2R_P<1> 8
NC NC
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

OUT IN BJ42 AD5
93 17 OUT FDI_DATA_N<3> AC10 FDI0_TX3* PEG_RX2 K21 =PEG_D2R_P<2>
IN 8
NC NC
BJ34 AC6
PEG_RX3 F19 =PEG_D2R_P<3>
IN 8
NC NC
BJ22 AC4
93 17 6 OUT FDI_DATA_N<4> U4 FDI1_TX0* PEG_RX4 K19 =PEG_D2R_P<4> IN 8
NC NC
BH43 AA4
93 17 6 OUT FDI_DATA_N<5> W2 FDI1_TX1* PEG_RX5 H17 =PEG_D2R_P<5>
IN 8
NC NC
BH35 P7
93 17 6 FDI_DATA_N<6> V1 FDI1_TX2* PEG_RX6 K15 =PEG_D2R_P<6> 8
NC RSVD NC
OUT IN BH25 N6
93 17 6 OUT FDI_DATA_N<7> Y5 FDI1_TX3* PEG_RX7 G14 =PEG_D2R_P<7> IN 8
NC NC
PCI EXPRESS BASED INTERFACE SIGNALS

BH23 M9
PEG_RX8 J16 =PEG_D2R_P<8>
IN 8
NC NC
BH21 M5
93 17 FDI_DATA_P<0> W6 FDI0_TX0 PEG_RX9 K13 =PEG_D2R_P<9> 8 NOTE: NC NC
OUT IN BH19 L10
93 17 6 OUT FDI_DATA_P<1> W10 FDI0_TX1 PEG_RX10 F11 =PEG_D2R_P<10>
IN 8 Intel is investigating processor driven VREF_DQ generation.
NC NC
BG62 L6
93 17 OUT FDI_DATA_P<2> Y9 FDI0_TX2 PEG_RX11 K11 =PEG_D2R_P<11> IN 8
This connection is to support the same.
NC NC
BG34 L4
NC NC
C 93 17 OUT FDI_DATA_P<3> AA10 FDI0_TX3 PEG_RX12
PEG_RX13
F9
H9
=PEG_D2R_P<12>
=PEG_D2R_P<13>
IN
IN
8
8
NC
BG26
BG22
L2
K49
NC C
93 17 6 OUT FDI_DATA_P<4> U2 FDI1_TX0 PEG_RX14 H7 =PEG_D2R_P<14>
IN 8
NC NC
PPCPU_MEM_VREFDQ_B BG4 K47
93 17 6 OUT FDI_DATA_P<5> W4 FDI1_TX1 PEG_RX15 G6 =PEG_D2R_P<15>
IN 8
93 31 (DDR_VREF1) (THERMDA)
NC
MIN_LINE_WIDTH=0.3 mm BF63 K9
93 17 6 OUT FDI_DATA_P<6> V3 FDI1_TX2 NC NC
MIN_NECK_WIDTH=0.2 mm BF43 K7
93 17 6 FDI_DATA_P<7> AA6 FDI1_TX3 PEG_TX0* A22 =PEG_R2D_C_N<0> 8
NC NC
OUT OUT BF41 K5
B23
VOLTAGE=0.75V NC RSVD NC
PEG_TX1* =PEG_R2D_C_N<1> OUT 8
BF35 J50
93 17 6 IN FDI_FSYNC<0> AC8 FDI0_FSYNC PEG_TX2* C18 =PEG_R2D_C_N<2>
OUT 8
NC NC
BF25 J4
93 17 6 IN FDI_FSYNC<1> AA2 FDI1_FSYNC PEG_TX3* D21 =PEG_R2D_C_N<3>
OUT 8
NC NC
BF23 J2
PEG_TX4* B19 =PEG_R2D_C_N<4>
OUT 8
NC NC
BF21 H49
93 17 6 IN FDI_INT AD9 FDI_INT PEG_TX5* E20 =PEG_R2D_C_N<5>
OUT 8
NC NC
BF19 H47
PEG_TX6* A14 =PEG_R2D_C_N<6> 8
NC (THERMDC)
NC
OUT PPCPU_MEM_VREFDQ_A BF3 H5
93 17 6 IN FDI_LSYNC<1> AB3 FDI1_LSYNC PEG_TX7* D17 =PEG_R2D_C_N<7>
OUT 8
93 31 (DDR_VREF0)
NC
MIN_LINE_WIDTH=0.3 mm BE32 G52
93 17 6 IN FDI_LSYNC<0> AB7 FDI0_LSYNC PEG_TX8* B15 =PEG_R2D_C_N<8> OUT 8
NC NC
MIN_NECK_WIDTH=0.2 mm BE16 G48
PEG_TX9* E16 =PEG_R2D_C_N<9>
OUT 8
NC NC
VOLTAGE=0.75V BE6 G4
93 8 OUT DP_INT_IG_ML_N<0> AG2 EDP_TX0* PEG_TX10* D13 =PEG_R2D_C_N<10>
OUT 8
NC NC
BD33 F5
93 8 OUT DP_INT_IG_ML_N<1> AF1 EDP_TX1* PEG_TX11* A10 =PEG_R2D_C_N<11>
OUT 8
NC NC
BD29 D49
93 8 OUT DP_INT_IG_ML_N<2> AE6 EDP_TX2* PEG_TX12* B11 =PEG_R2D_C_N<12>
OUT 8
NC NC
BD19 D25
93 8 OUT DP_INT_IG_ML_N<3> AG6 EDP_TX3* PEG_TX13* D9 =PEG_R2D_C_N<13>
OUT 8
NC NC
BD15 D3
NC NC
EMBEDDED DISPLAY PORT
PEG_TX14* B7 =PEG_R2D_C_N<14> 8
OUT BD13 C52
93 8 OUT DP_INT_IG_ML_P<0> AG4 EDP_TX0 PEG_TX15* E12 =PEG_R2D_C_N<15> OUT 8
NC NC
14 13 12 10 9 7 =PP1V05_S0_CPU_VCCIO BC42 C24
93 8 OUT DP_INT_IG_ML_P<1> AF3 EDP_TX1 NC NC
BC30 C4
93 8 OUT DP_INT_IG_ML_P<2> AF7 EDP_TX2 PEG_TX0 C22 =PEG_R2D_C_P<0>
OUT 8
NC NC
BC14 B53
1 DP_INT_IG_ML_P<3> AG8 EDP_TX3 PEG_TX1 D23 =PEG_R2D_C_P<1> NC NC
R1030 93 8 OUT OUT 8
B25
OMIT_TABLE 24.9 PEG_TX2 A18 =PEG_R2D_C_P<2>
OUT 8
NC
1 1%
R1031 AE4 B21
1/16W 93 8 BI DP_INT_IG_AUX_P EDP_AUX PEG_TX3 =PEG_R2D_C_P<3>
OUT 8
1K MF-LF
AE2 EDP_AUX* PEG_TX4 D19
B
DP_INT_IG_AUX_N =PEG_R2D_C_P<4>
B
5% 402 93 8 BI OUT 8
2
1/16W
PEG_TX5 F21 =PEG_R2D_C_P<5> 8
MF-LF PLACE_NEAR=U1000.AB1:12.7mm OUT
402
2 93 CPU_EDP_COMP AB1 EDP_ICOMPO PEG_TX6 C14 =PEG_R2D_C_P<6> 8
OUT
AC2 EDP_COMPIO PEG_TX7 B17 =PEG_R2D_C_P<7> 8
OUT
PEG_TX8 D15 =PEG_R2D_C_P<8> 8
OUT
DP_INT_IG_HPD_L AE8 EDP_HPD* PEG_TX9 F17 =PEG_R2D_C_P<9> 8
OUT
PEG_TX10 B13 =PEG_R2D_C_P<10> 8
OUT
PEG_TX11 C10 =PEG_R2D_C_P<11> 8
OUT
D PEG_TX12 D11 =PEG_R2D_C_P<12> 8
3 OUT
PEG_TX13 B9 =PEG_R2D_C_P<13>
Q1031 OUT 8
DP_INT_IG_HPD 1 PEG_TX14 D7 =PEG_R2D_C_P<14>

8 IN 2N7002TXG OUT 8
G SOT-523-3
EDP:YES PEG_TX15 F13 =PEG_R2D_C_P<15> 8
S 2 OUT
93 23 9 CPU_CFG<7>
93 23 9 CPU_CFG<6> 93 23 9 CPU_CFG<16> PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
93 23 9 CPU_CFG<5> 93 23 9 CPU_CFG<3>
116S0066 1 RES,MTL FILM,1/16W,1K,0402,SMD,LF R1031 EDP:YES
93 23 9 CPU_CFG<4> 93 23 9 CPU_CFG<1>
93 23 9 CPU_CFG<2> 93 23 9 CPU_CFG<0> 116S0090 1 RES,MTL FILM,1/16W,10K,0402,SMD,LF R1031 EDP:NO

EDP:YES
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 1 1 1 1 1 1 1 1
R1042 R1044 R1045 R1046 R1047 R1040 R1041 R1043 R1049
1K 1K 1K 1K 1K 1K 1K 1K 1K
5% 5% 5% 5% 5% 5% 5% 5% 5%
A 1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
A
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
CPU_CFG<4> should be pulled down to enable EDP These can be Placed close to J2500 and Only for debug access DRAWING NUMBER SIZE

REVISION
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
R
3.0.0
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED PROPRIETARY PROPERTY OF APPLE INC.
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
10 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
14 13 12 10 9 7 =PP1V05_S0_CPU_VCCIO
14 13 12 10 9 7 =PP1V05_S0_CPU_VCCIO
NOSTUFF NOSTUFF NOSTUFF

1 1 1
R1100 R1104 R1102
1 1K 51 1K
R1101 5% 5% 5% U1000
68 1/20W 1/16W 1/20W
5% MF MF-LF MF IVY-BRIDGE
1/16W 201 402 201
2 2 2 BGA
OMIT_TABLEDPLL_REF_CLK AJ4 DPLL_REF_CLK_P 8
MF-LF
IN
2
402
B59 PROC_DETECT* (2 OF 11) DPLL_REF_CLK* AJ2 DPLL_REF_CLK_N
NC IN 8
93 19 CPU_PROC_SEL_L AH9 PROC_SELECT* BCLK_ITP K63 ITPCPU_CLK100M_P 16 93

OUT IN
CLOCKS
BCLK_ITP* K65 ITPCPU_CLK100M_N
R1103 16 93
C
IN
C 93 69 46 45 BI CPU_PROCHOT_L 2
56
1
93 45 OUT CPU_CATERR_L H53 CATERR*
BCLK D5 DMI_CLK100M_CPU_P 16 93
5%
IN
1/16W CPU_PECI F53 PECI BCLK* C6 DMI_CLK100M_CPU_N
THERMAL
93 46 19 BI IN 16 93
MF-LF
14 13 12 10 9 7 =PP1V05_S0_CPU_VCCIO 402
CPU_PROCHOT_R_L H51 PROCHOT* (IPU) PRDY* J62 XDP_CPU_PRDY_L 23 93

1 OUT
R1126 (IPU) PREQ* H65 XDP_CPU_PREQ_L 23 93
IN
75
1% 93 46 19 PM_THRMTRIP_L F51 THERMTRIP*
OUT
1/16W
MF-LF (IPD) TCK J58 XDP_CPU_TCK 23 93
IN
402
2 R1125 (IPU) TMS H59 XDP_CPU_TMS
IN 23 93
43.2
PWR MGMT
K51 H63
JTAG & BPM

24 23 IN CPU_RESET_L 2 1 PLT_RESET_LS1V1_L RESET* (IPU) TRST* XDP_CPU_TRST_L
IN 23 93
1%
1/16W
MF-LF 93 17 PM_SYNC K53 PM_SYNC (IPU) TDI K61 XDP_CPU_TDI 23 93
402
IN IN
TDO K59 XDP_CPU_TDO 23 93
OUT
93 23 19 CPU_PWRGD C60 UNCOREPWRGOOD
IN
DBR* H61 XDP_DBRESET_L 23 24 93
OUT
PM_MEM_PWRGD_R AY25 SM_DRAMPWROK
(IPU) BPM0* C62 XDP_BPM_L<0> 23 93
BI
26 =MEM_RESET_L BE24 SM_DRAMRST* (IPU) BPM1* D61 XDP_BPM_L<1> 23 93
DDR3 MISC
OUT BI
(IPU) BPM2* E62 XDP_BPM_L<2> 23 93
26 15 13 10 7 =PP1V5_S3_CPU_VCCDDR BI
PLACE_NEAR=R1121.2:1mm CPU_DDR_VREF BJ44 SM_VREF (IPU) BPM3* F63 XDP_BPM_L<3> 23 93
BI
BPM4* D59 XDP_BPM_L<4>
R1120 1
(IPU) BI 23 93
93 CPU_SM_RCOMP<0> BJ46 SM_RCOMP0 (IPU) BPM5* F61 XDP_BPM_L<5> 23 93

200 BI
1% BG46 F59
1/16W
93 CPU_SM_RCOMP<1> SM_RCOMP1 (IPU) BPM6* XDP_BPM_L<6>
BI 23 93
MF-LF BF45 G60
402 R1121 93 CPU_SM_RCOMP<2> SM_RCOMP2 (IPU) BPM7* XDP_BPM_L<7> BI 23 93
2
130
93 26 17 PM_MEM_PWRGD 2 1
IN
1 1 1
B B
1%
R1120 and R1121 are Intel recommended values 1/16W R1112 R1113 R1114
MF-LF 140 25.5 200 1
402 R1111
1% 1% 1% PLACE_NEAR=U1000.BF45:12.7mm
PLACE_NEAR=U1000.AY25:51.562mm 1/16W 1/16W 1/16W 10K
MF-LF MF-LF MF-LF 5% PLACE_NEAR=U1800.AY11:157mm
402 402 402 1/16W
2 2 2
MF-LF
402
26 15 13 10 7 =PP1V5_S3_CPU_VCCDDR 2
1 PLACE_NEAR=U1000.BG46:12.7mm
R1130
1K PLACE_NEAR=U1000.BJ46:12.7mm
PLACE_NEAR=U1000.BJ44:2.54mm 5%
1/16W
MF-LF
402
2
1
R1131 1
C1130
PLACE_NEAR=U1000.BJ44:2.54mm 1K
5%
0.1UF
10%
1/16W
16V
MF-LF 2 X5R
402
2 402
PLACE_NEAR=U1000.BJ44:2.54mm
A A
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE

REVISION
R
3.0.0
11 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
94 28 6 BI MEM_A_DQ<0> AL6 SA_DQ0 U1000 SA_CLK0 BB31 MEM_A_CLK_P<0>

OUT 6 27 94 94 28 6 BI MEM_B_DQ<0> AL4 SB_DQ0 U1000 SB_CLK0 BF33 MEM_B_CLK_P<0>
OUT 6 29 94
94 28 6 BI MEM_A_DQ<1> AL8 SA_DQ1 IVY-BRIDGE SA_CLK0* BA32 MEM_A_CLK_N<0> OUT 6 27 94 94 28 6 BI MEM_B_DQ<1> AK3 SB_DQ1 IVY-BRIDGE SB_CLK0* BH33 MEM_B_CLK_N<0> OUT 6 29 94
94 28 6 MEM_A_DQ<2> AP7 SA_DQ2 BGA OMIT_TABLE 94 28 6 MEM_B_DQ<2> AP3 SB_DQ2 BGA OMIT_TABLE
BI BI
94 28 6 MEM_A_DQ<3> AM5 SA_DQ3 (3 OF 11) SA_CKE0 BC18 MEM_A_CKE<0> 6 27 94 94 28 6 MEM_B_DQ<3> AR2 SB_DQ3 (4 OF 11) SB_CKE0 BD25 MEM_B_CKE<0> 6 29 94
BI OUT BI OUT
D 94 28 6
94 28 6
BI
BI
MEM_A_DQ<4>
MEM_A_DQ<5>
AK7
AL10
SA_DQ4
SA_DQ5 SA_CLK1 AW34 MEM_A_CLK_P<1>
OUT 6 27 94
94 28 6
94 28 6
BI
BI
MEM_B_DQ<4>
MEM_B_DQ<5>
AL2
AK1
SB_DQ4
SB_DQ5 SB_CLK1 BF37 MEM_B_CLK_P<1>
OUT 6 29 94
D
94 28 6 MEM_A_DQ<6> AN10 SA_DQ6 SA_CLK1* AY33 MEM_A_CLK_N<1> 6 27 94 94 28 6 MEM_B_DQ<6> AP1 SB_DQ6 SB_CLK1* BH37 MEM_B_CLK_N<1> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<7> AM9 SA_DQ7 94 28 6 MEM_B_DQ<7> AR4 SB_DQ7
BI BI
94 28 6 MEM_A_DQ<8> AR10 SA_DQ8 SA_CKE1 BD17 MEM_A_CKE<1> 6 27 94 94 28 6 MEM_B_DQ<8> AV3 SB_DQ8 SB_CKE1 BJ26 MEM_B_CKE<1> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<9> AR8 SA_DQ9 94 28 6 MEM_B_DQ<9> AU4 SB_DQ9
BI BI
94 28 6 MEM_A_DQ<10> AV7 SA_DQ10 SA_CS0* BD41 MEM_A_CS_L<0> 6 27 94 94 28 6 MEM_B_DQ<10> BA4 SB_DQ10 SB_CS0* BE40 MEM_B_CS_L<0> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<11> AY5 SA_DQ11 SA_CS1* BD45 MEM_A_CS_L<1> 6 27 94 94 28 6 MEM_B_DQ<11> BB1 SB_DQ11 SB_CS1* BH41 MEM_B_CS_L<1> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<12> AT5 SA_DQ12 94 28 6 MEM_B_DQ<12> AV1 SB_DQ12
BI BI
94 28 6 MEM_A_DQ<13> AR6 SA_DQ13 SA_ODT0 BB41 MEM_A_ODT<0> 6 27 94 94 28 6 MEM_B_DQ<13> AU2 SB_DQ13 SB_ODT0 BG42 MEM_B_ODT<0> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<14> AW6 SA_DQ14 SA_ODT1 BC46 MEM_A_ODT<1> 6 27 94 94 28 6 MEM_B_DQ<14> BA2 SB_DQ14 SB_ODT1 BH45 MEM_B_ODT<1> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<15> AT9 SA_DQ15 94 28 6 MEM_B_DQ<15> BB3 SB_DQ15
BI BI
94 28 6 MEM_A_DQ<16> BA6 SA_DQ16 SA_DQS0* AN8 MEM_A_DQS_N<0> 6 28 94 94 28 6 MEM_B_DQ<16> BC2 SB_DQ16 SB_DQS0* AN4 MEM_B_DQS_N<0> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<17> BA8 SA_DQ17 SA_DQS1* AU6 MEM_A_DQS_N<1> 6 28 94 94 28 6 MEM_B_DQ<17> BF7 SB_DQ17 SB_DQS1* AW2 MEM_B_DQS_N<1> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<18> BG6 SA_DQ18 SA_DQS2* BC6 MEM_A_DQS_N<2> 6 28 94 94 28 6 MEM_B_DQ<18> BF11 SB_DQ18 SB_DQS2* BH9 MEM_B_DQS_N<2> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<19> AY9 SA_DQ19 SA_DQS3* BD9 MEM_A_DQS_N<3> 6 28 94 94 28 6 MEM_B_DQ<19> BJ10 SB_DQ19 SB_DQS3* BF15 MEM_B_DQS_N<3> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<20> AW8 SA_DQ20 SA_DQS4* BC50 MEM_A_DQS_N<4> 6 28 94 94 28 6 MEM_B_DQ<20> BC4 SB_DQ20 SB_DQS4* BF51 MEM_B_DQS_N<4> 6 28 94
BI BI BI BI
MEMORY CHANNEL A
94 28 6 MEM_A_DQ<21> BB7 SA_DQ21 SA_DQS5* BB55 MEM_A_DQS_N<5> 6 28 94 94 28 6 MEM_B_DQ<21> BH7 SB_DQ21 SB_DQS5* BH57 MEM_B_DQS_N<5> 6 28 94
BI BI BI BI
MEM_A_DQ<22> BC8 SA_DQ22 SA_DQS6* BD59 MEM_A_DQS_N<6> MEM_B_DQ<22> BH11 SB_DQ22 SB_DQS6* AY63 MEM_B_DQS_N<6>
MEMORY CHANNEL B
94 28 6 BI BI 6 28 94 94 28 6 BI BI 6 28 94
94 28 6 MEM_A_DQ<23> BE4 SA_DQ23 SA_DQS7* AU60 MEM_A_DQS_N<7> 6 28 94 94 28 6 MEM_B_DQ<23> BG10 SB_DQ23 SB_DQS7* AN62 MEM_B_DQS_N<7> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<24> AW12 SA_DQ24 94 28 6 MEM_B_DQ<24> BJ14 SB_DQ24
BI BI
94 28 6 MEM_A_DQ<25> AV11 SA_DQ25 SA_DQS0 AN6 MEM_A_DQS_P<0> 6 28 94 94 28 6 MEM_B_DQ<25> BG14 SB_DQ25 SB_DQS0 AN2 MEM_B_DQS_P<0> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<26> BB11 SA_DQ26 SA_DQS1 AU8 MEM_A_DQS_P<1> 6 28 94 94 28 6 MEM_B_DQ<26> BF17 SB_DQ26 SB_DQS1 AW4 MEM_B_DQS_P<1> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<27> BA12 SA_DQ27 SA_DQS2 BD5 MEM_A_DQS_P<2> 6 28 94 94 28 6 MEM_B_DQ<27> BJ18 SB_DQ27 SB_DQS2 BF9 MEM_B_DQS_P<2> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<28> BE8 SA_DQ28 SA_DQS3 BC10 MEM_A_DQS_P<3> 6 28 94 94 28 6 MEM_B_DQ<28> BF13 SB_DQ28 SB_DQS3 BH15 MEM_B_DQS_P<3> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<29> BA10 SA_DQ29 SA_DQS4 BB51 MEM_A_DQS_P<4> 6 28 94 94 28 6 MEM_B_DQ<29> BH13 SB_DQ29 SB_DQS4 BH51 MEM_B_DQS_P<4> 6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<30> BD11 SA_DQ30 SA_DQS5 BD55 MEM_A_DQS_P<5> 6 28 94 94 28 6 MEM_B_DQ<30> BH17 SB_DQ30 SB_DQS5 BF57 MEM_B_DQS_P<5> 6 28 94
C
BI BI BI BI
C 94 28 6
94 28 6
BI MEM_A_DQ<31>
MEM_A_DQ<32>
BE12
BB49
SA_DQ31
SA_DQ32
SA_DQS6
SA_DQS7
BD61
AV61
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
BI 6 28 94
6 28 94
94 28 6
94 28 6
BI MEM_B_DQ<31>
MEM_B_DQ<32>
BG18
BH49
SB_DQ31
SB_DQ32
SB_DQS6
SB_DQS7
AY65
AN64
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
BI 6 28 94
6 28 94
BI BI BI BI
94 28 6 MEM_A_DQ<33> AY49 SA_DQ33 94 28 6 MEM_B_DQ<33> BF47 SB_DQ33
BI BI
94 28 6 MEM_A_DQ<34> BE52 SA_DQ34 SA_MA0 BD27 MEM_A_A<0> 6 27 94 94 28 6 MEM_B_DQ<34> BH53 SB_DQ34 SB_MA0 BF31 MEM_B_A<0> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<35> BD51 SA_DQ35 SA_MA1 BA28 MEM_A_A<1> 6 27 94 94 28 6 MEM_B_DQ<35> BG50 SB_DQ35 SB_MA1 BH31 MEM_B_A<1> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<36> BD49 SA_DQ36 SA_MA2 BB27 MEM_A_A<2> 6 27 94 94 28 6 MEM_B_DQ<36> BF49 SB_DQ36 SB_MA2 BB37 MEM_B_A<2> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<37> BE48 SA_DQ37 SA_MA3 AW26 MEM_A_A<3> 6 27 94 94 28 6 MEM_B_DQ<37> BH47 SB_DQ37 SB_MA3 BC34 MEM_B_A<3> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<38> BA52 SA_DQ38 SA_MA4 BB23 MEM_A_A<4> 6 27 94 94 28 6 MEM_B_DQ<38> BF53 SB_DQ38 SB_MA4 BF27 MEM_B_A<4> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<39> AY51 SA_DQ39 SA_MA5 BA24 MEM_A_A<5> 6 27 94 94 28 6 MEM_B_DQ<39> BJ50 SB_DQ39 SB_MA5 BB33 MEM_B_A<5> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<40> BC54 SA_DQ40 SA_MA6 AY21 MEM_A_A<6> 6 27 94 94 28 6 MEM_B_DQ<40> BF55 SB_DQ40 SB_MA6 BH27 MEM_B_A<6> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<41> AY53 SA_DQ41 SA_MA7 BD21 MEM_A_A<7> 6 27 94 94 28 6 MEM_B_DQ<41> BH55 SB_DQ41 SB_MA7 BG30 MEM_B_A<7> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<42> AW54 SA_DQ42 SA_MA8 BC22 MEM_A_A<8> 6 27 94 94 28 6 MEM_B_DQ<42> BJ58 SB_DQ42 SB_MA8 BH29 MEM_B_A<8> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<43> AY55 SA_DQ43 SA_MA9 BB21 MEM_A_A<9> 6 27 94 94 28 6 MEM_B_DQ<43> BH59 SB_DQ43 SB_MA9 BF29 MEM_B_A<9> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<44> BD53 SA_DQ44 SA_MA10 AW38 MEM_A_A<10> 6 27 94 94 28 6 MEM_B_DQ<44> BJ54 SB_DQ44 SB_MA10 AY37 MEM_B_A<10> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<45> BB53 SA_DQ45 SA_MA11 AW22 MEM_A_A<11> 6 27 94 94 28 6 MEM_B_DQ<45> BG54 SB_DQ45 SB_MA11 BJ30 MEM_B_A<11> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<46> BE56 SA_DQ46 SA_MA12 BA20 MEM_A_A<12> 6 27 94 94 28 6 MEM_B_DQ<46> BG58 SB_DQ46 SB_MA12 AW30 MEM_B_A<12> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<47> BA56 SA_DQ47 SA_MA13 BB45 MEM_A_A<13> 6 27 94 94 28 6 MEM_B_DQ<47> BF59 SB_DQ47 SB_MA13 BA40 MEM_B_A<13> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<48> BD57 SA_DQ48 SA_MA14 BE20 MEM_A_A<14> 6 27 94 94 28 6 MEM_B_DQ<48> BA64 SB_DQ48 SB_MA14 BB29 MEM_B_A<14> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<49> BF61 SA_DQ49 SA_MA15 AW18 MEM_A_A<15> 6 27 94 94 28 6 MEM_B_DQ<49> BC62 SB_DQ49 SB_MA15 BE28 MEM_B_A<15> 6 29 94
BI OUT BI OUT
94 28 6 MEM_A_DQ<50> BA60 SA_DQ50 94 28 6 MEM_B_DQ<50> AU62 SB_DQ50
BI BI
94 28 6 MEM_A_DQ<51> BB61 SA_DQ51 94 28 6 MEM_B_DQ<51> AW64 SB_DQ51
BI BI
94 28 6 MEM_A_DQ<52> BE60 SA_DQ52 94 28 6 MEM_B_DQ<52> BA62 SB_DQ52
BI BI
94 28 6 MEM_A_DQ<53> BD63 SA_DQ53 94 28 6 MEM_B_DQ<53> BC64 SB_DQ53
BI BI
94 28 6 MEM_A_DQ<54> BB59 SA_DQ54 94 28 6 MEM_B_DQ<54> AU64 SB_DQ54
BI BI
94 28 6 MEM_A_DQ<55> BC58 SA_DQ55 94 28 6 MEM_B_DQ<55> AW62 SB_DQ55
BI BI
94 28 6 MEM_A_DQ<56> AW58 SA_DQ56 94 28 6 MEM_B_DQ<56> AR64 SB_DQ56
BI BI
B 94 28 6
94 28 6
BI
BI
MEM_A_DQ<57>
MEM_A_DQ<58>
AY59
AL60
SA_DQ57
SA_DQ58
94 28 6
94 28 6
BI
BI
MEM_B_DQ<57>
MEM_B_DQ<58>
AT65
AL64
SB_DQ57
SB_DQ58
B
94 28 6 MEM_A_DQ<59> AP61 SA_DQ59 94 28 6 MEM_B_DQ<59> AM65 SB_DQ59
BI BI
94 28 6 MEM_A_DQ<60> AW60 SA_DQ60 94 28 6 MEM_B_DQ<60> AR62 SB_DQ60
BI BI
94 28 6 MEM_A_DQ<61> AY57 SA_DQ61 94 28 6 MEM_B_DQ<61> AT63 SB_DQ61
BI BI
94 28 6 MEM_A_DQ<62> AN60 SA_DQ62 94 28 6 MEM_B_DQ<62> AL62 SB_DQ62
BI BI
94 28 6 MEM_A_DQ<63> AR60 SA_DQ63 94 28 6 MEM_B_DQ<63> AM63 SB_DQ63
BI BI
94 27 6 MEM_A_BA<0> BA36 SA_BS0 94 29 6 MEM_B_BA<0> BJ38 SB_BS0

OUT OUT
94 27 6 MEM_A_BA<1> BC38 SA_BS1 94 29 6 MEM_B_BA<1> BD37 SB_BS1
OUT OUT
94 27 6 MEM_A_BA<2> BB19 SA_BS2 94 29 6 MEM_B_BA<2> AY29 SB_BS2
OUT OUT
94 27 6 MEM_A_CAS_L BE44 SA_CAS* 94 29 6 MEM_B_CAS_L BH39 SB_CAS*

OUT OUT
94 27 6 MEM_A_RAS_L BE36 SA_RAS* 94 29 6 MEM_B_RAS_L BG38 SB_RAS*
OUT OUT
94 27 6 MEM_A_WE_L BA44 SA_WE* 94 29 6 MEM_B_WE_L BF39 SB_WE*
OUT OUT
A SYNC_DATE=06/15/2010 A
PAGE TITLE
CPU DDR3 INTERFACES

DRAWING NUMBER SIZE

REVISION
R
3.0.0
12 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
=PP3V3_S0_CPU_VCCIO_SEL 7 105 49 14 12 7 =PPVCORE_S0_CPU
=PPVCORE_S0_CPU 7 12 14 49 105
CPU:SNB
1
R1320 Pullup for SNB
10K
R46 U1000 H35
5%
R42 IVY-BRIDGE H31
1/16W
R40 BGA H29
MF-LF OMIT_TABLE
=PPVCCSA_S0_CPU
=PP1V05_S0_CPU_VCCIO 7 9 10 12 13 14
15 12 7 402
2 R36 (6 OF 11) H25
R34
CORE POWER G44
PLACE_NEAR=R1310.1:2.54mm =PP1V05_S0_CPU_VCCIO 7 9 10 12 13 14
1
W17 U1000 VCCIO_SEL AJ8 CPU_VCCIO_SEL R29 G40
R1300 1 W15 IVY-BRIDGE R27 G38
75 R1302
130 W12 BGA AV23 R23 G34
1% PLACE_NEAR=U1000.A50:2.54mm OMIT_TABLE =PP1V5_S3_CPU_VCCDQ 7 15
1/16W
MF-LF
1%
1/16W
U17 (9 OF 11) AT23 R21 G32
2
402 MF-LF
U15 VCCDQ AP23 N45 G28
R1312 2
402
93 69 CPU_VIDSOUT 402 1/16W 0 1 2 5% MF-LF CPU_VIDSOUT_R U12 AL23 N43 G26

BI
T16 N39 F45
R1311
93 69 CPU_VIDSCLK 402 1/16W 0 1 2 5% MF-LF CPU_VIDSCLK_R T14 AK65 =PP1V8_S0_CPU_VCCPLL_R 7 14 N37 F43
OUT
T11 AK63 N33 F41
R1310 VCCPLL
93 69 CPU_VIDALERT_L 402 1/16W 1 2 5% MF-LF CPU_VIDALERT_L_R N18 AK61 N30 F37
IN
N16
VCCSA N26 F35
43 PLACE_NEAR=U1000.B51:38mm
N14 AV21 =PP1V05_S0_CPU_VCCPQE 7 8 14 N24 F31
M17 AT21 N20 F29
M15
VCCPQE AP21 M46 F25
=PPVCORE_S0_CPU 7 12 14 49 105
C =PP1V05_S0_CPU_VCCIO 7 9 10 12 13 14
=PPVCORE_S0_CPU 7 12 14 49
105
M12
M11
AL21 M42
M40
E44
E40
C
=PPVCORE_S0_CPU_VCCAXG 7 12 13 =PPVCORE_S0_CPU_VCCAXG 7 12 13 15
15 L18 BJ60 M36 E38
L14 BJ6 M34 E34

PLACE_SIDE=BOTTOM
BH61 M29 E32
PLACE_SIDE=BOTTOM =PPVCCSA_S0_CPU 7 12
PLACE_SIDE=BOTTOM 15 A50 VIDSOUT BH5 M27 E28
PLACE_NEAR=U1000.AW10:50.8mm
NOSTUFF NOSTUFF NOSTUFF D51 VIDSCLK BE64 M23 E26
1 1 1 1 1 1 B51 BE2 M21 D45
R1360 R1362 R1366 R1364 R1370 R1368 VIDALERT*
PLACE_NEAR=U1000.B47:50.8mm 100 100 100 49.9 49.9 100 BD65 L44 VCC VCC D43
1% 1% 1% NOSTUFF NOSTUFF 1% 1% 1%
PLACE_SIDE=BOTTOM 93 66 CPU_VCCSA_VID<0> AE10 VCCSA_VID0 BD1 L40 D41
1/16W 1/16W 1/16W 1/20W 1/20W 1/16W
OUT
MF-LF MF-LF MF-LF MF MF MF-LF
93 66 CPU_VCCSA_VID<1> AG10 VCCSA_VID1 F65 L38 D37
402
2 2
402
2
402 201
2 2
201
2
402 OUT
PLACE_SIDE=BOTTOM (IPU)
PLACE_NEAR=U1000.F49:50.8mm
VSS_NCTF F1 L34 D35
93 69 CPU_VCCSENSE_P B47 VCC_SENSE E64 L32 D31

OUT
93 69 CPU_VCCSENSE_N A46 VSS_SENSE E2 L28 D29
OUT
B61 L26 C44
93 69 CPU_AXG_SENSE_P F49 VAXG_SENSE B5 L22 C40

OUT
93 69 CPU_AXG_SENSE_N E50 VSSAXG_SENSE A60 K45 C38
OUT
A6 K43 C34
93 71 CPU_VCCIOSENSE_P AW10 VCCIO_SENSE K41 C32

OUT
93 71 CPU_VCCIOSENSE_N AU10 VSS_SENSE_VCCIO DC_TEST_A4 A4 TP_DC_TEST_A4 K37 C28
OUT
PLACE_NEAR=U1000.E50:50.8mm DC_TEST_A62 A62 TP_DC_TEST_A62 6 K35 C26
PLACE_SIDE=BOTTOM TP_CPU_VDDQSENSEP AY19 VDDQ_SENSE DC_TEST_A64 A64 DC_TEST_B63_A64 K31 B45

1
R1367 TP_CPU_VDDQSENSEN AW20 VSS_SENSE_VDDQ DC_TEST_B3 B3 6 DC_TEST_B3_C2 K29 B43
100
1% DC_TEST_B63 B63 K25 B41
1/16W
93 66 CPU_VCCSASENSE K3 VCCSA_SENSE DC_TEST_B65 B65 DC_TEST_B65_C64 J44 B37
MF-LF OUT
402
2 BF1 J40 B35
DC_TEST_BF1 TP_DC_TEST_BF1
B
NOSTUFF
TP_CPU_DIE_SENSE F47 VCC_DIE_SENSE DC_TEST_BF65
DC_TEST_BG2
BF65
BG2
TP_DC_TEST_BF65
6 DC_TEST_BH1_BG2
J38
J34
B31
B29
B
CPU_VCC_VALSENSE_P D47 VCC_VAL_SENSE DC_TEST_BG64 BG64 DC_TEST_BG64_BH65 J32 A44
CPU_VCC_VALSENSE_N C48 VSS_VAL_SENSE DC_TEST_BH1 BH1 J28 A40
DC_TEST_BH3 BH3 6 DC_TEST_BH3_BJ2 J26 A38
CPU_AXG_VALSENSE_P B49 VAXG_VAL_SENSE DC_TEST_BH63 BH63 DC_TEST_BJ64_BH63 H45 A34
CPU_AXG_VALSENSE_N A48 VSSAXG_VAL_SENSE DC_TEST_BH65 BH65 H43 A32
PLACE_NEAR=U1000.A46:50.8mm PLACE_SIDE=BOTTOM DC_TEST_BJ2 BJ2 H41 A28

PLACE_NEAR=U1000.AU10:50.8mm
PLACE_SIDE=BOTTOM DC_TEST_BJ4 BJ4 TP_DC_TEST_BJ4 H37 A26
1 1
R1361 R1363 DC_TEST_BJ62 BJ62 TP_DC_TEST_BJ62
100 100 PLACE_SIDE=BOTTOM
NOSTUFF NOSTUFF 1 1
DC_TEST_BJ64 BJ64
1%
1/16W
1%
1/16W
R1314 R1313
MF-LF MF-LF 10K 10K DC_TEST_C2 C2
1
402
2 2
402
R1365 1
5% 5%
DC_TEST_C64 C64
49.9
R1371
PLACE_SIDE=BOTTOM
1/16W
MF-LF
1/16W
MF-LF
NOSTUFF 1% 49.9 402 402 DC_TEST_D1 D1 TP_DC_TEST_D1
2 2
1/20W 1% NOSTUFF
MF 1/20W DC_TEST_D65 D65 TP_DC_TEST_D65 6
201 MF
2
201
2
NOTE: Intel validation sense lines per doc 439028 rev1.0

HR_PPDG sections 6.2.1 and 6.3.1.
A SYNC_MASTER=K92_MLB SYNC_DATE=08/03/2010 A
PAGE TITLE
CPU POWER
DRAWING NUMBER SIZE

REVISION
R
3.0.0
13 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BJ56 U1000 AW16 AG12 U1000 L20
BJ52 IVY-BRIDGE AV65 AF65 IVY-BRIDGE L16

BJ48 BGA OMIT_TABLE AV63 AF63 BGA OMIT_TABLE L12
BJ40 (10 OF 11) AV59 AF61 (11 OF 11) L8
BJ32 AV57 AF11 K39
BJ24 AV50 AF9 K33
BJ20 AV44 AF5 K27
D
BJ16
BJ12
AV38
AV31
AE57
AD16
K1
J64
D
BJ8 AV25 AD14 J60 =PPVCORE_S0_CPU_VCCAXG =PP1V5_S3_CPU_VCCDDR
15 12 7 7 10 15 26
BG60 AV19 AD7 J56
BG56 AV9 AD3 J52 AH65 U1000 BJ36
BG52 AV5 AD1 J48 AH63 IVY-BRIDGE BJ28

BG48 AU54 AC64 J46 AH61 BGA OMIT_TABLE BG40
BG44 AU47 AC62 J42 AH58 (8 OF 11) BG32

=PP1V05_S0_CPU_VCCIO =PP1V05_S0_CPU_VCCIO
14 13 12 10 9 7 7 9 10 12 13 14
BG36 AU41 AC60 J36 AH56 BD47
BG28 AU35 AC57 J30 AG64 BD43
BG24 AU28 AB11 J24 AG62 BD39

AV55 U1000 AN20
BG20 AU22 AB9 J22 AG60 BD31

AV53 IVY-BRIDGE AN18
AV48 BGA AN16

OMIT_TABLE
BG16 AU16 AB5 J18 AF58 BD23
AV17 (7 OF11) AN14
BG12 AU14 AA57 J14 AF56 BB35 IO POWER
AV15 AM11
BG8 AT61 AA17 J10 AE64 AY47
AV12 AL55
BF5 AT57 AA15 J6 AE62 AY43
AU58 AL53
BE62 AT50 AA12 H39 AE60 AY39
AU56 AL48
BE58 AT44 Y65 H33 AD65 AY35
AU52 AL17
BE54 AT38 Y63 H27 AD63 AY31
AU49 AL15
BE50 AT31 Y61 H3 AD61 AY27
AU20 AL12
BE46 AT25 Y7 G62 AD58 AY23
AU18 AK58
BE42 AT19 Y3 G58 AD56 AV46
AT55 AK56
BE38 AT11 Y1 G54 AB65 AV42
AT53 AJ17
BE34 AT7 W57 G50 AB63 AV40
AT48 AJ15
BE30 AT3 V16 G46 AB61 AV36
AT17 AJ12
BE26 AT1 V14 G42 AB58 AV34
AT15 AH16
BE22 AR54 V11 G36 AB56 AV29 VCCIO VCCIO
C BE18
BE14
AR47
AR41
V9
V5
G30
G24
AA64
AA62
AV27
AU45
AT12
AR58
AH14
AH11 C
AR56 AF16
BE10 AR35 U64 G20 AA60 AU43
GRAPHIC CORE POWER

AR52 AF14
BD35 AR28 U62 G16 Y58 AU39
AR49 AE17
IO POWER DDR3
BD7 AR22 U60 G12 Y56 AU37
AR20 AE15
BD3 AP65 U57 G8 W64 AU33
AR18 AE12
BC60 AP63 T7 VSS VSS F39 W62 AU30
AR16 AD11
BC56 AP57 T3 F33 W60 AU26
AR14 AC17
BC52 AP50 T1 F27 V65 AU24
AP55 AC15
BC48 AP44 R57 E60 V63 AT46
VAXG AP53 AC12
BC44 VSS VSS AP38 R50 E56 V61 AT42
AP48 AB16
BC40 AP31 R44 E52 V58 AT40
AN58 AB14
BC36 AP25 R38 E48 V56 VDDQ AT36
AN56 Y16
BC32 AP19 R31 E46 T65 AT34
AN52 Y14
BC28 AP17 R25 E42 T63 AT29
AN49 Y11
BC26 AP15 R19 E36 T61 AT27
BC24 AP12 R17 E30 T58 AR45
BC20 AP11 R15 E24 T56 AR43
BC16 AP9 R12 E22 R64 AR39
BC12 AP5 P65 E18 R62 AR37
BB65 AN54 P63 E14 R60 AR33
BB63 AN47 P61 E10 R55 AR30
BB47 AN41 P11 E6 R53 AR26

BB39 AN35 P9 E4 R48 AR24
BB9 AN28 P5 D63 N64 AP46
BB5 AN22 N54 D39 N62 AP42
B BA58
BA54
AM61
AM7
N47
N41
D33
D27
N60
N58
AP40
AP36
B
BA50 AM3 N35 C58 N56 AP34
BA46 AM1 N28 C54 N52 AP29
BA42 AL57 N22 C50 N49 AP27
BA38 AL50 M57 C46 M65 AN45
BA34 AL44 M50 C42 M63 AN43
BA30 AL38 M44 C36 M61 AN39
BA26 AL31 M38 C30 M59 AN37
BA22 AL25 M31 C20 M55 AN33
BA18 AL19 M25 C16 M53 AN30
BA14 AK16 M19 C12 M48 AN26
AY61 AK14 M7 C8 L56 AN24
AY11 AK11 M3 B39 L52 AL46

AY7 AK9 M1 B33 L48 AL42
AY3 AK5 L64 B27 AL40
AY1 AJ64 L62 A56 AL36

AW56 AJ62 L60 A52 AL34
AW52 AJ60 L58 A42 AL29
AW48 AJ57 L54 A36 AL27
AW44 AH7 L50 A30
AW40 AH3 L46 A24
AW36 AH1 L42 A20
AW32 AG57 L36 A16
AW28 AG17 L30 A12
AW24 AG15 L24 A8
A A
PAGE TITLE
CPU POWER AND GND

DRAWING NUMBER SIZE

REVISION
R
3.0.0
14 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE DECOUPLING
Intel recommendation: 4x 470uF 4mOhm, 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 8x 1uF 0402 (NOSTUFF)
Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF)
PLACEMENT_NOTE (C1600-C16C7):
105 49 12 7 =PPVCORE_S0_CPU
Place on bottom side of U1000
U100.
1 C1600 1 C1601 1 C1602 1 C1603 1 C1604 1 C1605 1 C1606 1 C1607 1 C1608 1 C1609 1 C1610 1 C1611 1 C1612 1 C1613 1 C1614 1 C1615 1 C1616 1 C1617 1 C1618 1 C1619
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
D 2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
2
10%
10V
X5R
402
D
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1
C16A0 1
C16A1 1
C16A2 1
C16A3 1
C16A4 1
C16A5 1
C16A6 1
C16A7 1
C16A8 1
C16A9 1
C16B0 1
C16B1 1
C16B2 1
C16B3 1
C16B4 1
C16B5 1
C16B6 1
C16B7 1
C16B8 1
C16B9
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF

1
C16C0 1
C16C1 1
C16C2 1
C16C3 1
C16C4 1
C16C5 1
C16C6 1
C16C7
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
0201 0201 0201 0201 0201 0201 0201 0201
PLACEMENT_NOTE (C1620-C1623):
Place near U1000 on bottom side

CRITICAL CRITICAL CRITICAL CRITICAL
1
C1620 1
C1621 1
C1622 1
C1623
10UF 10UF 10UF 10UF
20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
0402-1 0402-1 0402-1 0402-1
C PLACEMENT_NOTE (C1624-C16D5): C
Place near inductors
Place near
on inductors
bottom
Place side.
near
on inductors
bottom side.
on bottom side.
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1
C1624 1
C1625 1
C1626 1
C1627 1
C1628 1
C1629 1
C1630 1
C1631 1
C1632 1
C1633 1
C1634 1
C1635 1
C1636 1
C1637 1
C1638 1
C1639 1
C16D0 1
C16D1 1
C16D2 1
C16D3 1
C16D4 1
C16D5
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
Place near inductors on bottom side.
NOSTUFF
1
C1640 1
C1641 1
C1642 1
C1643 1
C1644
470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 470UF-4MOHM
20% 20% 20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT POLY-TANT POLY-TANT
D2T-SM D2T-SM1 D2T-SM1 D2T-SM1 D2T-SM1
CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

U100.
CPU VCCPLL DECOUPLING
13 12 10 9 7 =PP1V05_S0_CPU_VCCIO
B 1
C1646 1
C1647 1
C1648 1
C1649 1
C1650 1
C1651 1
C1652 1
C1653 1
C1654 1
C1655 1
C1656 1
C1657 1
C1658
R1600
0
=PP1V8_S0_CPU_VCCPLL_R 7 12 B
7 =PP1V8_S0_CPU_VCCPLL 1 2
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 5% CRITICAL
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
1/16W
MF-LF 1
C1685 1
C1686 1 C1687
402 402 402 402 402 402 402 402 402 402 402 402 402 402 330UF-0.006OHM
1UF 1UF 20%
10% 10% 2V
10V 10V POLY
2 X5R 2 X5R 2
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA CASE-D2-SM
402 402
PLACE_NEAR=U1000.AK61:5 mm
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
C1659 1
C1660 1
C1661 1
C1662 1
C1663 1
C1664 1
C1665 1
C1666 1
C1667 1
C1668 1
C1669 1
C1670 1
C1671
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF CPU VCCPLL Low pass filter
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402
Place near U1000 on bottom side

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C1672 1
C1673 1
C1674 1
C1675 1
C1676 1
C1677 1
C1678 1
C1679 1
C1680 1
C1681
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 603 603 603 603 603 603 603 603 603
Place near inductors on bottom side

CRITICAL
1 C1682 1 C1683
330UF-0.006OHM 330UF-0.006OHM
20% 20%
2V 2V
A 2 POLY
CASE-D2-SM
2 POLY
CASE-D2-SM
CRITICAL PAGE TITLE
CPU DECOUPLING-I
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402 DRAWING NUMBER SIZE
R1601 Apple Inc. 051-9585 D

0.010 REVISION
1 2
1%
=PP1V05_S0_CPU_VCCPQE 7 8 12 R
3.0.0
1/4W
MF
1
C1684 NOTICE OF PROPRIETARY PROPERTY: BRANCH
0603 1UF THE INFORMATION CONTAINED HEREIN IS THE
10%
10V
2 X5R THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
16 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VAXG DECOUPLING
Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 8x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)
Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)
13 12 7 =PPVCORE_S0_CPU_VCCAXG
U100.
D NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF D

1 C1700 1 C1701 1 C1702 1 C1703 1 C1704 1 C1705 1 C1706 1 C1707 1 C1708 1 C1709 1 C1710 1 C1711 1 C1712 1 C1713 1 C1714 1 C1715 1 C1716 1 C1717
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
Place close to U1000 on bottom side
NOSTUFF NOSTUFF
1
C1718 1
C1719 1
C1720 1
C1721 1
C1722 1
C1723 1
C1724 1
C1725
20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1
Place near inductors on bottom side.
NOSTUFF NOSTUFF
1 C1726 1 C1727 1 C1728 1 C1729 1 C1730 1 C1731 1 C1732 1 C1733
20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1 2 X5R-CERM1
0603 0603 0603 0603 0603 0603 0603 0603
NOSTUFF
C 1
C1734
CRITICAL
1
CRITICAL
C1735 1
CRITICAL
C1737 C
470UF-4MOHM 470UF-4MOHM 470UF-4MOHM
20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT
D2T-SM1 D2T-SM1 D2T-SM1
CPU VDDQ/VCCDQ DECOUPLING CPU VCCSA DECOUPLING

26 13 10 7 =PP1V5_S3_CPU_VCCDDR
U100. 12 7 =PPVCCSA_S0_CPU Place on bottom side of U1000
U100.
1
C1738 1
C1739 1
C1740 1
C1741 1
C1742 1
C1743 1
C1744 1
C1745 1
C1746 1
C1747
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
1 C1758 1 C1759 1 C1760 1 C1761 1 C1762
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 1UF 1UF 1UF 1UF 1UF
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10% 10% 10% 10% 10%
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 10V 10V 10V 10V 10V
402 402 402 402 402 402 402 402 402 402 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402
Place close to U1000 on bottom side
1
C1748 1
C1749 1
C1750 1
C1751 1
C1752 1
C1753 1
C1754 1
C1755
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
1
C1763 1
C1764 1
C1765 1
C1766 1
C1767
2 2 2 2 2 2 2 2
X5R X5R X5R X5R X5R X5R X5R X5R 10UF 10UF 10UF 10UF 10UF
B 603 603 603 603 603 603 603 603
2
20%
6.3V
X5R
603
2
20%
6.3V
X5R
603
2
20%
6.3V
X5R
603
2
20%
6.3V
X5R
603
2
20%
6.3V
X5R
603
B
Place near inductors on bottom side
1 C1756
330UF-0.006OHM
20%
1
2
2V
POLY
C1768
CASE-D2-SM 330UF-0.006OHM
20%
2 2V
POLY
CASE-D2-SM
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1700
0.010
1 2 =PP1V5_S3_CPU_VCCDQ 7 12
1%
1/4W
MF
0603
1
C1757
1UF
10%
10V
2 X5R
402
PAGE TITLE
CPU DECOUPLING-II
DRAWING NUMBER SIZE

REVISION
R
3.0.0
17 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE OMIT_TABLE
24 IN SYSCLK_CLK32K_RTC A20
RTCX1 U1800 FWH0/LAD0 C38 LPC_AD_R<0> 16 96 36 IN PCIE_ENET_D2R_N BG34
PERN1 U1800 SMBALERT*/GPIO11 E12 PCH_GPIO11 16
C20
RTCX2 PANTHERPOINT FWH1/LAD1 A38 LPC_AD_R<1> PCIE_ENET_D2R_P BJ34
PERP1 PANTHERPOINT
NC MOBILE
16 96 36 IN
MOBILE SMBCLK H14 SMBUS_PCH_CLK OUT 48 96
B37 LPC_AD_R<2> =PP3V3_S0_PCH PCIE_ENET_R2D_C_N AV32
FWH2/LAD2 16 7 22 96 36 OUT PETN1 C9
FCBGA
C37 AU32
FCBGA SMBDATA SMBUS_PCH_DATA BI 48 96
(1 OF 10) FWH3/LAD3 LPC_AD_R<3> 16 96 36 OUT PCIE_ENET_R2D_C_P PETP1 (2 OF 10)
D20 (IPU)
16 RTC_RESET_L RTCRST* D36
1
R1820 BE34
LPC_FRAME_R_L PCIE_AP_D2R_N
SMBUS
FWH4/LFRAME* 16 96 32 IN PERN2
G22 10K BF34 A12
16 PCH_SRTCRST_L SRTCRST* E36 5% 96 32 IN PCIE_AP_D2R_P PERP2 SML0ALERT*/GPIO60 USB_EXTB_SEL_XHCI OUT 16 25
(IPU) LDRQ0* TP_LPC_DREQ0_L
RTC
LPC
6 1/20W BB32
K22 K36 MF 96 32 OUT PCIE_AP_R2D_C_N PETN2 C8
16 PCH_INTRUDER_L INTRUDER* LDRQ1*/GPIO23 TBT_PWR_EN_PCH OUT 24
2 201 AY32 SML0CLK SML_PCH_0_CLK OUT 48 96
(IPU) PCIE_AP_R2D_C_P PETP2
D 16 PCH_INTVRMEN_L C17
INTVRMEN SERIRQ V5 LPC_SERIRQ BI 6 45 47
96 32
96 38
OUT
IN PCIE_FW_D2R_N BG36
PERN3
SML0DATA G12 SML_PCH_0_DATA BI 48 96
D
PCIE_FW_D2R_P BJ36
96 38 IN PERP3
HDA_BIT_CLK_R N34 AM3 SATA_HDD_D2R_N PCIE_FW_R2D_C_N AV34 C13 USB_EXTD_SEL_XHCI
96 16 HDA_BCLK SATA0RXN IN 41 95 96 38 OUT PETN3 SML1ALERT*/PCHHOT*/GPIO74 OUT 16
AM1 SATA_HDD_D2R_P PCIE_FW_R2D_C_P AU34
SATA0RXP IN 41 95 96 38 OUT PETP3 E14
L34 AP7 SML1CLK/GPIO58 SML_PCH_1_CLK OUT 48 96
96 16 HDA_SYNC_R HDA_SYNC (IPD-BOOT) SATA0TXN SATA_HDD_R2D_C_N OUT 41 95 BF36 M16
AP5 8 IN PCIE_EXCARD_D2R_N PERN4 SML1DATA/GPIO75 SML_PCH_1_DATA BI 48 96
VSel strap not functional (VCCVRM = 1.8V) SATA0TXP SATA_HDD_R2D_C_P OUT 41 95 BE36
T10 8 IN PCIE_EXCARD_D2R_P PERP4
PCH_SPKR
PCI-E*
16 SPKR (IPD-PLTRST#) AM10 AY34
SATA1RXN SATA_ODD_D2R_N IN 41 95 8 OUT PCIE_EXCARD_R2D_C_N PETN4
AM8 SATA_ODD_D2R_P PCIE_EXCARD_R2D_C_P BB34
SATA1RXP PETP4
IHDA
K34 IN 41 95 8 OUT
HDA_RST_R_L
C-LINK
96 16 HDA_RST* AP11
SATA1TXN SATA_ODD_R2D_C_N OUT 41 95 BG37 M7
AP10
NC_PCIE_5_D2RN PERN5 (IPU/IPD) CL_CLK1 TP_CLINK_CLK 6
E34 SATA1TXP SATA_ODD_R2D_C_P OUT 41 95
BH37
96 57 IN HDA_SDIN0 HDA_SDIN0 (IPD) NC_PCIE_5_D2RP PERP5 T11
G34 AD7 AY36 (IPU/IPD) CL_DATA1 TP_CLINK_DATA 6
6 TP_HDA_SDIN1 HDA_SDIN1 (IPD) SATA2RXN TP_SATA_C_D2RN NC_PCIE_5_R2D_CN PETN5
TP_HDA_SDIN2 C34 AD5 TP_SATA_C_D2RP NC_PCIE_5_R2D_CP BB36 P10 TP_CLINK_RESET_L
6 HDA_SDIN2 (IPD) SATA2RXP PETP5 CL_RST1* 6
TP_HDA_SDIN3 A34 AH5 TP_SATA_C_R2D_CN

6 HDA_SDIN3 (IPD) SATA2TXN BJ38
AH4
NC_PCIE_6_D2RN PERN6
SATA2TXP TP_SATA_C_R2D_CP BG38
A36
NC_PCIE_6_D2RP PERP6
96 24 16 HDA_SDOUT_R HDA_SDO (IPD-BOOT) AB8 AU36
SATA3RXN TP_SATA_D_D2RN 6 NC_PCIE_6_R2D_CN PETN6 M10
AB10 AV36 PEG_A_CLKRQ*/GPIO47 PEGCLKRQA_L_GPIO47 16
C36 SATA3RXP TP_SATA_D_D2RP 6 NC_PCIE_6_R2D_CP PETP6
33 16 OUT JTAG_TBT_TMS HDA_DOCK_EN*/GPIO33 AF3 AB37
SATA3TXN TP_SATA_D_R2D_CN 6 CLKOUT_PEG_A_N TP_PCIE_CLK100M_PEGAN
SATA
ENET_MEDIA_SENSE_RDIV N32 NC_PCIE_7_D2RN BG40
24 16 IN HDA_DOCK_RST*/GPIO13 AF1 PERN7 AB38
SATA3TXP TP_SATA_D_R2D_CP 6 BJ40 CLKOUT_PEG_A_P TP_PCIE_CLK100M_PEGAP
NC_PCIE_7_D2RP PERP7
Y7 TP_SATA_E_D2RN NC_PCIE_7_R2D_CN AY40
J3 SATA4RXN 6 PETN7
23 IN XDP_PCH_TCK JTAG_TCK (IPD) Y5
=PP1V05_S0_PCH_VCCIO_SATA 7 20 22
BB40
SATA4RXP TP_SATA_E_D2RP 6 NC_PCIE_7_R2D_CP PETP7 AV22
H7 AD3 PLACE_NEAR=U1800.Y11:2.54mm CLKOUT_DMI_N DMI_CLK100M_CPU_N OUT 10 93
XDP_PCH_TMS JTAG_TMS (IPU) SATA4TXN TP_SATA_E_R2D_CN
JTAG
23 IN 6 BE38 AU22
AD1
1
R1830 NC_PCIE_8_D2RN PERN8 CLKOUT_DMI_P DMI_CLK100M_CPU_P OUT 10 93
K5 SATA4TXP TP_SATA_E_R2D_CP 6 BC38
23 IN XDP_PCH_TDI JTAG_TDI (IPU) 37.4 NC_PCIE_8_D2RP PERP8
Y3 1% AW38
H1 SATA5RXN TP_SATA_F_D2RN 6 1/20W NC_PCIE_8_R2D_CN PETN8
23 XDP_PCH_TDO JTAG_TDO MF
C
OUT
C
Y1 TP_SATA_F_D2RP NC_PCIE_8_R2D_CP AY38 AM12 TP_PCH_CLKOUT_DPN
SATA5RXP 6
2 201 PETP8 CLKOUT_DP_N OUT 8
AB3 TP_SATA_F_R2D_CN AM13 TP_PCH_CLKOUT_DPP
SATA5TXN 6 CLKOUT_DP_P OUT 8
AB1
=PP1V05_S0_PCH 7 22 Y40
SATA5TXP TP_SATA_F_R2D_CP 6 96 36 OUT PCIE_CLK100M_ENET_N CLKOUT_PCIE0N
Y39 Controlled by PCIECLKRQ5#
T3 96 36 OUT PCIE_CLK100M_ENET_P CLKOUT_PCIE0P
SPI_CLK_R 1
96 47 OUT SPI_CLK Y11 R1831 BF18
SATAICOMPO 95 PCH_SATAICOMP J2 CLKIN_DMI_N PCIE_CLK100M_PCH_N IN 16 96
Y14 Y10
49.9 16 PCIECLKRQ0_L_GPIO73 PCIECLKRQ0*/GPIO73 BE18
96 47 OUT SPI_CS0_R_L SPI_CS0* SATAICOMPI 1% CLKIN_DMI_P PCIE_CLK100M_PCH_P IN 16 96
SPI
1/20W
T1 MF AB49
TP_SPI_CS1_L SPI_CS1* AB12 201 96 38 OUT PCIE_CLK100M_FW_N CLKOUT_PCIE1N
SATA3RCOMPO 2
PCIE_CLK100M_FW_P AB47
V4 AB13 PLACE_NEAR=U1800.AB12:2.54mm 96 38 OUT CLKOUT_PCIE1P BJ30
96 47 OUT SPI_MOSI_R SPI_MOSI (IPD-BOOT) SATA3COMPI 95 PCH_SATA3COMP CLKIN_GND1_N PCH_CLKIN_GNDN1 16
AH1 PCH_SATA3RBIAS FW_CLKREQ_L M1 BG30 PCH_CLKIN_GNDP1
U3 SATA3RBIAS 39 16 IN PCIECLKRQ1*/GPIO18 CLKIN_GND1_P 16
96 47 IN SPI_MISO SPI_MISO (IPU)
PLACE_NEAR=U1800.AH1:2.54mm
P3 PCH_SATALED_L 1 PCIE_CLK100M_AP_N AA48
SATALED* 16 R1832 96 32 OUT CLKOUT_PCIE2N
CLOCKS
PCIE_CLK100M_AP_P AA47 G24 PCH_CLK96M_DOT_N
V14
750 96 32 OUT CLKOUT_PCIE2P CLKIN_DOT_96N IN 16 96
=PPVRTC_G3_PCH 7 17 20 SATA0GP/GPIO21 XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT 23 5% E24
P1 1/20W V10 CLKIN_DOT_96P PCH_CLK96M_DOT_P IN 16 96
SATA1GP/GPIO19 XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT 23 MF 32 16 IN AP_CLKREQ_L PCIECLKRQ2*/GPIO20
(IPU) 2 201
PCIE_CLK100M_EXCARD_N Y37
R1802 1
1
R1803 96 8 OUT CLKOUT_PCIE3N AK7
Y36 CLKIN_SATA_N PCH_CLK100M_SATA_N IN 16 96
20K 20K 96 8 OUT PCIE_CLK100M_EXCARD_P CLKOUT_PCIE3P AK5
5% 5% CLKIN_SATA_P PCH_CLK100M_SATA_P IN 16 96
1/20W 1/20W A8
R1800 1 1
R1801 MF MF 16 IN EXCARD_CLKREQ_L PCIECLKRQ3*/GPIO25
201 2
330K 1M 2 201
5% 5% Y43 K45
1/20W 1/20W 6 TP_PCIE_CLK100M_PE4N CLKOUT_PCIE4N REFCLK14IN PCH_CLK14P3M_REFCLK IN 16 96
MF MF RTC_RESET_L 16 Y45
201 2
2 201
6 TP_PCIE_CLK100M_PE4P CLKOUT_PCIE4P
PCH_SRTCRST_L 16
PCH_INTRUDER_L JTAG_DPMUXUC_TRST_L L12

16 16 OUT PCIECLKRQ4*/GPIO26 H45
CLKIN_PCILOOPBACK PCH_CLK33M_PCIIN IN 24 96
PCH_INTVRMEN_L 16
TP_PCIE_CLK100M_PE5N V45 DOES THIS NEED LENGTH MATCH???

6 CLKOUT_PCIE5N
C1802 1 1
C1803 16 LPC_AD_R<0> R1860 33 1 2 LPC_AD<0> BI 6 45 47 89 96 V46
5% 1/20W MF 201 6 TP_PCIE_CLK100M_PE5P CLKOUT_PCIE5P
1UF 1UF LPC_AD_R<1> R1861 33 1 2 LPC_AD<1> XTAL25_IN V47 SYSCLK_CLK25M_SB_R
B 10%
10V
X5R 2 2
10%
10V
X5R
16
16 LPC_AD_R<2> R1862 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
LPC_AD<2>
BI
BI
6 45 47 89 96
6 45 47 89 96 36 16 IN ENET_CLKREQ_L L14
PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)
XTAL25_OUT V49
NC
16
B
402 402
16 LPC_AD_R<3> R1863 33 1 2 LPC_AD<3> BI 6 45 47 89 96
5% 1/20W MF 201 22 20 7 =PP1V05_S0_PCH_VCCDIFFCLK
16 LPC_FRAME_R_L R1864 33 1 2 LPC_FRAME_L OUT 6 45 47 89 96 6 TP_PCIE_CLK100M_PEBN AB42
CLKOUT_PEG_B_N
5% 1/20W MF 201 AB40
6 TP_PCIE_CLK100M_PEBP CLKOUT_PEG_B_P 1
96 16 HDA_BIT_CLK_R R1810 33 1 2 HDA_BIT_CLK OUT 57 96
R1890
PEGCLKRQB_L_GPIO56 E6
PLACE_NEAR=U1800.N34:1.27mm 5% 1/20W MF 201 16 PEG_B_CLKRQ*/GPIO56 90.9
1%
96 16 HDA_SYNC_R R1811 33 1 2 HDA_SYNC OUT 57 96 1/20W
PLACE_NEAR=U1800.L34:1.27mm 5% 1/20W MF 201 V40 MF
96 75 OUT PEG_CLK100M_N CLKOUT_PCIE6N 201 2
96 16 HDA_RST_R_L R1812 33 1 2 HDA_RST_L OUT 57 96 V42 PLACE_NEAR=U1800.Y47:2.54mm
PLACE_NEAR=U1800.K34:1.27mm 5% 1/20W MF 201 96 75 OUT PEG_CLK100M_P CLKOUT_PCIE6P Y47
XCLK_RCOMP PCH_XCLK_RCOMP
96 24 16 HDA_SDOUT_R R1813 33 1 2 HDA_SDOUT OUT 57 96
T13
PLACE_NEAR=U1800.A36:1.27mm 5% 1/20W MF 201 16 8 IN PEG_CLKREQ_L PCIECLKRQ6*/GPIO45
=PP3V3_SUS_PCH_GPIO 7 17 18 19
=PP3V3_S0_PCH_GPIO K43 TP_PCH_GPIO64_CLKOUTFLEX0

7 17 18 19 30 V38 CLKOUTFLEX0/GPIO64 8
96 33 PCIE_CLK100M_TBT_N CLKOUT_PCIE7N (IPD-PWROK)
CLOCKS
=PP3V3_T29_PCH_GPIO OUT
7 19 NO STUFF V37
PCIE_CLK100M_TBT_P CLKOUT_PCIE7P
FLEX
96 33 OUT F47 TP_PCH_GPIO65_CLKOUTFLEX1
R1840 CLKOUTFLEX1/GPIO65 8
(IPD-PWROK)
R1876 10K 1 2 JTAG_TBT_TMS 16 33 0 35 16 IN TBT_CLKREQ_L K12
PCIECLKRQ7*/GPIO46
5% 1/20W MF 201 93 10 ITPCPU_CLK100M_N 1 2 (IPU-RSMRST#) H47
CLKOUTFLEX2/GPIO66 TP_PCH_GPIO66_CLKOUTFLEX2 8
R1877 4.7K 1 2 PCH_SPKR 16 NO STUFF 5%
AK14 (IPD-PWROK)
5% 1/20W MF 201 1/20W 93 23 ITPXDP_CLK100M_N CLKOUT_ITPXDP_N
R1878 10K 1 2 PCH_SATALED_L 16
R1841 MF
AK13 K49
5% 1/20W MF 201 201 93 23 ITPXDP_CLK100M_P CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 TP_PCH_GPIO67_CLKOUTFLEX3 8
0 (IPD-PWROK)
R1834 10K 1 2 DP_AUXCH_ISOL 23 87 93 10 ITPCPU_CLK100M_P 1 2
5% 1/20W MF 201
R1833 10K 1 2 SATARDRVR_EN 23 41 5%
1/20W
5% 1/20W MF 201
MF R1872
R1842 10K 1 2 FW_CLKREQ_L 16 39 201 604
5% 1/20W MF 201 24 IN SYSCLK_CLK25M_SB 1 2 SYSCLK_CLK25M_SB_R 16
R1869 10K 1 2 AP_CLKREQ_L 16 32
R1844 10K 1 2
5% 1/20W MF 201
EXCARD_CLKREQ_L
1%
1/16W
1.8V -> 1.1V
16
1
R1845 10K 1 2
5% 1/20W MF 201
JTAG_DPMUXUC_TRST_L 16 Unused clock terminations for FCIM Mode
MF-LF
402 R1873
5% 1/20W MF 201 1K
R1847 10K 1 2 ENET_CLKREQ_L 16 36 1%
5% 1/20W MF 201 96 16 PCH_CLK96M_DOT_P R1891 10K 1 2 1/20W
R1814 10K
A R1815 10K
2
1
1
2
5%
5%
1/20W
1/20W
MF
MF
201
201
PEG_CLKREQ_L
TBT_CLKREQ_L
8 16
16 35
96 16 PCH_CLK96M_DOT_N R1892 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
MF
2 201 SYNC_MASTER=J31_ANNE SYNC_DATE=06/02/2011 A
96 16 PCH_CLK100M_SATA_P R1893 10K 1 2 PAGE TITLE
R1843 10K PCIECLKRQ0_L_GPIO73
R1846 10K
1
1
2
2
5% 1/20W MF 201
PEGCLKRQA_L_GPIO47
16
16
96 16 PCH_CLK100M_SATA_N R1894 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
PCH SATA/PCIe/CLK/LPC/SPI
5% 1/20W MF 201 DRAWING NUMBER SIZE
R1848 10K 1 2 GPU:1P PEGCLKRQB_L_GPIO56 PCIE_CLK100M_PCH_P R1895 10K 1 2
R1853 10K 1 2
5% 1/20W MF 201
PCH_GPIO11
16
16
GPU:2P
96 16
96 16 PCIE_CLK100M_PCH_N R1896 10K 1 2

5% 1/20W MF 201
5% 1/20W MF 201 R1880 10K 1 2 PEGCLKRQB_L_GPIO56 16 5% 1/20W MF 201 REVISION
R1854 10K 1 2 USB_EXTB_SEL_XHCI
R1855 10K 1 2
5% 1/20W MF 201
USB_EXTD_SEL_XHCI
16 25
16
5% 1/20W MF 201
96 16 PCH_CLK14P3M_REFCLK R1897 10K 1 2
5% 1/20W MF 201
R
3.0.0
5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1879 10K 1 2 ENET_MEDIA_SENSE_RDIV 16 24 16 PCH_CLKIN_GNDP1 R1870 10K 1 2 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
16 PCH_CLKIN_GNDN1 R1871 10K 1 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
18 OF 132
If HDA = S0, must also ensure that signal cannot be high in S3.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_SUS_PCH_GPIO 7 16 17 18 19
=PP1V05_S0_PCH_VCCIO_PCIE 7
R1905 1
1
R1900
10K 49.9
5% 1%
1/20W 1/20W
MF MF
201 2 2 201 OMIT_TABLE OMIT_TABLE
93 9 IN DMI_N2S_N<0> BC24
DMI0RXN U1800 FDI_RXN0 BJ14 FDI_DATA_N<0> IN 9 93 17 8 OUT LVDS_IG_BKL_ON J47
L_BKLTEN U1800 SDVO_TVCLKINN AP43 TP_SDVO_TVCLKINN 6
BE20 PANTHERPOINT AY14 M45 (IPD)
PANTHERPOINT SDVO_TVCLKINP AP45
93 9 6 IN DMI_N2S_N<1> DMI1RXN MOBILE FDI_RXN1 FDI_DATA_N<1> IN 6 9 93 17 8 OUT LVDS_IG_PANEL_PWR L_VDD_EN TP_SDVO_TVCLKINP 6
(IPD)
D 93 9 6
93 9 6
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
BG18
BG20
DMI2RXN
DMI3RXN
FCBGA
(3 OF 10)
FDI_RXN2
FDI_RXN3
BE14
BH13
FDI_DATA_N<2>
FDI_DATA_N<3>
IN
IN
9 93
9 93
8 OUT LVDS_IG_BKL_PWM P45
L_BKLTCTL
MOBILE
FCBGA
(4 OF 10)
SDVO_STALLN
(IPD)
AM42
AM40
TP_SDVO_STALLN 6 D
BC12 T40 SDVO_STALLP TP_SDVO_STALLP 6
BE24 FDI_RXN4 FDI_DATA_N<4> IN 6 9 93 86 OUT LVDS_IG_DDC_CLK L_DDC_CLK (IPD)
93 9 IN DMI_N2S_P<0> DMI0RXP BJ12 K47 AP39
BC20 FDI_RXN5 FDI_DATA_N<5> IN 6 9 93 86 OUT LVDS_IG_DDC_DATA L_DDC_DATA SDVO_INTN TP_SDVO_INTN 6
93 9 6 IN DMI_N2S_P<1> DMI1RXP BG10 (IPD-PLTRST#) (IPD) AP40
BJ18 FDI_RXN6 FDI_DATA_N<6> IN 6 9 93 T45 SDVO_INTP TP_SDVO_INTP 6
93 9 6 IN DMI_N2S_P<2> DMI2RXP BG9 6 TP_LVDS_IG_CTRL_CLK L_CTRL_CLK (IPD)
BJ20 FDI_RXN7 FDI_DATA_N<7> IN 6 9 93 P39
93 9 6 IN DMI_N2S_P<3> DMI3RXP 6 TP_LVDS_IG_CTRL_DATA L_CTRL_DATA P38
BG14 SDVO_CTRLCLK DPA_IG_DDC_CLK 8
FDI_RXP0 FDI_DATA_P<0> IN 9 93
AF37 M39
AW24 BB14
PCH_LVDS_IBG LVD_IBG SDVO_CTRLDATA DPA_IG_DDC_DATA 8
93 9 6 OUT DMI_S2N_N<0> DMI0TXN FDI_RXP1 FDI_DATA_P<1> IN 6 9 93 PLACE_NEAR=U1800.AF37:2.54mm AF36 (IPD-PLTRST#)
AW20 BF14 6 TP_PCH_LVDS_VBG LVD_VBG AT49
93 9 6 OUT DMI_S2N_N<1> DMI1TXN FDI_RXP2 FDI_DATA_P<2> IN 9 93 R1950 1 DDPB_AUXN DPA_IG_AUX_CH_N 8
DMI_S2N_N<2> BB18 BG13 FDI_DATA_P<3> AE48 AT47 DPA_IG_AUX_CH_P

93 9 OUT DMI2TXN FDI_RXP3 IN 9 93 2.37K LVD_VREFH DDPB_AUXP 8
AV18 BE12 1% AE47 AT40
93 9 6 OUT DMI_S2N_N<3> DMI3TXN FDI_RXP4 FDI_DATA_P<4> IN 6 9 93 1/20W LVD_VREFL DDPB_HPD DPA_IG_HPD 8
MF
DMI
FDI
BG12
DIGITAL DISPLAY INTERFACE

AY24 FDI_RXP5 FDI_DATA_P<5> IN 6 9 93 201 AV42
93 9 6 OUT DMI_S2N_P<0> DMI0TXP BJ10
2
AK39 DDPB_0N TP_DP_IG_B_MLN<0> 8
AY20 FDI_RXP6 FDI_DATA_P<6> IN 6 9 93 95 89 OUT LVDS_IG_A_CLK_N LVDSA_CLK* AV40
93 9 6 OUT DMI_S2N_P<1> DMI1TXP BH9 AK40 DDPB_0P TP_DP_IG_B_MLP<0> 8
AY18 FDI_RXP7 FDI_DATA_P<7> IN 6 9 93 95 89 OUT LVDS_IG_A_CLK_P LVDSA_CLK AV45
93 9 OUT DMI_S2N_P<2> DMI2TXP DDPB_1N TP_DP_IG_B_MLN<1> 8
LVDS
DMI_S2N_P<3> AU18 LVDS_IG_A_DATA_N<0> AN48 AV46 TP_DP_IG_B_MLP<1>
93 9 6 OUT DMI3TXP AW16 95 89 OUT LVDSA_DATA0* DDPB_1P 8
FDI_INT FDI_INT OUT 6 9 93
AM47 AU48
95 89 OUT LVDS_IG_A_DATA_N<1> LVDSA_DATA1* DDPB_2N TP_DP_IG_B_MLN<2> 8
AV12
=PPVRTC_G3_PCH 7 16 20 AK47 AU47
BJ24 FDI_FSYNC0 FDI_FSYNC<0> OUT 6 9 93 95 89 OUT LVDS_IG_A_DATA_N<2> LVDSA_DATA2* DDPB_2P TP_DP_IG_B_MLP<2> 8
PCH_DMI_COMP DMI_ZCOMP BC10 AJ48 AV47
BG25 FDI_FSYNC1 FDI_FSYNC<1> OUT 6 9 93
1
95 8 OUT LVDS_IG_A_DATA_N<3> LVDSA_DATA3* DDPB_3N TP_DP_IG_B_MLN<3> 8
DMI_IRCOMP R1915 AV49
AV14 AN47 DDPB_3P TP_DP_IG_B_MLP<3> 8
FDI_LSYNC0 FDI_LSYNC<0> OUT 6 9 93 390K 95 89 OUT LVDS_IG_A_DATA_P<0> LVDSA_DATA0
BH21 BB10 5% AM49
PCH_DMI2RBIAS DMI2RBIAS FDI_LSYNC1 FDI_LSYNC<1> OUT 6 9 93 1/20W 95 89 OUT LVDS_IG_A_DATA_P<1> LVDSA_DATA1 P46
MF AK49 DDPC_CTRLCLK DPB_IG_DDC_CLK 8
PLACE_NEAR=U1800.BH21:2.54mm 201 95 89 OUT LVDS_IG_A_DATA_P<2> LVDSA_DATA2 P42
2
AJ47 DDPC_CTRLDATA DPB_IG_DDC_DATA 8
1
R1920 A18 95 8 OUT LVDS_IG_A_DATA_P<3> LVDSA_DATA3 (IPD-PLTRST#)
DSWVRMEN PCH_DSWVRMEN AP47
750 DDPC_AUXN DPB_IG_AUX_CH_N
SYSTEM POWER
8
1% C12 E22 AF40 AP49
PCH_SUSACK_L PM_DSW_PWRGD LVDS_IG_B_CLK_N DPB_IG_AUX_CH_P
MANAGEMENT
1/20W 17 SUSACK* (IPU) DPWROK IN 45 8 OUT LVDSB_CLK* DDPC_AUXP 8
MF AF39 AT38
2 201 K3 B9 8 OUT LVDS_IG_B_CLK_P LVDSB_CLK DDPC_HPD DPB_IG_HPD 8
45 24 6 PM_SYSRST_L SYS_RESET* WAKE* PCIE_WAKE_L 6 17 24 32
C
IN IN
C
1
R1909 95 89 LVDS_IG_B_DATA_N<0> AH45
LVDSB_DATA0* DDPC_0N AY47 TP_DP_IG_C_MLN<0> 6
PM_PCH_SYS_PWROK P12 N3 PM_CLKRUN_L 100K OUT
92 45 23 IN SYS_PWROK CLKRUN*/GPIO32 BI 6 17 45 47 AH47 AY49
5% 95 89 OUT LVDS_IG_B_DATA_N<1> LVDSB_DATA1* DDPC_0P TP_DP_IG_C_MLP<0> 6
L22 G8 1/20W AF49 AY43
92 24 IN PM_PCH_PWROK PWROK SUS_STAT*/GPIO61 LPC_PWRDWN_L OUT 6 45 47 MF 95 89 OUT LVDS_IG_B_DATA_N<2> LVDSB_DATA2* DDPC_1N TP_DP_IG_C_MLN<1> 6
201 AF45 AY45
2 LVDS_IG_B_DATA_N<3> TP_DP_IG_C_MLP<1>
L10 N14 8 OUT LVDSB_DATA3* DDPC_1P 6
92 IN PM_PCH_APWROK APWROK SUSCLK/GPIO62 PM_CLK32K_SUSCLK_R OUT 46 BA47
AH43 DDPC_2N TP_DP_IG_C_MLN<2> 6
B13 D10 95 89 OUT LVDS_IG_B_DATA_P<0> LVDSB_DATA0 BA48
93 26 10 OUT PM_MEM_PWRGD DRAMPWROK SLP_S5*/GPIO63 PM_SLP_S5_L OUT 17 45 74 AH49 DDPC_2P TP_DP_IG_C_MLP<2> 6
95 89 OUT LVDS_IG_B_DATA_P<1> LVDSB_DATA1 BB47
C21 H4 AF47 DDPC_3N TP_DP_IG_C_MLN<3> 6
74 IN PM_RSMRST_L RSMRST* SLP_S4* PM_SLP_S4_L OUT 17 26 32 45 74 95 89 OUT LVDS_IG_B_DATA_P<2> LVDSB_DATA2 BB49
AF43 DDPC_3P TP_DP_IG_C_MLP<3> 6
K16 F4 8 OUT LVDS_IG_B_DATA_P<3> LVDSB_DATA3
17 PCH_SUSWARN_L SUSWARN*/SUSPWRDNACK/GPIO30 SLP_S3* PM_SLP_S3_L OUT 6 17 26 45 74
M43 TP_DP_IG_D_CTRL_CLK
E20 G10 DDPD_CTRLCLK 6
45 23 17 IN PM_PWRBTN_L PWRBTN* (IPU) SLP_A* TP_PM_SLP_A_L M36
DDPD_CTRLDATA TP_DP_IG_D_CTRL_DATA 6
G16 N48 (IPD-PLTRST#)
74 46 45 IN SMC_ADAPTER_EN H20 ACPRESENT/GPIO31 SLP_SUS* PM_SLP_SUS_L OUT 17 74 6 TP_CRT_IG_BLUE CRT_BLUE AT45
(IPD-DeepS4/S5) P49 DDPD_AUXN TP_DP_IG_D_AUXN 6
E10 AP14 6 TP_CRT_IG_GREEN CRT_GREEN AT43
46 IN PM_BATLOW_L BATLOW*/GPIO72 (IPU) PMSYNCH PM_SYNC OUT 10 93 T49 DDPD_AUXP TP_DP_IG_D_AUXP 6
6 TP_CRT_IG_RED CRT_RED BH41
A10 K14 DDPD_HPD TP_DP_IG_D_HPD 6
PCH_RI_L RI* SLP_LAN*/GPIO29 MEM_VDD_SEL_1V5_L OUT 17
CRT
TP_CRT_IG_DDC_CLK T39 BB43 TP_DP_IG_D_MLN<0>
6 CRT_DDC_CLK DDPD_0N 6
TP_CRT_IG_DDC_DATA M40 BB45 TP_DP_IG_D_MLP<0>

6 CRT_DDC_DATA DDPD_0P 6
BF44 TP_DP_IG_D_MLN<1>
DDPD_1N 6
TP_CRT_IG_HSYNC M47 BE44 TP_DP_IG_D_MLP<1>

6 CRT_HSYNC DDPD_1P 6
19 18 17 16 7 =PP3V3_SUS_PCH_GPIO M49 BF42
6 TP_CRT_IG_VSYNC CRT_VSYNC DDPD_2N TP_DP_IG_D_MLN<2> 6
BE42 TP_DP_IG_D_MLP<2>
DDPD_2P 6
R1983 1 PCH_DAC_IREF T43
DAC_IREF DDPD_3N BJ42 TP_DP_IG_D_MLN<3> 6
10K T42 BG42
5% PLACE_NEAR=U1800.T43:2.54mm CRT_IRTN DDPD_3P TP_DP_IG_D_MLP<3> 6
1/20W
1
MF R1951
201
2 R1986 1K
0 5%
17 PCH_SUSWARN_L 2 1 PCH_SUSACK_L 17 1/20W
B 5%
1/20W
MF
MF
2 201 B
201
=PP3V3_SUS_PCH_GPIO 7 16 17 18 19
=PP3V3_S0_PCH_GPIO 7 16 18 19 30
=PP3V3_S5_PCH 7
R1985 1K 1 2 PM_PWRBTN_L 17 23 45
5% 1/20W MF 201
R1991 8.2K 1 2 PM_CLKRUN_L 6 17 45 47
5% 1/20W MF 201
R1982 10K
A R1925 1K
1
1
2
2
5% 1/20W MF 201
MEM_VDD_SEL_1V5_L
PCIE_WAKE_L
17
6 17 24 32
5% 1/20W MF 201 MAKE_BASE=TRUE
PAGE TITLE
=TBT_WAKE_L IN 87
PCH DMI/FDI/PM/Graphics
DRAWING NUMBER SIZE
R1924 100K 2 1 PM_SLP_S3_L
R1921 100K 2 1
5% 1/20W MF 201
PM_SLP_S4_L
6 17 26 45 74
17 26 32 45 74 Apple Inc. 051-9585 D

5% 1/20W MF 201 REVISION
R1922 100K 2 1 PM_SLP_S5_L
R1923 100K 2 1
5% 1/20W MF 201
PM_SLP_SUS_L
17 45 74
17 74
R
3.0.0
5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1981 100K 2 1 LVDS_IG_BKL_ON 8 17 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
R1984 100K 2 1 LVDS_IG_PANEL_PWR 8 17 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
19 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
BG26
TP1 U1800 RSVD1 AY7
NC PANTHERPOINT NC
BJ26 AV7
NC TP2 MOBILE RSVD2 NC
BH25 AU3
NC TP3 FCBGA RSVD3 NC
BJ16
TP4 (5 OF 10) RSVD4 BG4
NC NC
BG16
NC TP5 AT10
AH38 RSVD5 NC
NC TP6 BC8
AH37 RSVD6 NC
NC TP7
AK43 AU2
NC TP8 RSVD7 NC
AK45 AT4
NC TP9 RSVD8 NC
C18 AT3
TP10 RSVD9
D
NC
NC
N30
H3
TP11 RSVD10 AT1
AY3
NC
NC D
NC TP12 RSVD11 NC
AH12 AT5
NC TP13 RSVD12 NC
AM4 AV3
NC TP14 RSVD13 NC
AM5 AV1
NC TP15 RSVD14 NC
Y13 BB1
NC TP16 RSVD15 NC
K24 BA3
NC TP17 RSVD16 NC
L24 BB5
NC TP18 RSVD17 NC
AB46 BB3
NC TP19 RSVD18 NC
AB45 BB7
NC TP20 RSVD19 NC
BE8
B21 RSVD20 NC
NC TP21 BD4
M20 RSVD21 NC
NC TP22 BF6
AY16 RSVD22 NC
TP_PCH_TP23 TP23
BG46 AV5
NC TP24 RSVD23 NC
AV10
RSVD24 NC
AT8
RSVD25 NC
AY5
RSVD26 NC
BA2
RSVD27 NC
AT12
RSVD28 NC
BF3
RSVD29 NC
USB3_EXTA_RX_N BE28 C24 USB_EXTA_N
95 42 6 IN USB3RN1 USBP0N BI 42 95
USB3_EXTB_RX_N BC30 A24 USB_EXTA_P

Ext A (XHCI/EHCI)
95 43 6 IN USB3RN2 USBP0P BI 42 95
USB3_EXTC_RX_N BE32
8 IN USB3RN3 C25
USBP1N USB_EXTB_XHCI_N 25 95
C
BI
C Ext B (XHCI)
USB3_EXTD_RX_N BJ32
8 IN USB3RN4 B25
USBP1P USB_EXTB_XHCI_P BI 25 95
USB3_EXTA_RX_P BC28
95 42 6 IN USB3RP1 C26
USBP2N USB_EXTC_N BI 8 95
95 43 6 IN USB3_EXTB_RX_P BE30
USB3RP2 A26 USB_EXTC_P
Ext C (XHCI/EHCI)
BF32 USBP2P BI 8 95
8 IN USB3_EXTC_RX_P USB3RP3
USB3_EXTD_RX_P BG32 K28 USB_EXTD_XHCI_N
8 IN USB3RP4 USBP3N BI 25 95
H28 USB_EXTD_XHCI_P
Ext D (XHCI) (Mobiles: Trackpad?)
USB
USBP3P BI 25 95
USB3_EXTA_TX_N AV26
95 42 6 OUT USB3TN1 E28
USBP4N TP_USB_4N
95 43 6 OUT USB3_EXTB_TX_N BB26
USB3TN2 D28 TP_USB_4P
Unused
AU28 USBP4P
8 OUT USB3_EXTC_TX_N USB3TN3
USB3_EXTD_TX_N AY30 C28 TP_USB_SDN
8 OUT USB3TN4 USBP5N
A28 TP_USB_SDP
RSVD: SD
AU26 USBP5P
95 42 6 OUT USB3_EXTA_TX_P USB3TP1
USB3_EXTB_TX_P AY26 C29 TP_USB_WLANN
95 43 6 OUT USB3TP2 USBP6N
USB3_EXTC_TX_P AV28 B29 TP_USB_WLANP
RSVD: WiFi
8 OUT USB3TP3 USBP6P
USB3_EXTD_TX_P AW30
8 OUT USB3TP4 N28
USBP7N USB_HUB_UP_N BI 25 95
M28 USB_HUB_UP_P
USB Hub (All LS/FS Devices)
USBP7P BI 25 95
=PP3V3_S0_PCH_GPIO L30 USB_CAMERA_N

30 19 18 17 16 7 USBP8N BI 32 95
R2010 10K 1 2 PCI_INTA_L K40 K30 USB_CAMERA_P

Camera
PIRQA* USBP8P BI 32 95
PCI
5% 1/20W MF 201
R2011 10K 1 2 PCI_INTB_L K38
PIRQB* G30
5% 1/20W MF 201 USBP9N USB_EXTB_EHCI_N BI 25 95
R2012 10K 1 2 PCI_INTC_L H38
PIRQC* E30 Ext B (EHCI)
5% 1/20W MF 201 USBP9P USB_EXTB_EHCI_P BI 25 95
R2013 10K 1 2 PCI_INTD_L G38
PIRQD*
5% 1/20W MF 201 C30
USBP10N USB_EXTD_EHCI_N BI 8
JTAG_GMUX_TMS C46 A30 USB_EXTD_EHCI_P

Ext D (EHCI)
89 18 OUT REQ1*/GPIO50 USBP10P BI 8
BLC_I2C_MUX_SEL C44
18 OUT REQ2*/GPIO52 L32
USBP11N TP_USB_BT_HSN
18 OUT USE_HDD_OOB_L E40
REQ3*/GPIO54 K32 TP_USB_BT_HSP
RSVD: BT (HS)
USBP11P
B TP_PCH_STRP_BBS1 D47
E42
GNT1*/GPIO51 USBP12N G32
E32
TP_USB_12N
Unused
B
NO STUFF TP_PCH_STRP_ESI_L GNT2*/GPIO53 USBP12P TP_USB_12P
R2054 10K 2 1 PCH_STRP_TOPBLK_SWP_L F46
GNT3*/GPIO55 C32
5% 1/20W MF 201 USBP13N TP_USB_13N
(IPU-PCIERST#) A32 TP_USB_13P
Unused
G42 USBP13P
18 IN BLC_GPIO PIRQE*/GPIO2 (IPD)
AUD_IP_PERIPHERAL_DET G40
63 18 IN PIRQF*/GPIO3 C33
C42 USBRBIAS* 95 PCH_USB_RBIAS
87 18 IN TBT_PWR_REQ_L PIRQG*/GPIO4 B33
D44 USBRBIAS PLACE_NEAR=U1800.B33:2.54mm
63 18 IN AUD_I2C_INT_L PIRQH*/GPIO5 1
R2070
TP_PCI_PME_L K10 A14 XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L 22.6
6 PME* (IPU) OC0*/GPIO59 IN 18 23
K20 1%
C6 OC1*/GPIO40 XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L IN 18 23 1/20W
26 24 OUT PLT_RESET_L PLTRST* B17 MF
OC2*/GPIO41 XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L IN 18 23
2 201
LPC_CLK33M_SMC_R H49 C16 XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
96 24 OUT CLKOUT_PCI0 OC3*/GPIO42 IN 18 23
LPC_CLK33M_LPCPLUS_R H43 L16 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

24 OUT CLKOUT_PCI1 OC4*/GPIO43 IN 23
=PP3V3_SUS_PCH_GPIO TP_PCI_CLK33M_OUT2 J48 A16 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

7 16 17 19 24 CLKOUT_PCI2 OC5*/GPIO9 IN 23
=PP3V3_S3_PCH_GPIO TP_PCI_CLK33M_OUT3 K42 D14 XDP_DB2_PCH_GPIO10_AP_PWR_EN

7 24 6 CLKOUT_PCI3 OC6*/GPIO10 OUT 23
=PP3V3_S0_PCH_GPIO PCH_CLK33M_PCIOUT H40 C14 XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

7 16 17 18 19 30 24 OUT CLKOUT_PCI4 OC7*/GPIO14 IN 18 23
(IPD)
R2016 10K 1 2 JTAG_GMUX_TMS 18 89

5% 1/20W MF 201
R2017 10K 1 2 BLC_I2C_MUX_SEL 18
5% 1/20W MF 201
R2018 10K 1 2 USE_HDD_OOB_L 18
5% 1/20W MF 201
R2030 10K 1 2 BLC_GPIO 18
5% 1/20W MF 201
NO STUFF Redundant to pull-up on audio page

R2014 10K 1 2 AUD_IP_PERIPHERAL_DET 18 63
5% 1/20W MF 201
R2031 10K 1 2 TBT_PWR_REQ_L 18 87
A NO STUFF
5% 1/20W MF 201
Redundant to pull-up on audio page SYNC_MASTER=J31_ANNE SYNC_DATE=06/02/2011 A

R2033 10K 1 2 AUD_I2C_INT_L 18 63
PAGE TITLE
5% 1/20W MF 201
PCH PCI/USB/TP/RSVD
R2069 10K 1 2 XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE 18 23 DRAWING NUMBER SIZE
R2060 10K 1 2
5% 1/20W MF 201
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L 18 23 Apple Inc. 051-9585 D
5% 1/20W MF 201 REVISION
R2061 10K 1 2 XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
R2062 10K 1 2
5% 1/20W MF 201
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
18 23
18 23
R
3.0.0
R2068 10K 1 2
5% 1/20W MF 201
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
18 23
5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE
R2067 10K 2 1 AP_PWR_EN 23 32 74 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM
RAMCFG_SLOT RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.
30 19 18 17 16 7 =PP3V3_S0_PCH_GPIO
RAMCFG3:H RAMCFG2:H RAMCFG1:H RAMCFG0:H

R2172 1
1
R2174 1
1
R2173 R2175
10K 10K 10K 10K
D 5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
D
OMIT_TABLE 201
2 2
201 201
2 2
201
23 19 XDP_FC1_PCH_GPIO0 T7
BMBUSY*/GPIO0 U1800 TACH4/GPIO68 C40 MLB_RAMCFG3
PANTHERPOINT
FW_PME_L A42 MOBILE B41 MLB_RAMCFG2
39 19 8 IN TACH1/GPIO1 TACH5/GPIO69
FCBGA
DPMUX_UC_IRQ H36 C41 MLB_RAMCFG1
19 8 IN TACH2/GPIO6 (6 OF 10) TACH6/GPIO70
SMC_RUNTIME_SCI_L E38 A40 MLB_RAMCFG0

45 19 IN TACH3/GPIO7 TACH7/GPIO71
TP_PCH_GPIO8 C10
GPIO8 (IPU-RSMRST#)
WOL_EN C4
74 19 OUT LAN_PHY_PWR_CTRL/GPIO12
P4 PCH_A20GATE
G2 A20GATE 19
68 23 IN XDP_FC0_PCH_GPIO15 GPIO15 (IPU)
NO STUFF
23 OUT XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH U2
SATA4GP/GPIO16 (IPD) PECI AU16 PCH_PECI R2170 43 1 2 CPU_PECI BI 10 46 93
5% 1/20W
D40 MF 201
47 19 6 BI LPCPLUS_GPIO TACH0/GPIO17 P5
RCIN* PCH_RCIN_L 19
ODD_PWR_EN_L T5
41 19 OUT SCLOCK/GPIO22
=PP1V8_S0_PCH_VCC_DFTERM 7 20 22
E8 PROCPWRGD AY11 PCH_PROCPWRGD R2140 0 1 2 CPU_PWRGD OUT 10 23 93
CPU/MISC
19 PCH_GPIO24 GPIO24 5% 1/20W
(PU necessary?) MF 201
1
46 19 SMC_SCI_L E16
GPIO27 (IPU-DeepS4/S5) THRMTRIP* AY10 46 PM_THRMTRIP_L_R R2156 390 1 2 PM_THRMTRIP_L 10 46 93
R2179
IN IN
5% 1/20W 2.2K
P8 MF 201 5%
23 OUT XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L GPIO28 (IPU-RSMRST#) T14 1/20W
INIT3_3V* PCH_INIT3V3_L
GPIO
MF
(IPU) R2178 201
35 OUT TBT_SW_RESET_L R2180 0 1 2 19 TBT_SW_RESET_R_L K1
STP_PCI*/GPIO34 2
5% 1/20W AY1 1K
MF 201 K4 DF_TVS PCH_DF_TVS 2 1 CPU_PROC_SEL_L 10 93
23 OUT XDP_DC1_PCH_GPIO35_MXM_GOOD GPIO35 (IPD-PLTRST#?)
NO STUFF 5% DF_TVS:DMI & FDI Term Voltage
1/20W
V8 AH8
23 19 OUT XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL SATA2GP/GPIO36
(IPD-PLTRST#)
TS_VSS1 R2130 1 MF
201
Set to Vss when Low
C 23 OUT XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK M5
SATA3GP/GPIO37
(IPD-PLTRST#)
TS_VSS2
TS_VSS3
AK11
AH10
1K
5%
1/20W
MF
This has internal pull up and should not pulled low.
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
Set to Vcc when High
C
JTAG_ISP_TDO N2 AK10
89 19 8 IN SLOAD/GPIO38 TS_VSS4 201
2
JTAG_ISP_TDI M3
89 8 OUT SDATAOUT0/GPIO39 P37
NC_1 NC
FW_PWR_EN_PCH V13
24 19 OUT SDATAOUT1/GPIO48
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH V3 BG2
23 OUT SATA5GP/GPIO49/TEMP_ALERT* VSS_NCTF_14
BG48
D6 VSS_NCTF_15
56 47 19 6 BI SPIROM_USE_MLB GPIO57 BH3
VSS_NCTF_16
BH47
VSS_NCTF_17
A4 BJ4
VSS_NCTF_0 VSS_NCTF_18
A44 BJ44
A45 BJ45
A46 BJ46
A5 BJ5
NCTF
A6 BJ6
B3 C2
B47 C48
BD1 D1
BD49 D49
BE1 E1
BE49 E49
BF1 F1
BF49 F49
B B
=PP3V3_S5_PCH_GPIO 7
=PP3V3_SUS_PCH_GPIO 7 16 17 18
=PP3V3_S0_PCH_GPIO 7 16 17 18 19 30
=PP3V3_T29_PCH_GPIO 7 16
R2186 10K 1 2 JTAG_ISP_TDO 8 19 89

5% 1/20W MF 201
R2199 10K 1 2 JTAG_TBT_TDI 8 33
5% 1/20W MF 201 NO STUFF
R2160 10K 1 2 XDP_FC1_PCH_GPIO0 19 23 R2181 10K 2 1 SPIROM_USE_MLB 6 19 47 56
5% 1/20W MF 201 5% 1/20W MF 201
R2185 10K 1 2 FW_PME_L 8 19 39
5% 1/20W MF 201
R2196 10K 1 2 SMC_RUNTIME_SCI_L 19 45
5% 1/20W MF 201
R2190 100K 1 2 LPCPLUS_GPIO 6 19 47
5% 1/20W MF 201
NO STUFF Must stuff R2197 when R2180 NO STUFFed.

R2197 10K 1 2 TBT_SW_RESET_R_L 19
5% 1/20W MF 201
R2184 10K 1 2 FW_PWR_EN_PCH 19 24
5% 1/20W MF 201
R2150 10K 1 2 PCH_A20GATE 19
5% 1/20W MF 201
R2155 10K 1 2 PCH_RCIN_L 19
5% 1/20W MF 201
R2194 10K
A R2192 10K
1
1
2
2
5%
5%
1/20W
1/20W
MF
MF
201
201
WOL_EN
PCH_GPIO24
19 74
19 SYNC_MASTER=J31_ANNE SYNC_DATE=06/02/2011 A
R2193 100K 1 2 SPIROM_USE_MLB 6 19 47 56
PAGE TITLE
R2191 10K 1 2
5% 1/20W MF 201
SMC_SCI_L 19 46
PCH GPIO/MISC/NCTF
5% 1/20W MF 201 DRAWING NUMBER SIZE
R2111 20K 2 1
5% 1/20W MF 201
DPMUX_UC_IRQ 8 19
R2195 100K 2 1 AUD_IPHS_SWITCH_EN_PCH 23 24 REVISION
R2112 10K 2 1
5%
5%
1/20W
1/20W
MF
MF
201
201
ODD_PWR_EN_L 19 41
R
3.0.0
R2198 10K 2 1 XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL 19 23 NOTICE OF PROPRIETARY PROPERTY: BRANCH
5% 1/20W MF 201
R2113 10K 2 1 JTAG_ISP_TCK 8 23 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
R2116 10K 2 1 ENET_LOW_PWR_PCH 23 24 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
21 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OMIT_TABLE OMIT_TABLE
22 7 =PP1V05_S0_PCH_VCC_CORE
VCCACLK pin left as NC per DG AD49
VCCACLK U1800 VCCIO_29_USB N26 =PP1V05_S0_PCH_VCCIO_USB 1.44 A Max, 474mA Idle AA23
VCCCORE U1800
NC 7 22
PANTHERPOINT VCCIO_30_USB P26 AC23
VCCCORE PANTHERPOINT
22 7 =PP3V3_S5_PCH_VCCDSW T16 VCCDSW3_3 MOBILE
P28 AD21
MOBILE
FCBGA
VCCIO_31_USB VCCCORE FCBGA
TP_PPVOUT_PCH_DCPSUSBYP V12 DCPSUSBYP (8 OF 10) VCCIO_32_USB T27 AD23 VCCCORE (7 OF 10)
T29 AF21 U48 PP3V3_S0_PCH_VCCA_DAC_F
VCCIO_33_USB VCCCORE VCCADAC 22
PP3V3_S0_PCH_VCC3_3_CLK_F T38
VCC3_3_5_CLK
CRT
22
AF23 VCCCORE
T23 =PP3V3_SUS_PCH_VCCSUS_USB
VCCSUS3_3_7_USB 7 22
VCCAPLLDMI2 pin left as NC per DG BH23 AG21 U47
VCC CORE
NC VCCAPLLDMI2 T24
VCCCORE VSSADAC
VCCSUS3_3_8_USB AG23
VCCCORE
22 20 7 =PP1V05_S0_PCH_VCCIO_CLK AL29
VCCIO_14_PLLCLK VCCSUS3_3_9_USB V23
AG24
V24 VCCCORE
VCCSUS3_3_10_USB
AL24 left as NC per DG NC
AL24
DCPSUS_3_CLK P24
AG26
VCCCORE AK36 =PP3V3_S0_PCH_VCCA_LVDS
VCCSUS3_3_6_USB AG27
VCCALVDS 7
VCCCORE
22 20 7 =PP1V05_S0_PCH_VCCASW AA19 VCCASW_1_CLK
AA21 VCCIO_34_PLLUSB T26 =PP1V05_S0_PCH_VCCIO_PLLUSB 7
AG29
VCCCORE VSSALVDS AK37
VCCASW_2_CLK AJ23
VCCCORE
AA24
VCCASW_3_CLK V5REF_SUS M26 =PP5V_SUS_PCH_V5REFSUS 22
USB
AJ26 VCCCORE
AA26 VCCASW_4_CLK
LVDS
AA27 DCPSUS_4_USB AN23
NC NC-ed per DG AJ27
VCCCORE
PP1V8_S0_PCH_VCCTX_LVDS_F
VCCASW_5_CLK AJ29 22
VCCCORE
AA29
VCCASW_6_CLK VCCSUS3_3_1_USB AN24 =PP3V3_SUS_PCH_VCCSUS 7 22 VCCTX_LVDS AM37
AJ31 VCCCORE
AA31 AM38
VCCASW_7_CLK VCCTX_LVDS
C
AC26
AC27
VCCASW_8_CLK
VCCASW_9_CLK
V5REF P34 =PP5V_S0_PCH_V5REF 22
7 =PP1V05_S0_PCH_VCCIO_PLLPCIE AN19
VCCIO_28_PLLPCIE
VCCTX_LVDS
VCCTX_LVDS
AP36
AP37 C
AC29 VCCASW_10_CLK VCCSUS3_3_2_GPIO N20 =PP3V3_SUS_PCH_VCCSUS_GPIO 7 22
TP_1V05_S0_PCH_VCCAPLLEXP BJ22
CLK/MISC
AC31 N22
6 VCCAPLLEXP
VCCASW_11_CLK VCCSUS3_3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS 7 22
AD29
VCCASW_12_CLK VCCSUS3_3_4_GPIO P20
22 7 =PP1V05_S0_PCH_VCCIO AN16
VCCIO_15_FDI V33
HVCMOS
AD31 P22 AN17 VCC3_3_6_HVCMOS
VCCASW_13_CLK VCCSUS3_3_5_GPIO VCCIO_16_FDI
PCI/GPIO/
W21
VCCASW_14_CLK
VCC3_3_1_GPIO AA16 =PP3V3_S0_PCH_VCC3_3_GPIO 7 22
AN21 VCCIO_17_PCIE VCC3_3_7_HVCMOS V34
W23 VCCASW_15_CLK
LPC
W16 AN26
VCC3_3_8_GPIO VCCIO_18_PCIE
VCCIO
W24
VCCASW_16_CLK T34 AN27
W26 VCC3_3_4_GPIO VCCIO_19_PCIE
VCCASW_17_CLK AP21
W29
VCCIO_20_PCIE
VCCASW_18_CLK AP23 VCCIO_21_PCIE VCCVRM_3_DMI AT16 =PP1V8R1V5_S0_PCH_VCCVRM 7 20
W31
VCCASW_19_CLK VCC3_3_2_SATA AJ2 =PP3V3_S0_PCH_VCC3_3_SATA 7 22
AP24
VCCIO_22_PCIE
PCH output, for decoupling only W33
VCCASW_20_CLK
DMI
VCCIO_5_PLLSATA AF13 =PP1V05_S0_PCH_VCCIO_SATA 7 16 20 22
AP26
VCCIO_23_PCIE VCCDMI_1_DMI AT20 =PP1V05_S0_PCH_VCC_DMI 7 22
PLACE_NEAR=U1800.N16:2.54mm
PPVOUT_G3_PCH_DCPRTC N16
DCPRTC AT24
VCCIO_24_PCIE
MIN_LINE_WIDTH=0.2 mm VCCIO_12_SATA3 AH13
AB36 PP1V05_S0_PCH_VCCCLKDMI_F
MIN_NECK_WIDTH=0.2 mm VCCCLKDMI 22
VOLTAGE=3.3V 20 7 =PP1V8R1V5_S0_PCH_VCCVRM Y49
VCCVRM_4_CLK VCCIO_13_SATA3 AH14 AN33
VCCIO_25_DP
C2210 1
AN34
0.1UF VCCIO_26_DP
20%
22 PP1V05_S0_PCH_VCCADPLLA_F BD47
VCCADPLLA VCCIO_6_PLLSATA3 AF14
10V PP1V05_S0_PCH_VCCADPLLB_F BF47 =PP3V3_S0_PCH_VCC3_3_PCI BH29
2 22 VCCADPLLB 22 7 VCC3_3_3_PCIE
NC VCCAPLLSATA pin left as NC per DG
CERM
SATA
AK1
402 VCCAPLLSATA
=PP1V8_S0_PCH_VCC_DFTERM 7 19 22
22 20 7 =PP1V05_S0_PCH_VCCIO_CLK AF17
VCCIO_7_CLK AF11 AG16
VCCVRM_1_SATA =PP1V8R1V5_S0_PCH_VCCVRM 7 20 VCCDFTERM
20 7 =PP1V8R1V5_S0_PCH_VCCVRM AP16
VCCVRM_2_FDI
22 16 7 =PP1V05_S0_PCH_VCCDIFFCLK AF33
VCCDIFFCLKN VCCDFTERM AG17
AC16
DFT/SPI
VCCIO_2_SATA =PP1V05_S0_PCH_VCCIO_SATA 7 16 20 22
55mA Max, 5mA Idle AF34
VCCDIFFCLKN VCCAFDIPLL pin left as NC per DG BG6
VCCAFDIPLL VCCDFTERM AJ16
FDI
VCCIO_3_SATA AC17 NC
AG34 AJ17
VCCDIFFCLKN VCCDFTERM
VCCIO_4_SATA AD17
7 =PP1V05_S0_PCH_VCCIO_PLLFDI AP17
VCCIO_27_PLLFDI
=PP1V05_S0_PCH_VCCSSC AG33
22 7 VCCSSC
7 =PP1V05_S0_PCH_VCCDMI_FDI AU20 VCCDMI_2_FDI VCCSPI V1 =PP3V3_SUS_PCH_VCC_SPI 7 22
PPVOUT_S0_PCH_DCPSST V16 T21 =PP1V05_S0_PCH_VCCASW

DCPSST VCCASW_22_MISC 7 20 22
MISC
B C2222 1
VOLTAGE=3.3V
NC-ed per DG NC
T17
V19
DCPSUS_1_CLK
VCCASW_23_MISC
VCCASW_21_MISC
V21
T19
B
0.1UF NC DCPSUS_2_CLK
20%
PLACE_NEAR=U1800.V16:2.54mm
10V
CPU
CERM 2
402 22 7 =PP1V05_S0_PCH_V_PROC_IO BJ8 V_PROC_IO
HDA
VCCSUSHDA P32 =PP3V3R1V5_S0_PCH_VCCSUSHDA 7 22 24
10 mA Max, 1mA Idle

RTC
=PPVRTC_G3_PCH A22
17 16 7 VCCRTC
C2231 1 1
C2232 1
C2233
1UF 0.1UF 0.1UF
10% 20% 20%
6.3V 10V 10V
CERM 2 2 CERM 2 CERM
402 402 402
PLACE_NEAR=U1800.A22:2.54mm PLACE_NEAR=U1800.A22:2.54mm
PLACE_NEAR=U1800.A22:2.54mm
A SYNC_MASTER=J5_MLB SYNC_DATE=03/21/2011 A
PAGE TITLE
PCH POWER
DRAWING NUMBER SIZE

REVISION
R
3.0.0
22 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
OMIT_TABLE
AY4
VSS U1800 VSS H46
H5
VSS U1800 VSS AK38
AY42 PANTHERPOINT K18
AA17 PANTHERPOINT AK4 VSS VSS
VSS VSS AY46 MOBILE K26
AA2 MOBILE AK42 VSS FCBGA VSS
VSS VSS AY8 K39
AA3 FCBGA AK46 VSS (10 OF 10) VSS
VSS VSS B11 VSS K46
AA33 (9 OF 10) AK8 VSS VSS
VSS VSS B15 K7
AA34 VSS AL16 VSS VSS
VSS VSS B19 L18
AB11 AL17 VSS VSS
VSS VSS B23 L2
AB14 AL19 VSS VSS
VSS VSS B27 L20
AB39 AL2 VSS VSS
VSS VSS B31 L26
AB4 AL21 VSS VSS
VSS VSS
D AB43
AB5
VSS VSS AL23
AL26
B35
B39
VSS
VSS
VSS
VSS
L28
L36
D
VSS VSS B7 L48
AB7 AL27 VSS VSS
VSS VSS F45 M12
AC19 AL31 VSS VSS
VSS VSS BB12 P16
AC2 AL33 VSS VSS
VSS VSS BB16 M18
AC21 AL34 VSS VSS
VSS VSS BB20 M22
AC24 AL48 VSS VSS
VSS VSS BB22 M24
AC33 AM11 VSS VSS
VSS VSS BB24 M30
AC34 AM14 VSS VSS
VSS VSS BB28 M32
AC48 AM36 VSS VSS
VSS VSS BB30 M34
AD10 AM39 VSS VSS
VSS VSS BB38 M38
AD11 AM43 VSS VSS
VSS VSS BB4 M4
AD12 AM45 VSS VSS
VSS VSS BB46 M42
AD13 AM46 VSS VSS
VSS VSS BC14 M46
AD19 AM7 VSS VSS
VSS VSS BC18 M8
AD24 AN2 VSS VSS
VSS VSS BC2 N18
AD26 AN29 VSS VSS
VSS VSS BC22 P30
AD27 AN3 VSS VSS
VSS VSS BC26 N47
AD33 AN31 VSS VSS
VSS VSS BC32 P11
AD34 AP12 VSS VSS
VSS VSS BC34 P18
AD36 AP19 VSS VSS
VSS VSS BC36 T33
AD37 AP28 VSS VSS
VSS VSS BC40 P40
AD38 AP30 VSS VSS
VSS VSS BC42 P43
AD39 AP32 VSS VSS
VSS VSS BC48 P47
AD4 AP38 VSS VSS
VSS VSS BD46 P7
AD40 AP4 VSS VSS
VSS VSS BD5 R2
VSS VSS
C
AD42
AD43
VSS
VSS
VSS
VSS
AP42
AP46
BE22
BE26
VSS
VSS
VSS
VSS
R48
T12
C
AD45 AP8
VSS VSS BE40 T31
AD46 AR2 VSS VSS
VSS VSS BF10 T37
AD8 AR48 VSS VSS
VSS VSS BF12 T4
AE2 AT11 VSS VSS
VSS VSS BF16 W34
AE3 AT13 VSS VSS
VSS VSS BF20 T46
AF10 AT18 VSS VSS
VSS VSS BF22 T47
AF12 AT22 VSS VSS
VSS VSS BF24 T8
AD14 AT26 VSS VSS
VSS VSS BF26 V11
AD16 AT28 VSS VSS
VSS VSS BF28 V17
AF16 AT30 VSS VSS
VSS VSS BD3 V26
AF19 AT32 VSS VSS
VSS VSS BF30 V27
AF24 AT34 VSS VSS
VSS VSS BF38 V29
AF26 AT39 VSS VSS
VSS VSS BF40 V31
AF27 AT42 VSS VSS
VSS VSS BF8 V36
AF29 AT46 VSS VSS
VSS VSS BG17 V39
AF31 AT7 VSS VSS
VSS VSS BG21 V43
AF38 AU24 VSS VSS
VSS VSS BG33 V7
AF4 AU30 VSS VSS
VSS VSS BG44 W17
AF42 AV11 VSS VSS
VSS VSS BG8 W19
AF46 AV16 VSS VSS
VSS VSS BH11 W2
AF5 AV20 VSS VSS
VSS VSS BH15 W27
AF7 AV24 VSS VSS
VSS VSS BH17 W48
AF8 AV30 VSS VSS
VSS VSS BH19 Y12
AG19 AV38 VSS VSS
VSS VSS H10 Y38
AG2 AV4 VSS VSS
VSS VSS
B AG31
AG48
VSS VSS AV43
AV8
BH27
BH31
VSS
VSS
VSS
VSS
Y4
Y42
B
VSS VSS BH33 Y46
AH11 AW14 VSS VSS
VSS VSS BH35 Y8
AH3 AW18 VSS VSS
VSS VSS BH39
AH36 AW2 VSS
VSS VSS BH43
AH39 AW22 VSS
VSS VSS BH7 BG29
AH40 AW26 VSS VSS
VSS VSS D3 N24
AH42 AW28 VSS VSS
VSS VSS D12 AJ3
AH46 AW32 VSS VSS
VSS VSS D16 AD47
AH7 AW34 VSS VSS
VSS VSS D18
AJ19 AW36 VSS
VSS VSS D22 B43
AJ21 AW40 VSS VSS
VSS VSS D24 BE10
AJ24 AW48 VSS VSS
VSS VSS D26 BG41
AJ33 AY12 VSS VSS
VSS VSS D30
AJ34 AY22 VSS
VSS VSS D32 G14
AK12 AY28 VSS VSS
VSS VSS D34 H16
AK3 VSS VSS
VSS D38
VSS
D42 T36
VSS VSS
D8
VSS
E18 BG22
VSS VSS
E26 BG24
VSS VSS
G18 C22
VSS VSS
G20 AP13
VSS VSS
G26 M14
VSS VSS
G28 AP3
VSS VSS
A G36
G48
VSS
VSS
VSS
VSS
AP1
BE16 SYNC_MASTER=J5_MLB SYNC_DATE=03/21/2011 A

PAGE TITLE
H12
H18
VSS
VSS
VSS
VSS
BC16
BG28 PCH GROUNDS

H22 BJ28 DRAWING NUMBER SIZE
VSS VSS
H24
VSS Apple Inc. 051-9585 D
H26 REVISION
VSS
H30
VSS
R
3.0.0
H32 NOTICE OF PROPRIETARY PROPERTY: BRANCH
VSS
H34 THE INFORMATION CONTAINED HEREIN IS THE
VSS PROPRIETARY PROPERTY OF APPLE INC.
F3 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VSS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
23 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
20 7 =PP3V3_SUS_PCH_VCCSUS 16 7 =PP3V3_S0_PCH
7 =PP5V_SUS_PCH PCH V5REF_SUS Filter & Follower 24 7 =PP5V_S0_PCH PCH V5REF Filter & Follower =PP3V3_S0_PCH_VCC3_3_GPIO =PP1V05_S0_PCH_VCCSSC
20 7 20 7
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB) 1 mA (PCH Reference for 5V Tolerance on PCI)
2 4 2 1
R2404 2 D2400 R2405 5 D2400 C2475 1
10 NC 100 NC 1UF
5% BAT54DW-X-G 5% BAT54DW-X-G 1
C2486 1
C2485
NC
NC
1/16W 1/16W 10%
MF-LF 3
SOT-363
MF-LF 6
SOT-363 0.1UF 0.1UF 6.3V
2
10% 10% CERM
402 402 25V 25V 402
1 1
2 X5R 2 X5R
402 402 PLACE_NEAR=U1800.AG33:2.54mm
PP5V_SUS_PCH_V5REFSUS PP5V_S0_PCH_V5REF
MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM <1 mA S0-S5 MIN_NECK_WIDTH=0.2 MM <1 mA PLACE_NEAR=U1800.T34:2.54mm
VOLTAGE=5V VOLTAGE=5V PLACE_NEAR=U1800.AA16:2.54mm
C2438 1 MAKE_BASE=TRUE C2439 1 MAKE_BASE=TRUE
D
0.1UF
20%
10V
CERM 2
=PP5V_SUS_PCH_V5REFSUS 20
1UF
10%
10V
X5R 2
=PP5V_S0_PCH_V5REF 20 20 16 7 =PP1V05_S0_PCH_VCCDIFFCLK D
402 402
PLACE_NEAR=U1800.M26:2.54mm PLACE_NEAR=U1800.P34:2.54mm 20 7 =PP3V3_S0_PCH_VCC3_3_HVCMOS C2434 1
1UF
10%
C2424 1 6.3V
CERM 2
0.1UF 402
10% PLACE_NEAR=U1800.AF34:2.54mm
16V
X5R 2
402
CRITICAL
20 7 =PP1V05_S0_PCH_VCCIO_CLK
L2407
7 =PP1V8_S0_PCH_VCCTX_LVDS 0.1UH PP1V8_S0_PCH_VCCTX_LVDS_F 20
1 2 MIN_LINE_WIDTH=0.5 MM 20 7 =PP3V3_S5_PCH_VCCDSW 20 7 =PP3V3_S0_PCH_VCC3_3_PCI C2469 1
VOLTAGE=1.8V
1UF
0805 10%
C2499 1 C2421 1 6.3V
CERM 2
CRITICAL 0.1UF 0.1UF 402
C2400 1 1 C2406 1 C2408 20%
10V
10%
16V PLACE_NEAR=U1800.AF17:2.54mm
2 2
22UF 0.01UF 0.01UF CERM X5R
20% 10% 10% 402 402
6.3V 16V 16V
X5R-CERM-1 2 2 CERM 2 CERM PLACE_NEAR=U1800.T16:2.54mm PLACE_NEAR=U1800.BH29:2.54mm
603 402 402
PLACE_NEAR=U1800.AM37:2.54mm 20 16 7 =PP1V05_S0_PCH_VCCIO_SATA
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
20 7 =PP3V3_SUS_PCH_VCC_SPI 20 7 =PP3V3_S0_PCH_VCC3_3_SATA
C2444 1 C2452 1
C2442 1
C2423 1 1UF 1UF
7 =PP3V3_S0_PCH_VCCADAC R2450 PP3V3_S0_PCH_VCCA_DAC_F 20
10% 10%
0 MIN_LINE_WIDTH=0.4 MM
1UF 0.1UF 6.3V
2
6.3V
2
1 2 10% 10% CERM CERM
MIN_NECK_WIDTH=0.2 MM 6.3V 16V 402 402
VOLTAGE=3.3V CERM 2 X5R 2
5%
C 1/20W
MF
201
402
PLACE_NEAR=U1800.AJ2:2.54mm
402
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.AC17:2.54mm C
CRITICAL
PCH VCCIO BYPASS
C2450 1 1 C2451 1 C2455
10UF 0.1UF 0.01UF (PCH USB 1.05V PWR)
20%
6.3V
10%
16V
10%
16V 20 7 =PP3V3_SUS_PCH_VCCSUS_GPIO 20 7 =PP1V05_S0_PCH_VCCIO_USB
X5R 2 2 X5R 2 CERM
603 402 402
C2476 1 C2446 1
PLACE_NEAR=U1800.U48:2.54mm 1UF 1UF
PLACE_NEAR=U1800.U48:2.54mm 10% 10%
PLACE_NEAR=U1800.U48:2.54mm 6.3V 6.3V
CERM 2 CERM 2
402 402
PLACE_NEAR=U1800.P22:2.54mm PLACE_NEAR=U1800.P28:2.54mm
PCH VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)
20 7 =PP3V3_SUS_PCH_VCCSUS_USB 20 7 =PP1V05_S0_PCH_VCCIO
CRITICAL
L2451
7 =PP3V3_S0_PCH_VCC3_3_CLK R2451 10UH-0.12A-0.36OHM PP3V3_S0_PCH_VCC3_3_CLK_F 20
1
C2484 1
C2413 C2401 1 1
C2429 1
C2414 1
C2407 1
C2463
0.1UF 0.1UF 10UF 1UF 1UF 1UF 1UF
1 2 PP3V3_S0_PCH_VCC3_3_CLK_R 1 2
10% 10% 20% 10% 10% 10% 10%
MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V 16V 16V 6.3V 6.3V 6.3V 6.3V 6.3V
5% MIN_NECK_WIDTH=0.075 MM 0603 2 2 2 2 2 2 2
1/16W X5R X5R X5R CERM CERM CERM CERM
VOLTAGE=3.3V 402 402 603 402 402 402 402
MF-LF CRITICAL
402
C2453 1 1
C2454 PLACE_NEAR=U1800.P24:2.54mm PLACE_NEAR=U1800.AN27:2.54mm
10UF 1UF PLACE_NEAR=U1800.V24:2.54mm PLACE_NEAR=U1800.AN27:2.54mm
20% 10%
PLACE_NEAR=U1800.AN27:2.54mm
6.3V 10V PLACE_NEAR=U1800.AN27:2.54mm
X5R 2 2 X5R PLACE_NEAR=U1800.AN27:2.54mm
603 402
PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm PCH VCCSUSHDA BYPASS 20 7 =PP1V05_S0_PCH_VCCASW
B CRITICAL PCH VCCADPLLA Filter

24 20 7 =PP3V3R1V5_S0_PCH_VCCSUSHDA
B
L2490 (PCH DPLLA PWR) C2441 1
C2420 1
C2428 1 1
C2426 1
C2456 1
C2496
7 =PP1V05_S0_PCH_VCCADPLL R2490 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLA_F 20
0.1UF 22UF 22UF 1UF 1UF 1UF
0 MIN_LINE_WIDTH=0.4 MM 20% 20% 20% 10% 10% 10%
1 2 PP1V05_S0_PCH_VCCADPLLA_R 1 2
MIN_NECK_WIDTH=0.2 MM 68 mA 10V
CERM 2
6.3V
X5R-CERM-1 2
6.3V
X5R-CERM-1 2 2
6.3V
CERM 2
6.3V
CERM 2
6.3V
CERM
MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V 402 603 603 402 402 402
5% MIN_NECK_WIDTH=0.2 MM 0603
1/16W VOLTAGE=1.05V PLACE_NEAR=U1800.P32:2.54mm
MF-LF CRITICAL NO STUFF PLACE_NEAR=U1800.AC27:2.54mm
402 PLACE_NEAR=U1800.AC27:2.54mm
C2491 1 1
C2492 PLACE_NEAR=U1800.AC27:2.54mm
220UF 1UF PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) 20%
2.5V 2
10%
6.3V PCH VCCCORE BYPASS
2
TANT
B16
CERM
402 20 19 7 =PP1V8_S0_PCH_VCC_DFTERM (PCH 1.05V CORE PWR)
20 7 =PP1V05_S0_PCH_VCC_CORE
PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BD47:2.54MM C2440 1
0.1UF
20%
CRITICAL PCH VCCADPLLB Filter 10V
CERM 2 C2460 1 1
C2481 1
C2482 1
C2483
L2491 (PCH DPLLB PWR) 402 10UF 1UF 1UF 1UF
20% 10% 10% 10%
R2491 10UH-0.12A-0.36OHM PLACE_NEAR=U1800.AJ16:2.54mm 6.3V 6.3V 6.3V 6.3V
PP1V05_S0_PCH_VCCADPLLB_F 20 X5R 2 2 CERM 2 CERM 2 CERM
1 2 PP1V05_S0_PCH_VCCADPLLB_R 1 2
MIN_NECK_WIDTH=0.2 MM 69 mA 603 402 402 402
5% MIN_NECK_WIDTH=0.2 MM 0603 PLACE_NEAR=U1800.AG26:2.54mm
1/16W VOLTAGE=1.05V PLACE_NEAR=U1800.AD21:2.54mm
MF-LF CRITICAL NO STUFF PLACE_NEAR=U1800.AG24:2.54mm
402 20 7 =PP1V05_S0_PCH_V_PROC_IO PLACE_NEAR=U1800.AJ27:2.54mm
C2493 1 1 C2494
220UF 1UF
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) 20% 10%
2.5V 2 6.3V
2
TANT
B16
CERM
402 C2416 1 1 C2417 1 C2430
4.7UF 0.1UF 0.1UF
PLACE_NEAR=U1800.BF47:2.54MM 20% 10% 10%
6.3V 16V 16V
PLACE_NEAR=U1800.BF47:2.54MM X5R 2 2 X5R 2 X5R
402 402 402
A CRITICAL
L2406
PAGE TITLE
10UH-0.58A-0.35OHM R2415
16 7 =PP1V05_S0_PCH
1 2 PP1V05_S0_PCH_VCCCLKDMI_R 1
0
2
PP1V05_S0_PCH_VCCCLKDMI_F
20
PCH DECOUPLING
1098AS-SM
MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.05V DRAWING NUMBER SIZE
5%
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)
VOLTAGE=1.05V 1/16W
MF-LF
20 7 =PP1V05_S0_PCH_VCC_DMI
402 REVISION
C2419 1
R
3.0.0
C2411 1 1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
10%
10UF 6.3V
2 THE INFORMATION CONTAINED HEREIN IS THE
20% CERM
6.3V 402 PROPRIETARY PROPERTY OF APPLE INC.
X5R 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PLACE_NEAR=U1800.AT20:2.54mm
PLACE_NEAR=U1800.AB36:2.54mm
603
PCH VCCIO BYPASS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
24 OF 132
PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
23 7 =PPVCCIO_S0_XDP CPU Micro2-XDP 23 7 =PPVCCIO_S0_XDP
CRITICAL NOTE: This is not the standard XDP pinout. XDP PLACE_NEAR=J2500.52:2.54mm
XDP_CONN_CPU Use with 921-0133 Adapter Flex to 93 23 10 XDP_CPU_TDO R2510 51 2 1
5% 1/20W MF 201
=PP3V3_S0_XDP J2500 support chipset debug.
7 XDP PLACE_NEAR=U1000.K61:2.54mm
DF40RC-60DP-0.4V
NO STUFF M-ST-SM 93 23 10 XDP_CPU_TDI R2511 51 2 1
1 5% 1/20W MF 201
R2540 62 61 XDP PLACE_NEAR=U1000.H59:2.54mm
1K
5% 93 23 10 XDP_CPU_TMS R2512 51 2 1
1/16W 5% 1/20W MF 201
MF-LF
402 2 1 XDP PLACE_NEAR=U1000.J58:2.54mm
2
XDP_CPU_PREQ_L OBSFN_A0 4 3
OBSFN_C0 CPU_CFG<16> XDP_CPU_TCK R2513 51 2 1
D
93 10
93 10
BI
IN XDP_CPU_PRDY_L OBSFN_A1 6
8
5
7
OBSFN_C1 CPU_CFG<17>
IN
IN
9 93
9 93
93 23 10
XDP
5% 1/20W MF
PLACE_NEAR=U1000.H63:2.54mm
201
D
93 23 10 XDP_CPU_TRST_L R2514 51 2 1
(R2560-R2563) 93 10 IN XDP_BPM_L<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<0> IN 9 23 93 5% 1/20W MF 201
XDP_CPU:BPM 93 10 IN XDP_BPM_L<1> OBSDATA_A1 12 11

OBSDATA_C1 CPU_CFG<1> IN 9 93
93 10 IN XDP_BPM_L<4> R2560 0 1 2 14 13
5% 1/20W MF 201
93 10 IN XDP_BPM_L<5> R2561 0 1 2 93 10 IN XDP_BPM_L<2> OBSDATA_A2 16 15
5% 1/20W MF 201
93 10 IN XDP_BPM_L<6> R2562 0 1 2 93 10 IN XDP_BPM_L<3> OBSDATA_A3 18 17
5% 1/20W MF 201
93 10 IN XDP_BPM_L<7> R2563 0 1 2 20 19
5% 1/20W MF 201
93 9 IN CPU_CFG<10> OBSFN_B0 22 21 OBSFN_D0 CPU_CFG<8> IN 9 93
(R2564-R2567) 93 9 IN CPU_CFG<11> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<9> IN 9 93
XDP_CPU:CFG 26 25
93 9 IN CPU_CFG<12> R2564 0 1 2 XDP_OBSDATA_B<0> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<4> IN 9 93

5% 1/20W MF 201
93 9 IN CPU_CFG<13> R2565 0 1 2 XDP_OBSDATA_B<1> OBSDATA_B1 30 29
OBSDATA_D1 CPU_CFG<5> IN 9 93
5% 1/20W MF 201
93 9 IN CPU_CFG<14> R2566 0 1 2 32 31
5% 1/20W MF 201
93 9 IN CPU_CFG<15> R2567 0 1 2 XDP_OBSDATA_B<2> OBSDATA_B2 34 33
OBSDATA_D2 CPU_CFG<6> IN 9 93
5% 1/20W MF 201 XDP PLACE_NEAR=R1841.1:2.54mm
XDP_OBSDATA_B<3> OBSDATA_B3 36 35 OBSDATA_D3 CPU_CFG<7> IN 9 93
R2515 0 1 2 ITPXDP_CLK100M_P IN 16 93
38 37
XDP 5% 1/20W MF 201
93 19 10 IN CPU_PWRGD R2500 1K 1 2 93 XDP_CPU_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 93 XDP_CPU_CLK100M_P XDP PLACE_NEAR=R1840.1:2.54mm
PLACE_NEAR=U1000.C60:2.54mm 5% 1/20W MF 201
R2516 0
XDP_CPU_PWRBTN_L HOOK1 42 41 ITPCLK#/HOOK5 93 XDP_CPU_CLK100M_N 1 2 ITPXDP_CLK100M_N IN 16 93
XDP 5% 1/20W MF 201
PM_PWRBTN_L R2502 0 1 2
VCC_OBS_AB 44 43 VCC_OBS_CD
45 23 17 OUT
PLACE_NEAR=U4900.P17:2.54mm 5% 1/20W MF 201 XDP_CPU_CFG<0> HOOK2 46 45
RESET#/HOOK6 XDP_CPURST_L XDP PLACE_NEAR=U1000.G3:2.54mm
XDP XDP_VR_READY HOOK3 48 47
DBR#/HOOK7 XDP_DBRESET_L OUT 10 23 24 93 R2505 1K 1 2 CPU_RESET_L IN 10 24
5% 1/20W MF 201
93 23 9 OUT CPU_CFG<0> R2501 1K 1 2 50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
PLACE_NEAR=U1000.B57:2.54mm 5% 1/20W MF 201
48 23 BI =SMBUS_XDP_SDA SDA 52 51
TDO XDP_CPU_TDO IN 10 23 93
XDP
PM_PCH_SYS_PWROK R2504 330 1 2
48 23 IN =SMBUS_XDP_SCL SCL 54 53
TRSTn XDP_CPU_TRST_L OUT 10 23 93
92 45 17 OUT
5% 1/20W MF 201 TCK1 NC
56 55
TDI XDP_CPU_TDI OUT 10 23 93
C 93 23 10 OUT XDP_CPU_TCK TCK0 58
60
57
59
TMS
XDP_PRESENT#
XDP_CPU_TMS OUT 10 23 93
C
(R2520-R2537) XDP XDP
XDP SIGNALS XDP PCH SIGNALS C2500 1
64 63
1 C2501
PCH SIGNALS Non-XDP Signals
0.1uF 0.1uF
23 OUT XDP_DA0_USB_EXTA_OC_L R2520 33 1 2 XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L IN 18 23
10%
16V
10%
16V
23 OUT XDP_DA1_USB_EXTB_OC_L R2521 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L IN 18 23
X5R
402
2
998-2516 2 X5R
402
23 OUT XDP_DA2_USB_EXTC_OC_L R2522 33 1 2 XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L IN 18 23 18 OUT XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L R2590 0 1 2 USB_EXTA_OC_L IN 42
5% 1/20W MF 201 5% 1/20W MF 201
23 OUT XDP_DA3_USB_EXTD_OC_L R2523 33 1 2 XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L IN 18 23 23 18 OUT XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L R2591 0 1 2 USB_EXTB_OC_L IN 42
5% 1/20W MF 201 5% 1/20W MF 201
23 18 IN XDP_DB2_PCH_GPIO10_AP_PWR_EN R2596 0 1 2 AP_PWR_EN OUT 18 32 74
5% 1/20W MF 201
23 OUT XDP_DB0_USB_EXTB_OC_EHCI_L R2524 33 1 2 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L IN 18 23 23 18 OUT XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE R2597 0 1 2 SDCONN_STATE_CHANGE IN 24
5% 1/20W MF 201 5% 1/20W MF 201
23 OUT XDP_DB1_USB_EXTD_OC_EHCI_L R2525 33 1 2 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L IN 18 23
5% 1/20W MF 201 NOTE: This is not the standard XDP pinout. 23 16 IN XDP_DC3_PCH_GPIO19_SATARDRVR_EN R2573 0 1 2 SATARDRVR_EN OUT 16 41
23 IN XDP_DB2_AP_PWR_EN R2526 33 1 2 XDP_DB2_PCH_GPIO10_AP_PWR_EN OUT 18 23 5% 1/20W MF 201
XDP_DB3_SDCONN_STATE_CHANGE R2527 33 1 2
5% 1/20W MF 201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
Use with 921-0133 Adapter Flex to
23 OUT IN 18 23
5% 1/20W MF 201 support chipset debug. 23 19 OUT XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L R2570 0 1 2 ISOLATE_CPU_MEM_L OUT 26
23 OUT XDP_FC0 R2528 33 1 2 XDP_FC0_PCH_GPIO15 IN 19 68 5% 1/20W MF 201
5% 1/20W MF 201
23 16 IN XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL R2572 0 1 2 DP_AUXCH_ISOL OUT 16 87
5% 1/20W MF 201
23 OUT XDP_FC1 R2529 33 1 2 XDP_FC1_PCH_GPIO0 IN 19
5% 1/20W MF 201
23 IN XDP_DC0_ISOLATE_CPU_MEM_L R2530 33 1 2 XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L OUT 19 23
23 IN XDP_DC1_MXM_GOOD R2531 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
XDP_DC1_PCH_GPIO35_MXM_GOOD OUT 19 PCH Micro2-XDP =PP3V3_S5_XDP 7
23 IN XDP_DC2_DP_AUXCH_ISOL R2532 33 1 2 XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT 16 23

5% 1/20W MF 201
23 IN XDP_DC3_SATARDRVR_EN R2533 33 1 2 XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT 16 23 CRITICAL
5% 1/20W MF 201
23 IN XDP_DD0_DP_GPU_TBT_SEL R2534 33 1 2 XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL OUT 19 XDP_CONN_PCH
5% 1/20W MF 201
23 IN XDP_DD1_JTAG_ISP_TCK R2535 33 1 2 XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK OUT 19 23 J2550
5% 1/20W MF 201
DF40RC-60DP-0.4V 23 19 OUT XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK R2575 0 1 2 JTAG_ISP_TCK OUT 8 19
M-ST-SM 5% 1/20W MF 201
23 IN XDP_DD2_AUD_IPHS_SWITCH_EN R2536 33 1 2 XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH OUT 19 23 23 19 OUT XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH R2576 0 1 2 AUD_IPHS_SWITCH_EN_PCH OUT 19 24
5% 1/20W MF 201 5% 1/20W MF 201
23 IN XDP_DD3_ENET_LOW_PWR R2537 33 1 2 XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH OUT 19 23
62 61 23 19 OUT XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH R2577 0 1 2 ENET_LOW_PWR_PCH OUT 19 24
5% 1/20W MF 201 5% 1/20W MF 201
B PCH/XDP Signal Isolation Notes: 2 1

B
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3 TP_XDP_PCH_OBSFN_A<0> OBSFN_A0 4 3
OBSFN_C0 XDP_FC0 23
doc id 404081. TP_XDP_PCH_OBSFN_A<1> OBSFN_A1 6 5

OBSFN_C1 XDP_FC1 23
Initially, stuffing both 33 and 0 ohms and validate whether 8 7
it is functional in that state, else add BOM options. 23 XDP_DA0_USB_EXTA_OC_L OBSDATA_A0 10 9

OBSDATA_C0 XDP_DC0_ISOLATE_CPU_MEM_L 23
- For isolated GPIOs: 23 XDP_DA1_USB_EXTB_OC_L OBSDATA_A1 12 11 OBSDATA_C1 XDP_DC1_MXM_GOOD 23
- ’Output’ non-XDP signals require pulls. 14 13
- ’Output’ PCH/XDP signals require pulls. 23 XDP_DA2_USB_EXTC_OC_L OBSDATA_A2 16 15

OBSDATA_C2 XDP_DC2_DP_AUXCH_ISOL 23
23 XDP_DA3_USB_EXTD_OC_L OBSDATA_A3 18 17 OBSDATA_C3 XDP_DC3_SATARDRVR_EN 23

20 19 7 =PP1V05_SUS_PCH_JTAG
TP_XDP_PCH_OBSFN_B<0> OBSFN_B0 22 21
OBSFN_D0 TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_B<1> OBSFN_B1 24 23
OBSFN_D1 TP_XDP_PCH_OBSFN_D<1> XDP PLACE_NEAR=J2550.52:2.54mm
26 25 23 16 XDP_PCH_TDO R2550 51 2 1
5% 1/20W MF 201
R252x, R253x, R257x and R259x should be placed where signal path 23 XDP_DB0_USB_EXTB_OC_EHCI_L OBSDATA_B0 28 27 OBSDATA_D0 XDP_DD0_DP_GPU_TBT_SEL 23
XDP PLACE_NEAR=U1800.K5:2.54mm
needs to split between route from PCH to J2550 23 XDP_DB1_USB_EXTD_OC_EHCI_L OBSDATA_B1 30 29
OBSDATA_D1 XDP_DD1_JTAG_ISP_TCK 23
XDP_PCH_TDI R2551 51 2 1
23 16
and path to non-XDP signal destination. 32 31 5% 1/20W MF 201
23 XDP_DB2_AP_PWR_EN OBSDATA_B2 34 33
OBSDATA_D2 XDP_DD2_AUD_IPHS_SWITCH_EN 23 XDP PLACE_NEAR=U1800.H7:2.54mm
23 XDP_DB3_SDCONN_STATE_CHANGE OBSDATA_B3 36 35
OBSDATA_D3 XDP_DD3_ENET_LOW_PWR 23 23 16 XDP_PCH_TMS R2552 51 2 1
5% 1/20W MF 201
38 37
XDP
XDP PLACE_NEAR=U1800.J3:2.54mm
92 89 74 45 IN ALL_SYS_PWRGD R2584 1K 1 2 XDP_PCH_S5_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 TP_XDP_PCH_HOOK4
PLACE_NEAR=J2550.39:2.54mm 5% 1/20W MF 201 23 16 XDP_PCH_TCK R2556 51 2 1
XDP_PCH_PWRBTN_L HOOK1 42 41 ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5 5% 1/20W MF 201
XDP
PM_PWRBTN_L R2585 0 1 2
VCC_OBS_AB 44 43 VCC_OBS_CD
45 23 17 OUT
PLACE_NEAR=U4900.P17:2.54mm 5% 1/20W MF 201 6 TP_XDPPCH_HOOK2 HOOK2 46 45 RESET#/HOOK6 XDPPCH_PLTRST_L IN 24 1K series R on PCH Support Page
6 TP_XDPPCH_HOOK3 HOOK3 48 47
DBR#/HOOK7 XDP_DBRESET_L OUT 10 23 24 93
50 49
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
A 48 23
48 23
BI =SMBUS_XDP_SDA
=SMBUS_XDP_SCL
SDA
SCL
52
54
51
53
TDO
TRSTn
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
IN 16 23
SYNC_MASTER=J31_ANNE SYNC_DATE=06/09/2011 A
IN PAGE TITLE
23 16 OUT XDP_PCH_TCK
TCK1
TCK0
NC
56
58
55
57
TDI
TMS
XDP_PCH_TDI
XDP_PCH_TMS
OUT 16 23
OUT 16 23
CPU & PCH XDP
DRAWING NUMBER SIZE
60 59 XDP_PRESENT#
XDP XDP Apple Inc. 051-9585 D
REVISION
C2580 1 1
C2581
0.1uF
64 63
0.1uF
R
3.0.0
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L R2580 1K 1 2 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
10%
16V
10%
16V NOTICE OF PROPRIETARY PROPERTY: BRANCH
23 18
5% 1/20W MF 201
18 23 X5R
402
2
998-2516 2 X5R
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L R2581 1K 1 2 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
23 18
5% 1/20W MF 201
18 23
25 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Ethernet WAKE# Isolation
=PP3V3_ENET_PHY
Platform Reset Connections
GPIO Glitch Prevention CRITICAL
7 36 72
Unbuffered LPC_RESET_L
R2681 OUT 89 96
1
R2630 33
Q2630 26 18 IN PLT_RESET_L 1 2 LPCPLUS_RESET_L OUT 6 47
24 18 7 =PP3V3_S3_PCH_GPIO 1
10K MAKE_BASE=TRUE MAKE_BASE=TRUE
5%
SSM3K15FV 5%
1/16W
G
1/16W
MF-LF
SOD-VESM-HF MF-LF
402 402 R2683
2 33
CRITICAL 8 1 C2150 1 2 SMC_LRESET_L OUT 45
S
0.1UF 32 17 6 OUT PCIE_WAKE_L ENET_WAKE_L =ENET_WAKE_L IN 36
D
5%
VCC 20% 3 2 MAKE_BASE=TRUE
D
1/16W
10V
U2150 2 CERM
MF-LF
402
SOT833 402
08
R2671
74LVC2G08GT
ENET_LOW_PWR_PCH 1 7 ENET_LOW_PWR
23 19 IN A1 Y1 OUT 30 36
0
92 24 17 IN PM_PCH_PWROK 2
B1 PCH Reset Button 1 2 PCA9557D_RESET_L OUT 31
FW_PWR_EN_PCH 5 3 FW_PWR_EN =PP3V3_S0_SB_PM 5%

19 IN
6
A2 Y2 OUT 39 92 7
1/16W
MF-LF
B2 1
402
GND R2695
4
4.7K XDP
5%
XDP 1/16W
R2689
MF-LF
R2696 402 1K
2 1 2 XDPPCH_PLTRST_L OUT 23
0
93 23 10 IN XDP_DBRESET_L 1 2 PM_SYSRST_L BI 6 17 45 5%
1/16W
5% MF-LF
1/16W 402
MF-LF
=PP3V3_S3_PCH_GPIO 402
24 18 7
OMIT R2687
0
1
R2697 1 2 GMUX_RESET_L
CRITICAL 8
1
C2152
SDCONN_STATE_CHANGE 0
5%
5%
1/16W
MAKE_BASE=TRUE
1/16W MF-LF =GMUX_PCIE_RESET_L OUT 89

0.1UF =PP3V3_S3_SDBUF
VCC 20%
7 MF-LF
402
402
10V
U2152 2 CERM
2
SOT833
08
402 1 C2630 SILK_PART=SYS RESET
0.1UF
74LVC2G08GT
TBT_PWR_EN_PCH 1 7 TBT_PWR_EN =FW_RESET_L
16 IN A1 Y1 OUT 35
10% OUT 39
92 24 17 IN PM_PCH_PWROK 2
B1 2
6.3V
X5R Buffered Series R is R4283
AUD_IPHS_SWITCH_EN_PCH 5 3 AUD_IPHS_SWITCH_EN 201
23 19 IN A2 Y2 OUT 63 Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.
6 =PP3V3_S0_RSTBUF
B2 24 7
GND CRITICAL
4 TC7SZ08FEAPE 5 CRITICAL
C 23 SDCONN_STATE_CHANGE
SOT665
4
Y U2630
A
2
1
5
MC74VHC1G08
SC70-HF
C
1 SDCONN_STATE_CHANGE_SMC 4 PLT_RST_BUF_L =ENET_RESET_L
B 30 46
U2680 MAKE_BASE=TRUE
OUT 30
2
3
1
3 R2680 =TBT_RESET_L
C2680 1 100K OUT 35
5%
0.1UF 1/16W
20% MF-LF Series R on Pg38, R3803
10V
2
CERM 2 402
402
R2688
0
1 2 AP_RESET_L OUT 32
5%
1/16W
R2655 MF-LF
22 Buffered CPU reset 402
96 18 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 45 96 ENET_MEDIA_SENSE ISOLATION CIRCUIT 24 7 =PP3V3_S0_RSTBUF
5%
1/20W CRITICAL R2693
MF
R2656 R2610 0
201 1 2 BKLT_PLT_RST_L OUT 90
18 IN LPC_CLK33M_LPCPLUS_R 1
22
2 LPC_CLK33M_LPCPLUS OUT 6 47 96 36 IN ENET_MEDIA_SENSE 1
12K 5%
2 ENET_MEDIA_SENSE_RDIV OUT 16
5 U2690 5%
5%
74LVC1G07 1/16W
MF-LF
402 MF-LF 1/16W SC70
1/20W 402
MF 2 4 PLT_RST_CPU_BUF_L CPU_RESET_L
R2657 201 MAKE_BASE=TRUE
OUT 10 23
22 CRITICAL NC
18 IN TP_PCI_CLK33M_OUT2 LPC_CLK33M_GMUX_R 1 2 LPC_CLK33M_GMUX OUT 89 VTT voltage divider on CPU page
SSM6N37FEAPE 1
MAKE_BASE=TRUE
5%
24 18 7 =PP3V3_S3_PCH_GPIO
D 3
1 3 R2690
1/20W
MF
Q2610 C2690 1
NC 100K
201 R2659 SOT563 0.1UF 5%
1/16W
22 1 20%
R2611 10V MF-LF
PCH_CLK33M_PCIOUT 1 2 PCH_CLK33M_PCIIN 2
2 402
18 IN OUT 16 96 CERM
100K
5% 402
5%
1/20W
MF
1/20W 5 G S 4
MF
201 201
2
B B
System RTC Power Source & 32kHz / 25MHz Clock Generator ENET_MEDIA_SENSE_EN_L
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

VDDIO_25M_A: SB power rail for XTAL circuit. 24 22 20 7 =PP3V3R1V5_S0_PCH_VCCSUSHDA
SSM6N37FEAPE If high, ME is disabled. This allows for full re-flashing of SPI ROM.
VDDIO_25M_B: Ethernet power rail for XTAL circuit. Q2610 SMC controls strap enable to allow in-field control of strap setting.
VDDIO_25M_C: T29 power rail for XTAL circuit. 7 =PPVBAT_G3_SYSCLK 1 SOT563 D 6
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
R2612
Coin-Cell: VBAT (300-ohm & 10uF RC)
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered. 0 22 7 =PP5V_S0_PCH
No Coin-Cell: 3.42V G3Hot (no RC) 5%
1/16W
7 =PP3V3_S5_SYSCLK
Coin-Cell & G3Hot: 3.42V G3Hot
MF-LF
402
2
2 G S 1
PCH ME Disable Strap 1
R2620
100K
5%
Coin-Cell & No G3Hot: 3.3V S5 ENET_MEDIA_SENSE_EN 1/20W
Q2620 MF
No Coin-Cell: 3.3V S5 2
201
SSM6N37FEAPE
GreenClk 25MHz Power 7 =PP3V3_ENET_SYSCLK No bypass necessary
SPI_DESCRIPTOR_OVERRIDE_LS5V
5
SOT563
G
Ethernet XTAL Power 7 =PPVDDIO_ENET_CLK
24 22 20 7 =PP3V3R1V5_S0_PCH_VCCSUSHDA
13
SB XTAL Power 7 =PPVDDIO_S0_SBCLK

5
S
SPI_DESCRIPTOR_OVERRIDE
T29 XTAL Power =PPVDDIO_T29_CLK
VDD_25M
+V3.3A
+3.42V
3
7
4
VBAT and +V3.3A are
1
internally ORed to R2621
create VDD_RTC_OUT. Q2620 D 6
1K
C2624 1
C2622 1
C2620 1 1
C2602 SSM6N37FEAPE 5%
1/20W
0.1UF 0.1UF 0.1UF 1UF U2600 +V3.3A should be first SOT563 MF
20% 20% 20% 10%
10V 10V 10V 10V 201
2
CERM 2 CERM 2 CERM 2 2 X5R SLG3NB148A available ~3.3V power
402 402 402 402-1 TQFN HDA_SDOUT_R
to reduce VBAT draw. OUT 16 96
CRITICAL 2 G S
11 12 SYSCLK_CLK32K_RTC
1 IPD = 9-50k
VDDIO_25M_A 32KHZ_A OUT 16
A 6
14
VDDIO_25M_B
VDDIO_25M_C 25MHZ_A 9 SYSCLK_CLK25M_SB R2600
45 IN SPI_DESCRIPTOR_OVERRIDE_L
C2605 OUT 16
0 PAGE TITLE
12PF R2605 25MHZ_B 8 SYSCLK_CLK25M_ENET_R 1 2 SYSCLK_CLK25M_ENET
2 1 SYSCLK_CLK25M_X2 1
0
2 SYSCLK_CLK25M_X2_R 3
X2 25MHZ_C 15 SYSCLK_CLK25M_TBT 33 5%
OUT 36
Chipset Support
OUT 1/20W DRAWING NUMBER SIZE
5% NO STUFF 4 X1 =PPVRTC_G3_OUT MF
5%
50V
CRITICAL 1/16W
1
VDD_RTC_OUT 1 For SB RTC Power
7
201
MF-LF
R2606
1
CERM
402 NC Y2605 402
1M
REVISION
THRM R
3.0.0
2
NC SM-3.2X2.5MM 5% GND PAD

1/16W
1
C2610
4
C2606 25.000MHZ-12PF-20PPM MF-LF

1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
3
10
16
17
402
7
2 10%
12PF 6.3V THE INFORMATION CONTAINED HEREIN IS THE
2 CERM PROPRIETARY PROPERTY OF APPLE INC.
1 2 SYSCLK_CLK25M_X1 402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5%
NOTE: 30 PPM crystal required I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
26 OF 132
50V
CERM III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM
HUB_ALLREM HUB_NONREM1_0,HUB_NONREM0_0
TABLE_BOMGROUP_ITEM
HUB_1NONREM HUB_NONREM1_0,HUB_NONREM0_1
USB MUX FOR LS/FS INTERNAL DEVICES HUB_2NONREM HUB_NONREM1_1,HUB_NONREM0_0
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
HUB_3NONREM HUB_NONREM1_1,HUB_NONREM0_1
NON_REM 1 : NON_REM 0 STRAP PIN CFG

BYPASS=U2700.5::2MM
D 25 7 =PP3V3_S3_USB_HUB
BYPASS=U27000.5::5MM 0
0
1
1
:
:
:
:
0
1
0
1
ALL PORTS ARE REMOVABLE
PORT 1 IS NON REMOVABLE
PORT 1&2 ARE NON REMOVABLE
PORT 1&2&3 ARE NON REMOVABLE
D
C2700 1
C2701 1 1
C2702 1
C2703 CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
4.7UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10%
6.3V 16V 16V 16V
2 2 2 2
X5R
603
X7R-CERM
402
X7R-CERM
402
X7R-CERM
402
BOM TABLE TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

BYPASS=U2700.15::2MM CRITICAL
TABLE_5_ITEM
338S0824 1 USB HUB 2514B U2700 USBHUB2514B

BYPASS=U2700.10::2MM TABLE_5_ITEM
BYPASS=U2700.23::5MM BYPASS=U2700.23::2MM 338S0923 1 USB HUB 2513B U2700

CRITICAL USBHUB2513B
TABLE_5_ITEM
338S0983 1 USB HUB 2512B U2700

CRITICAL USBHUB2512B
C2704 1
C2705 1
C2706 1
C2708 1
PPUSB_HUB2_VDD1V8
4.7UF 0.1UF 0.1UF 0.1UF MIN_LINE_WIDTH=0.4MM J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
20% 10% 10% 10%
6.3V
2
16V
2
16V
2
16V
2 VOLTAGE=1.8V J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
X5R
603
X7R-CERM
402
X7R-CERM
402
X7R-CERM
402 PPUSB_HUB2_VDD1V8PLL
1
C2713 1
C2714
MIN_LINE_WIDTH=0.4MM 0.1UF 1UF
10% 10%
10
15
23
29
36
14
34
16V 16V
VOLTAGE=1.8V 2 2
5
BYPASS=U2700.36::2MM 1
C2711 1
C2712 X7R-CERM
402
X5R
402
0.1UF 1UF
CRFILT
PLLFILT
CRITICAL BYPASS=U2650.29::2MM VDD33 10% 10%
Y2700 2
16V
X7R-CERM 2
16V
X5R
24.000M-60PPM-16PF 402 402
USB_HUB_XTAL_C 1 2
CRITICAL SYM VER 1
CRITICAL 5X3.2X1.4-SM =PP3V3_S3_USB_HUB
U2700 7 25
C2709 1 1
R2710
1
C2710
18PF 18PF USB2513B NOSTUFF NOSTUFF NOSTUFF NOSTUFF
5%
0 5% R2701 1 1 1 1
50V
2
5%
1/16W 2
50V
100
QFN R2716 R2717 R2718 R2719
HUB_NONREM1_1 HUB_NONREM0_1
CERM
402 MF-LF
CERM
402
1 2 USB_HUB_TEST 11
TEST USBDM_DN1/PRT_DIS_M1 1 USBHUB_DN1_N BI 8 10K 10K 10K 10K
402
OMIT BLUETOOTH FOR J5 & J3X 5% 5% 5% 5%
2
R2700 5% USBDP_DN1/PRT_DIS_P1 2 USBHUB_DN1_P BI 8 1/16W 1/16W 1/16W 1/16W
1 1 USB_HUB_RESET_L 26
C R2702 R2703 RESET*

C
1/16W 25 MF-LF MF-LF MF-LF MF-LF
1M MF-LF 402
2 402
2 402
2 402
10K 10K 1 2 402 USBDM_DN2/PRT_DIS_M2 3 USBHUB_DN2_N BI 8
2
5% 5% USB_HUB_XTAL1 33 XTALIN/CLKIN TP/KB FOR J5, IR FOR J3X
1/16W 1/16W 5%
32 USBDP_DN2/PRT_DIS_P2 4 USBHUB_DN2_P BI 8
MF-LF MF-LF 1/16W USB_HUB_XTAL2 XTALOUT
402 402 MF-LF 25 8 USBHUB_DN3_N
2 2 402 USBDM_DN3/PRT_DIS_M3 6 USBHUB_DN3_N BI 8 25
USB_HUB_NONREM0 28 USBHUB_DN3_P
SUSP_IND/LOCAL_PWR/NON_REM0 SMC DEBUG PORT FOR J5, TP/KB FOR J3X 25 8
CRITICAL USBDP_DN3/PRT_DIS_P3 7 USBHUB_DN3_P BI 8 25
USB_HUB_NONREM1 22
SDA/SMBDATA/NON_REM1
NC 8 USBHUB_DN4_N BI 8 25 25 8 USBHUB_DN4_N
24 9 NC FOR J5, SMC DEBUG PORT FOR J3X
HUB_NONREM1_0 HUB_NONREM0_0
USB_HUB_CFG_SEL0 SCL/SMBCLK/CFG_SEL0 NC USBHUB_DN4_P BI 8 25 25 8 USBHUB_DN4_P
USB_HUB_CFG_SEL1 25 12 TP_USB_HUB_PRTPWR1
R2704 1
1
R2705 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1*
10K 10K PRTPWR2/BC_EN2* 16 NC_USB_HUB_PRTPWR2
5% 5%
18 NC_USB_HUB_PRTPWR3 =PP3V3_S3_USB_HUB 7 25
1/16W 1/16W
1 1
PRTPWR3/BC_EN3*
MF-LF
402
MF-LF
402
R2706 R2707 NC 20 NC_USB_HUB_PRTPWR4
2 2 10K 10K
5% 5%
1/16W 1/16W
IPU OCS1* 13 TP_USB_HUB_OCS1 1
MF-LF
402
MF-LF
402 OCS2* 17 NC_USB_HUB_OCS2 R2708
2 2 IPU 10K
19 NC_USB_HUB_OCS3
IPU OSC3* 5%
1/16W
IPU NC 21 NC_USB_HUB_OCS4 MF-LF
402
2
RBIAS 35 USB_HUB_RBIAS
J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION 27 USB_HUB_VBUS_DET
VBUS_DET
J3X USE 197S0284 FOR Y2700 TO SAVE COST CRITICAL
USBDM_UP 30 USB_HUB_UP_N BI 18 95
1
R2709
USBDP_UP 31 USB_HUB_UP_P BI 18 95 12K TO CONNECT TP/KB TO PCH XHCI
1%
THRM_PAD 1/16W NOSTUFF R5701 & R5702, STUFF R2720 & R2721
7 =PP3V3_S3_USB_RESET
PCH PORT 7 (EHCI1) MF
402
2 NOSTUFF
37
R2720
27
95 18 BI USB_EXTD_XHCI_N 1 2 USB_TPAD_R_N BI 53 95 101
B 1 TO PCH XHCI
NOSTUFF
R2721
5%
1/16W TO TP/KB B
R2712 27
MF-LF
402
10K 95 18 BI USB_EXTD_XHCI_P 1 2 USB_TPAD_R_P BI 53 95 101
5%
1/16W 5%
MF-LF 1/16W
MF-LF
2 402 402
USB_HUB_RESET_L 25
C2715 1
0.1UF
10%
16V
X7R-CERM 2
402
BYPASS=U2700.26::2MM
USB XHCI/EHCI2 PORT MUX FOR EXT B
7 =PP3V3_S3_USBMUX
C2760 1
9
0.1UF
20%
10V VCC
CERM 2
95 18 USB_EXTB_EHCI_P 402 5 M+ Y+ 1 USB_EXTB_MUX_P 43 95
BI BI
PCH PORT 9 (EHCI2) USB_EXTB_EHCI_N 4 M- Y- 2 USB_EXTB_MUX_N
TO CONNECTOR
95 18 BI U2760 BI 43 95
A 95 18 BI USB_EXTB_XHCI_P 7 D+
PI3USB102ZLE
TQFN SYNC_MASTER=J31_LINDA SYNC_DATE=09/16/2011 A
CRITICAL PAGE TITLE
PCH PORT 1 (XHCI) USB_EXTB_XHCI_N 6 D-
95 18 BI
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE USB HUB & MUX
8 OE* SEL 10 USB_EXTB_SEL_XHCI DRAWING NUMBER SIZE
IN 16
PCH GPIO60 051-9585 D
GND SEL=0 CHOOSE USB EHCI2 PORT Apple Inc. REVISION
SEL=1 CHOOSE USB XHCI PORT
3.0.0
3

27 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
D WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. D
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

1V5 S0 "PGOOD" for CPU
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L 7 =PP3V3_S5_CPU_VCCDDR
74 45 32 17 IN PM_SLP_S4_L PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CPUMEM_S0
1
R2805 15 13 10 7 =PP1V5_S3_CPU_VCCDDR PM_MEM_PWRGD OUT 10 17 93
10K 1
R2822
5%
1/16W 10K
MF-LF 5%
2 402 1/16W CRITICAL 6
MF-LF
CPUMEM_S0 402
D
SSM6N37FEAPE
P1V5CPU_EN OUT 73
R2820 1
2
Q2820
CRITICAL 27.4K DMB53D0UV
7 =PP3V3_S3_MEMRESET Q2805 1% SOT-563
CPUMEM_S0 SOT563 D 6 1/16W
MF-LF PM_MEM_PWRGD_L 2 G
402
R2801 1
2
100K
5% 3 CRITICAL
1/16W
MF-LF Q2820 S
402
2
2 G S P1V5_S0_DIV 5
1 DMB53D0UV 1
SOT-563
P1V5CPU_EN_L
CPUMEM_S0 4
CRITICAL 1
NO STUFF
SSM6N37FEAPE SSM6N37FEAPE R2821 C2820 1
D 3 3 D CRITICAL 33.2K
Q2800 Q2805 1%
0.001UF
C SOT563 SOT563
CPUMEM_S0 1/16W
MF-LF
402
2
20%
50V
CERM
402
2 C
5 G S 4 4
S G 5
23 IN ISOLATE_CPU_MEM_L PM_SLP_S3_L IN 6 17 45 74
CPUMEM_S0
1
R2810
10K
5%
1/16W
MF-LF
2 402
CPUMEM_S0
MEMVTT_EN OUT 8
=PP5V_S3_MEMRESET SSM6N37FEAPE
MEMVTT Clamp
26 7
CRITICAL
Q2810
CPUMEM_S0 CPUMEM_S0 SOT563 D 6
1 1
Ensures CKE signals are held low in S3
R2815 R2802
100K 100K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 402 2 G S 7 =PPVTT_S0_VTTCLAMP
2 2 1
CPUMEM_S0 CPUMEM_S0
MEMVTT_EN_L 1
SSM6N37FEAPE
CRITICAL CRITICAL R2850
Q2800 10 75mA max load @ 0.75V
CPUMEM_S0 SSM6N37FEAPE CPUMEM_S0
SOT563 D 6 3 D CRITICAL
5%
1/10W 60mW max power
Q2815 Q2810 MF-LF
CRITICAL 603
2
SOT563
SSM6N37FEAPE
CPUMEM_S0
VTTCLAMP_L
2
SSM6N37FEAPE
G
SOT563
2 G S S G 5 26 7 =PP5V_S3_MEMRESET Q2850
B
1 4
B CPUMEM_S0 SOT563 D 6
D
PLT_RESET_L IN 18 24
R2851 1
6
NOSTUFF 100K
5%
1
C2817 1/16W
MF-LF
0.047UF 402 2 G S
10% CRITICAL 2 1
2
6.3V
X5R
=PP1V5_S3_MEMRESET 7
201 CPUMEM_S0 VTTCLAMP_EN
CPUMEM_S0 CPUMEM_S0
Q2815 1
CPUMEM_S0 CRITICAL
R2816 1
C2816 SSM6N37FEAPE NO STUFF
SSM6N37FEAPE 1K D 3
MEMRESET_ISOL_LS5V_L 0.1UF Q2850 C2851 1

5
31 OUT SOT563 5%
10%
1/16W
G
MF-LF 2
16V SOT563 0.001UF
X5R 20%
402 402 50V
2 2
CERM
S
=MEM_RESET_L CPU_MEM_RESET_L MEM_RESET_L 402

10 IN OUT 27 29
MAKE_BASE=TRUE G S
3
5
4
68 8 IN =DDRVTT_EN
CPUMEM_S3
R2817
0
1 2
5%
1/16W
MF-LF
402
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN
S0 0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1
to 2 0 0 1 1 1 1 0 1
A S3
3
4
0
0
0
0
0
1
1
1
X
X
1
1
0
0
0
1
PAGE TITLE
5 0 1 1 1 0 (*) 1 1 1
to 6 0 1 1 1 1 1 1 1
CPU Memory S3 Support
DRAWING NUMBER SIZE
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
S0 Apple Inc. 051-9585 D
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
3.0.0
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
28 OF 132
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
7 =PP1V5_S3_MEM_A
Power aliases required by this page:
- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
1
C2910 1
C2911 1
C2912 1
C2913 1
C2914 1
C2915 1
C2916 1
C2917 1
C2918 1
C2919 1
C2920 1
C2921 1
C2922 1
C2923
- =PP0V75_S0_MEM_VTT_A
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
- =PPSPD_S0_MEM_A (2.5 - 3.3V) 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402
Signal aliases required by this page: PLACE_NEAR=J2900.75:2.54mm
1
C2900 1
C2901 PLACE_NEAR=J2900.75:2.54mm
- =I2C_SODIMMA_SCL
10UF 10UF
20% 20%
- =I2C_SODIMMA_SDA
6.3V 6.3V PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm 2 X5R 2 X5R PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm PLACE_NEAR=J2900.75:2.54mm
D BOM options provided by this page:
(NONE)
603 603
93 31 PP0V75_S3_MEM_VREFDQ_A D
1
C2930 1
C2931
2.2UF 0.1UF
20% 20%
PLACE_NEAR=J2900.75:2.54mm 6.3V 10V
2 2
CERM CERM
402-LF 402
OMIT_TABLE
OMIT_TABLE 1 2
VREFDQ VSS
3 4
VSS DQ4 =MEM_A_DQ<4>
BI 28
KEY
73 74 5 6
94 11 6 IN MEM_A_CKE<0> CKE0 CKE1 MEM_A_CKE<1>
IN 6 11 94 28 BI =MEM_A_DQ<0> DQ0 DQ5 =MEM_A_DQ<5>
BI 28
75 76 7
CRITICAL 8
VDD VDD 28 BI =MEM_A_DQ<1> DQ1 VSS
77 78 9 10
NC NC J2900 A15 MEM_A_A<15>
IN 6 11 94 VSS DQS0* =MEM_A_DQS_N<0>
BI 28
94 11 6 IN MEM_A_BA<2> 79 BA2 F-RT-THB A14 80 MEM_A_A<14>

IN 6 11 94
11 DM0 J2900 DQS0 12 =MEM_A_DQS_P<0>
BI 28
81 82 13 F-RT-THB 14
(SYMBOL 2 OF 2)
VDD VDD VSS VSS
DDR3-SODIMM-DUAL-K6
DDR3-SODIMM-DUAL-K6
(SYMBOL 1 OF 2)
83 84 15 16
94 11 6 IN MEM_A_A<12> A12/BC* A11 MEM_A_A<11>
BI 28
85 86 17 18
94 11 6 IN MEM_A_A<9> A9 A7 MEM_A_A<7>
BI 28
87 88 19 20
VDD VDD VSS VSS
94 11 6 MEM_A_A<8> 89 A8 A6 90 MEM_A_A<6> 6 11 94 28 =MEM_A_DQ<8> 21 DQ8 DQ12 22 =MEM_A_DQ<12> 28
IN IN BI BI
91 92 23 24
94 11 6 IN MEM_A_A<5> A5 A4 MEM_A_A<4>
BI 28
93 94 25 26
VDD VDD VSS VSS
94 11 6 MEM_A_A<3> 95 A3 A2 96 MEM_A_A<2> 6 11 94 28 =MEM_A_DQS_N<1> 27 DQS1* DM1 28
IN IN BI
97 98 29 30
94 11 6 IN MEM_A_A<1> A1 A0 MEM_A_A<0>
IN 6 11 94 28 BI =MEM_A_DQS_P<1> DQS1 RESET* MEM_RESET_L
IN 26 29
99 100 31 32
VDD VDD VSS VSS
94 11 6 MEM_A_CLK_P<0> 101 CK0 CK1 102 MEM_A_CLK_P<1> 6 11 94 28 =MEM_A_DQ<10> 33 DQ10 DQ14 34 =MEM_A_DQ<14> 28
IN IN BI BI
94 11 6 MEM_A_CLK_N<0> 103 CK0* CK1* 104 MEM_A_CLK_N<1> 6 11 94 28 =MEM_A_DQ<11> 35 DQ11 DQ15 36 =MEM_A_DQ<15> 28
C
IN IN BI BI
C 94 11 6 MEM_A_A<10>
105
107
VDD
A10/AP
VDD
BA1
106
108 MEM_A_BA<1> 6 11 94 28 =MEM_A_DQ<16>

37
39
VSS
DQ16
VSS
DQ20
38
40 =MEM_A_DQ<20> 28
IN IN BI BI
109 110 41 42
94 11 6 IN MEM_A_BA<0> BA0 RAS* MEM_A_RAS_L IN 6 11 94 28 BI =MEM_A_DQ<17> DQ17 DQ21 =MEM_A_DQ<21> BI 28
111 112 43 44
VDD VDD VSS VSS
113 114 45 46
94 11 6 IN MEM_A_WE_L WE* S0* MEM_A_CS_L<0>
IN 6 11 94 28 BI =MEM_A_DQS_N<2> DQS2* DM2
115 116 47 48
94 11 6 IN MEM_A_CAS_L CAS* ODT0 MEM_A_ODT<0>
IN 6 11 94 28 BI =MEM_A_DQS_P<2> DQS2 VSS
117 VDD VDD 118 49 VSS DQ22 50 =MEM_A_DQ<22> 28
BI
119 120 51 52
94 11 6 IN MEM_A_A<13> A13 ODT1 MEM_A_ODT<1>
BI 28
121 122 53 54
94 11 6 IN MEM_A_CS_L<1> S1* NC NC 28 BI =MEM_A_DQ<19> DQ19 VSS
123 124 55 56
VDD VDD VSS DQ28 =MEM_A_DQ<28>
BI 28
125 TEST VREFCA 126 =MEM_A_DQ<24> 57 DQ24 DQ29 58 =MEM_A_DQ<29>
NC 28 BI BI 28
127 128 59 60
VSS VSS 28 BI =MEM_A_DQ<25> DQ25 VSS
129 130 61 62
28 BI =MEM_A_DQ<32> DQ32 DQ36 =MEM_A_DQ<36>
BI 28 VSS DQS3* =MEM_A_DQS_N<3>
BI 28
131 132 63 64
BI 28 DM3 DQS3 =MEM_A_DQS_P<3>
BI 28
133 134 65 66
VSS VSS VSS VSS
135 136 67 68
28 BI =MEM_A_DQS_N<4> DQS4* DM4 28 BI =MEM_A_DQ<26> DQ26 DQ30 =MEM_A_DQ<30>
BI 28
137 138 69 70
28 BI =MEM_A_DQS_P<4> DQS4 VSS 28 BI =MEM_A_DQ<27> DQ27 DQ31 =MEM_A_DQ<31> BI 28
139 VSS DQ38 140 =MEM_A_DQ<38> 28
71 VSS VSS 72
BI
141 142
BI 28 KEY
143 144
28 BI =MEM_A_DQ<35> DQ35 VSS
145 146
BI 28
147 148
See CSA05 BOM table
BI 28
149 150
28 BI =MEM_A_DQ<41> DQ41 VSS
151 152
VSS DQS5* =MEM_A_DQS_N<5> BI 28
153 DM5 DQS5 154 =MEM_A_DQS_P<5> 28
BI
155 156
VSS VSS
B 28
28
BI
BI
=MEM_A_DQ<42>
=MEM_A_DQ<43>
157
159
DQ42
DQ43
DQ46
DQ47
158
160
=MEM_A_DQ<46>
=MEM_A_DQ<47>
BI
BI
28
28
B
161 162
VSS VSS
163 164
BI 28
165 166
BI 28
167 168
VSS VSS
28 =MEM_A_DQS_N<6> 169 DQS6* DM6 170
BI
171 172
28 BI =MEM_A_DQS_P<6> DQS6 VSS
173 174
VSS DQ54 =MEM_A_DQ<54> BI 28
28 =MEM_A_DQ<50> 175 DQ50 DQ55 176 =MEM_A_DQ<55> 28 PP0V75_S3_MEM_VREFCA_A 31 93

BI BI
28 =MEM_A_DQ<51> 177 DQ51 VSS 178
BI
179 180
BI 28
181 182
28 BI =MEM_A_DQ<56> DQ56 DQ61 =MEM_A_DQ<61> BI 28
1
C2935 1
C2936
28 =MEM_A_DQ<57> 183 DQ57 VSS 184 2.2UF 0.1UF
BI 20% 20%
185 VSS DQS7* 186 =MEM_A_DQS_N<7> 28
6.3V 10V
BI 2
CERM
2
CERM
187 188 402-LF 402
DM7 DQS7 =MEM_A_DQS_P<7> BI 28
189 VSS VSS 190
191 192
BI 28
193 194
28 BI =MEM_A_DQ<59> DQ59 DQ63 =MEM_A_DQ<63> BI 28
195 196
VSS VSS
6 MEM_A_SA<0> 197 SA0 EVENT* 198 MEM_EVENT_L 29 45 46
OUT
7 =PPSPD_S0_MEM_A
199 VDDSPD SDA 200 =I2C_SODIMMA_SDA 48 "Factory" (top) slot
BI
6 MEM_A_SA<1> 201 SA1 SCL 202 =I2C_SODIMMA_SCL 48
IN
203 VTT VTT 204 =PP0V75_S0_MEM_VTT_A 7
1 1
1
C2940 R2940 R2941
A 2
2.2UF
20%
6.3V
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
516-0229
SPD ADDR=0xA0(WR)/0xA1(RD)
1
C2950
1UF
1
C2951
1UF
1
C2952
1UF
1
C2953
1UF SYNC_MASTER=K92_SUMA SYNC_DATE=06/23/2010 A
CERM
402 402
10% 10% 10% 10% PAGE TITLE
402-LF 2 2 10V 10V 10V 10V
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402 DDR3 SO-DIMM Connector A
DRAWING NUMBER SIZE

REVISION
R
3.0.0
29 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU CHANNEL A DQS 0 -> DIMM A DQS 0 CPU CHANNEL B DQS 0 -> DIMM B DQS 0
94 11 6 MEM_A_DQS_N<0> =MEM_A_DQS_N<0> 27 94 11 6 MEM_B_DQS_N<0> =MEM_B_DQS_N<0> 29
MAKE_BASE=TRUE MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_P<0> =MEM_A_DQS_P<0> 27 94 11 6 MEM_B_DQS_P<0> =MEM_B_DQS_P<0> 29
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ<7> =MEM_A_DQ<3> 27 94 11 6 MEM_B_DQ<7> =MEM_B_DQ<6> 29

D 94 11 6 MEM_A_DQ<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<2> 27 94 11 6 MEM_B_DQ<0>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<0> 29
D


C CPU CHANNEL A DQS 3 -> DIMM A DQS 3

94 11 6 MEM_A_DQS_N<3>
MAKE_BASE=TRUE
=MEM_A_DQS_N<3> 27
CPU CHANNEL B DQS 3 -> DIMM B DQS 3
94 11 6 MEM_B_DQS_N<3>
MAKE_BASE=TRUE
=MEM_B_DQS_N<3> 29
C


94 11 6 MEM_A_DQS_N<5>
B
=MEM_A_DQS_N<5> 94 11 6 MEM_B_DQS_N<5> =MEM_B_DQS_N<5>
B
27 29


A 94 11 6 MEM_A_DQS_P<7>
MAKE_BASE=TRUE
=MEM_A_DQS_P<7> 27 94 11 6 MEM_B_DQS_P<7>
MAKE_BASE=TRUE
=MEM_B_DQS_P<7> 29
SYNC_MASTER=K92_SUMA SYNC_DATE=05/10/2010 A
PAGE TITLE
94 11 6 MEM_A_DQ<62> =MEM_A_DQ<58> 27 94 11 6 MEM_B_DQ<62> =MEM_B_DQ<62> 29 DDR3 Byte/Bit Swaps
94 11 6 MEM_A_DQ<61> =MEM_A_DQ<56> 27 94 11 6 MEM_B_DQ<61> =MEM_B_DQ<61> 29 DRAWING NUMBER SIZE
94 11 6 MEM_A_DQ<60>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<61> 27 94 11 6 MEM_B_DQ<60>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<60> 29
94 11 6 MEM_A_DQ<59> =MEM_A_DQ<63> 27 94 11 6 MEM_B_DQ<59> =MEM_B_DQ<59> 29 REVISION
94 11 6 MEM_A_DQ<58>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<62> 27 94 11 6 MEM_B_DQ<58>
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<58> 29
R
3.0.0
94 11 6 MEM_A_DQ<57> =MEM_A_DQ<57> 27 94 11 6 MEM_B_DQ<57> =MEM_B_DQ<57> 29 NOTICE OF PROPRIETARY PROPERTY: BRANCH
94 11 6 MEM_A_DQ<56> =MEM_A_DQ<60> 27 94 11 6 MEM_B_DQ<56> =MEM_B_DQ<56> 29 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE INC.
30 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
7 =PP1V5_S3_MEM_B
- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
1
C3110 1
C3111 1
C3112 1
C3113 1
C3114 1
C3115 1
C3116 1
C3117 1
C3118 1
C3119 1
C3120 1
C3121 1
C3122 1
C3123
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF PLACE_NEAR=J3100.75:2.54mm
- =PP0V75_S0_MEM_VTT_B
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
PLACE_NEAR=J3100.75:2.54mm
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
- =PPSPD_S0_MEM_B (2.5 - 3.3V) 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402
Signal aliases required by this page:
1
C3100 1
C3101
- =I2C_SODIMMB_SCL
10UF 10UF PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm
20% 20%
- =I2C_SODIMMB_SDA
6.3V 6.3V PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm PLACE_NEAR=J3100.75:2.54mm
2 X5R 2 X5R
D BOM options provided by this page:
(NONE)
603 603
93 31 PP0V75_S3_MEM_VREFDQ_B D
1
C3130 1
C3131
2.2UF 0.1UF
PLACE_NEAR=J3100.75:2.54mm 20% 20%
6.3V 10V
2 2
CERM CERM
402-LF 402
OMIT_TABLE
OMIT_TABLE 1 2
VREFDQ VSS
3 4
VSS DQ4 =MEM_B_DQ<4>
BI 28
KEY
73 74 5 6
94 11 6 IN MEM_B_CKE<0> CKE0 CKE1 MEM_B_CKE<1>
IN 6 11 94 28 BI =MEM_B_DQ<0> DQ0 DQ5 =MEM_B_DQ<5>
BI 28
75 76 7
CRITICAL 8
VDD VDD 28 BI =MEM_B_DQ<1> DQ1 VSS
77 78 9 10
NC NC A15 MEM_B_A<15>
IN 6 11 94 VSS DQS0* =MEM_B_DQS_N<0>
BI 28
94 11 6 IN MEM_B_BA<2> 79 BA2 J3100 A14 80 MEM_B_A<14>

IN 6 11 94
11 DM0 J3100 DQS0 12 =MEM_B_DQS_P<0>
BI 28
81 82 13 F-RT-BGA6 14
VDD F-RT-BGA6 VDD VSS VSS
DDR3-SODIMM
(1 OF 2)
(2 OF 2)
83 84 15 16
DDR3-SODIMM
94 11 6 IN MEM_B_A<12> A12/BC* A11 MEM_B_A<11>
BI 28
85 86 17 18
94 11 6 IN MEM_B_A<9> A9 A7 MEM_B_A<7>
BI 28
87 88 19 20
VDD VDD VSS VSS
94 11 6 MEM_B_A<8> 89 A8 A6 90 MEM_B_A<6> 6 11 94 28 =MEM_B_DQ<8> 21 DQ8 DQ12 22 =MEM_B_DQ<12> 28
IN IN BI BI
91 92 23 24
94 11 6 IN MEM_B_A<5> A5 A4 MEM_B_A<4>
BI 28
93 94 25 26
VDD VDD VSS VSS
94 11 6 MEM_B_A<3> 95 A3 A2 96 MEM_B_A<2> 6 11 94 28 =MEM_B_DQS_N<1> 27 DQS1* DM1 28
IN IN BI
97 98 29 30
94 11 6 IN MEM_B_A<1> A1 A0 MEM_B_A<0>
IN 6 11 94 28 BI =MEM_B_DQS_P<1> DQS1 RESET* MEM_RESET_L
IN 26 27
99 100 31 32
VDD VDD VSS VSS
94 11 6 MEM_B_CLK_P<0> 101 CK0 CK1 102 MEM_B_CLK_P<1> 6 11 94 28 =MEM_B_DQ<10> 33 DQ10 DQ14 34 =MEM_B_DQ<14> 28
IN IN BI BI
94 11 6 MEM_B_CLK_N<0> 103 CK0* CK1* 104 MEM_B_CLK_N<1> 6 11 94 28 =MEM_B_DQ<11> 35 DQ11 DQ15 36 =MEM_B_DQ<15> 28
C
IN IN BI BI
C 94 11 6 MEM_B_A<10>
105
107
VDD
A10/AP
VDD
BA1
106
108 MEM_B_BA<1> 6 11 94 28 =MEM_B_DQ<16>

37
39
VSS
DQ16
VSS
DQ20
38
40 =MEM_B_DQ<20> 28
IN IN BI BI
109 110 41 42
94 11 6 IN MEM_B_BA<0> BA0 RAS* MEM_B_RAS_L IN 6 11 94 28 BI =MEM_B_DQ<17> DQ17 DQ21 =MEM_B_DQ<21> BI 28
111 112 43 44
VDD VDD VSS VSS
113 114 45 46
94 11 6 IN MEM_B_WE_L WE* S0* MEM_B_CS_L<0>
IN 6 11 94 28 BI =MEM_B_DQS_N<2> DQS2* DM2
115 116 47 48
94 11 6 IN MEM_B_CAS_L CAS* ODT0 MEM_B_ODT<0>
IN 6 11 94 28 BI =MEM_B_DQS_P<2> DQS2 VSS
117 VDD VDD 118 49 VSS DQ22 50 =MEM_B_DQ<22> 28
BI
119 120 51 52
94 11 6 IN MEM_B_A<13> A13 ODT1 MEM_B_ODT<1>
BI 28
121 122 53 54
94 11 6 IN MEM_B_CS_L<1> S1* NC NC 28 BI =MEM_B_DQ<19> DQ19 VSS
123 124 55 56
VDD VDD VSS DQ28 =MEM_B_DQ<28>
BI 28
125 TEST VREFCA 126 =MEM_B_DQ<24> 57 DQ24 DQ29 58 =MEM_B_DQ<29>
NC 28 BI BI 28
127 128 59 60
VSS VSS 28 BI =MEM_B_DQ<25> DQ25 VSS
129 130 61 62
28 BI =MEM_B_DQ<32> DQ32 DQ36 =MEM_B_DQ<36>
BI 28 VSS DQS3* =MEM_B_DQS_N<3>
BI 28
131 132 63 64
BI 28 DM3 DQS3 =MEM_B_DQS_P<3>
BI 28
133 134 65 66
VSS VSS VSS VSS
135 136 67 68
28 BI =MEM_B_DQS_N<4> DQS4* DM4 28 BI =MEM_B_DQ<26> DQ26 DQ30 =MEM_B_DQ<30>
BI 28
137 138 69 70
28 BI =MEM_B_DQS_P<4> DQS4 VSS 28 BI =MEM_B_DQ<27> DQ27 DQ31 =MEM_B_DQ<31> BI 28
139 VSS DQ38 140 =MEM_B_DQ<38> 28
71 VSS VSS 72
BI
141 142
BI 28 KEY
143 144
28 BI =MEM_B_DQ<35> DQ35 VSS
145 146
BI 28 516S0806
147 148
BI 28
149 150
28 BI =MEM_B_DQ<41> DQ41 VSS
151 152
VSS DQS5* =MEM_B_DQS_N<5> BI 28
153 DM5 DQS5 154 =MEM_B_DQS_P<5> 28
BI
155 156
VSS VSS
B 28
28
BI
BI
=MEM_B_DQ<42>
=MEM_B_DQ<43>
157
159
DQ42
DQ43
DQ46
DQ47
158
160
=MEM_B_DQ<46>
=MEM_B_DQ<47>
BI
BI
28
28
B
161 162
VSS VSS
163 164
BI 28
165 166
BI 28
167 168
VSS VSS
28 =MEM_B_DQS_N<6> 169 DQS6* DM6 170
BI
171 172
28 BI =MEM_B_DQS_P<6> DQS6 VSS
173 174
VSS DQ54 =MEM_B_DQ<54> BI 28
28 =MEM_B_DQ<50> 175 DQ50 DQ55 176 =MEM_B_DQ<55> 28 PP0V75_S3_MEM_VREFCA_B 31 93

BI BI
28 =MEM_B_DQ<51> 177 DQ51 VSS 178
BI
179 180
BI 28
181 182
28 BI =MEM_B_DQ<56> DQ56 DQ61 =MEM_B_DQ<61> BI 28
1
C3135 1
C3136
28 =MEM_B_DQ<57> 183 DQ57 VSS 184 2.2UF 0.1UF
BI 20% 20%
185 VSS DQS7* 186 =MEM_B_DQS_N<7> 28
6.3V 10V
BI 2
CERM
2
CERM
187 188 402-LF 402
DM7 DQS7 =MEM_B_DQS_P<7> BI 28
189 VSS VSS 190
191 192
BI 28
193 194
28 BI =MEM_B_DQ<59> DQ59 DQ63 =MEM_B_DQ<63> BI 28
195 196
VSS VSS
6 MEM_B_SA<0> 197 SA0 EVENT* 198 MEM_EVENT_L 27 45 46
OUT
7 =PPSPD_S0_MEM_B
199 VDDSPD SDA 200 =I2C_SODIMMB_SDA 48
BI
201 202 "Expansion" (bottom) slot
6 MEM_B_SA<1> SA1 SCL =I2C_SODIMMB_SCL IN 48
203 VTT VTT 204 =PP0V75_S0_MEM_VTT_B 7
MTG PINS
1 1 205 206
R3140 R3141 MTG PIN MTG PIN
1
C3140
A
207 208
2
2.2UF
20%
6.3V
CERM
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
209
211
MTG
MTG
PIN
PIN
MTG PIN
MTG PIN 210
212
1
C3150
1UF
10%
1
C3151
1UF
10%
1
C3152
1UF
10%
1
C3153
1UF
10%
SYNC_MASTER=K92_SUMA
PAGE TITLE
SYNC_DATE=06/23/2010 A
402-LF 2
402
2
402 MTG PIN MTG PIN 10V 10V 10V 10V
2 X5R
402
2 X5R
402
2 X5R
402
2 X5R
402 DDR3 SO-DIMM Connector B
DRAWING NUMBER SIZE
516S0806
SPD ADDR=0xA4(WR)/0xA5(RD) REVISION
R
3.0.0
31 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SD Card Connector
516-0225
CRITICAL
J3300
SD-CARD-K19-K24
CRITICAL F-RT-TH
L3300 3
VSS
47NH-1.3OHM 6
VSS
97 36 SDCONN_CLK R3379 33 1 2 5% 1/16W MF-LF 402 97 SDCONN_CLK_R 1 2 97 SDCONN_CLK_R_L 5
CLK
IN
SDCONN_CMD R3361 33 1 2 5% 1/16W MF-LF 402 SDCONN_CMD_R 0402 2
D
97 36
97 36
OUT
BI SDCONN_DATA<0> R3371
R3372
33 1 2 5% 1/16W MF-LF 402 97 SDCONN_R_DATA<0> 7
CMD
DAT0 D
97 36 BI SDCONN_DATA<1> 33 1 2 5% 1/16W MF-LF 402 97 SDCONN_R_DATA<1> 8
DAT1
97 36 BI SDCONN_DATA<2> R3373 33 1 2 5% 1/16W MF-LF 402 97 SDCONN_R_DATA<2> 9 DAT2
SDCONN_DATA<3> R3374 33 1 2 5% 1/16W MF-LF 402 97 SDCONN_R_DATA<3> 1
97 36 BI CD/DAT3
SDCONN_DATA<4> R3375 33 1 2 5% 1/16W MF-LF 402 97 SDCONN_R_DATA<4> 10
97 36 BI DAT4
97 36 SDCONN_DATA<5> R3376 33 1 2 5% 1/16W MF-LF 402 97 SDCONN_R_DATA<5> 11
DAT5
BI
97 36 SDCONN_DATA<6> R3377 33 1 2 5% 1/16W MF-LF 402 97 SDCONN_R_DATA<6> 12
DAT6
BI
97 36 BI SDCONN_DATA<7> R3378 33 1 2 5% 1/16W MF-LF 402 97 SDCONN_R_DATA<7> 13
DAT7 SD Not Inserted, CARD_DETECT is OPEN.
30 OUT SDCONN_CARDDETECT_L 14
CARD_DETECT_SW CAESAR-IV Card Detect is programmable,
15
CARD_DETECT_GND but a Silicon bug makes the active
36 OUT SDCONN_WP 16
WRITE_PROTECT_SW high case unusable.
30 =PP3V3_S0_SW_SD_PWR 4
VDD
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF 17
SHLD_PIN
Place near attr for series resistors: 1 C3373 1 C3375 1 C3377 1 C3379 1 C3381 1 C3371 1 C3370 18
SHLD_PIN
PLACE_NEAR=U3900.21:5MM 10PF 10PF 10PF 10PF 10PF 22PF 15PF 19
SHLD_PIN
5% 5% 5% 5% 5% 5% 5%
25V 25V 25V 25V 25V 50V 50V 20
PLACE_NEAR=U3900.26:5MM 2 CER 2 CER 2 CER 2 CER 2 CER 2 CERM 2 CERM SHLD_PIN
0201 0201 0201 0201 0201 402 402
PLACE_NEAR=U3900.25:5MM
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 C3372 1 C3374 1 C3376 1 C3378 1 C3380
10PF 10PF 10PF 10PF 10PF
PLACE_NEAR=U3900.54:5MM 5% 5% 5% 5% 5%
25V 25V 25V 25V 25V
2 CER 2 CER 2 CER 2 CER 2 CER
PLACE_NEAR=U3900.55:5MM 0201 0201 0201 0201 0201
C C
SD Detect & Reset Logic
SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit
Converts SDCONN from active-low level signal to active-high pulses.
7 =PP3V3_S4_SD_HPD Must STUFF R3312 and NOSTUFF R3314

when R3311 is NOT STUFFED.
R3314 and R3312 mutually exclusive
C3310 1
1
to bypass reset logic
1UF CRITICAL R3315
10
R3311 and R3310 mutually exclusive 10%
to control effect of =ENET_RESET_L 10V 2
VDD
10K
X5R 5%
402-1 1/16W
on DET_CHANGED# logic. MF-LF
U3311 2 402
SLG4AP026V
TDFN
R3314
36 24 IN ENET_LOW_PWR 2 LOW_PWR 0
RST RST_OUT* 4 SLG_ENET_RESET_OUT_L 1 2 ENET_RESET_L OUT 36 97
R3311 3 RST_IN* LOGIC
5%
0 1/16W
-> From PCH GPI0 24 IN =ENET_RESET_L 1 2 SLG_ENET_RESET_IN_L MF-LF
DET_CH_EN* 6 SD_DET_CH_EN_L 402
5%
1/16W 7 DET_IN
-> To SMC & to Isolation Circuit (then to PCH GPIO)
DLY (OD) 9 SDCONN_STATE_CHANGE_SMC
XOR
MF-LF (IPU) OUT 24 46
402 (Low active pulse signal)
DET_CHNGD*
-> From SD Conn 30 IN SDCONN_CARDDETECT_L (OD) 8 SDCONN_DETECT_L
XOR
OUT 36 -> To ENET Chip
(Low active) SD_DET_LVL_L 1
DET_OUT
B 1
R3310
10K
1
R3316
10K
DET_LVL
GND
THRM
PAD
1
R3317 1
R3312
B
5% 5% 10K 0
11
1/16W 1/16W 5% 5%
MF-LF MF-LF 1/16W 1/16W
2 402 2 402 MF-LF MF-LF
402 402
NOSTUFF 2 2 DLY block is 20ms nominal
NOSTUFF When ENET_LOW_PWR deasserts, RST_OUT#
deasserts for >80ms, then asserts for
10ms regardless ofmove RST_IN# state.
Otherwise RST_OUT# follows RST_IN#
SD Card 3.3V Overcurrent Protection

TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.
CRITICAL
U3300 =PP3V3_S0_SW_SD_PWR 30
TPS2065-1
2 DGN 6
IN0 OUT0
7 =PP3V3_S0_SDCARD 3 7
IN1 OUT1 PP3V3_S0_SW_SD_PWR
8 MAKE_BASE=TRUE
OUT2 MIN_LINE_WIDTH=0.4 mm
ENET_CR_PWREN 4 VOLTAGE=3.3V
36 EN 5 NOSTUFF
OC* CRITICAL
A CRITICAL THRM
1 C3302
10UF
1 C3303
0.1UF
1
R3300
47K =PP3V3_S0_PCH_GPIO
SYNC_MASTER=J31_YONAS SYNC_DATE=10/25/2011 A
1 C3300 1 C3301 GND PAD
20% 10% 5% 7 16 17 18 19
PAGE TITLE
10UF 0.1UF 353S3004 1/16W
6.3V 16V
SD Card Connector
1
20% 10% 2 X5R 2 X7R-CERM MF-LF

402
6.3V
2 X5R
16V
2 X7R-CERM
603 402 2 R33011 DRAWING NUMBER SIZE
603 402 10K
5%
1/16W Apple Inc. 051-9585 D
MF-LF REVISION
402 2 R
3.0.0
R3302 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SDCONN_OC_L_R 0
1 2 SDCONN_OC_L THE INFORMATION CONTAINED HEREIN IS THE
5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1/16W
MF-LF
402
33 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Must not enable more than two SO-DIMM margining
7 =PP3V3_S3_VREFMRGN
buffers at once or VRef source may be overloaded.
VREFDQ:LDO_DAC
OMIT
=PPVTT_S3_DDR_BUF R3403
R3418 68 7
200 PLACE_NEAR=J2900.1:2.54mm
1
SHORT
2 PP3V3_S3_VREFMRGN_DAC
10mA max load 1 2
MIN_LINE_WIDTH=0.3 mm CRITICAL 1%
NONE MIN_NECK_WIDTH=0.2 mm DDRVREF_DAC DDRVREF_DAC 1/16W
NONE VOLTAGE=3.3V MF-LF
NONE C3400 1 1 C3401 DDRVREF_DAC 402
PP0V75_S3_MEM_VREFDQ_A
402
2.2UF 0.1UF DDRVREF_DAC 27 31 93
20% 20% CRITICAL C3403 1
B1 U3402 MIN_LINE_WIDTH=0.3 mm
VREFDQ:LDO_DAC
D
6.3V
CERM
402-LF
2 2
10V
CERM
402
DDRVREF_DAC
U3400
0.1UF
20%
10V
CERM 2
A2
V+
MAX4253
UCSP
R3404
133
VOLTAGE=0.75V
D
8
402
A1 VREFMRGN_DQ_SODIMMA_BUF 1 2
VDD
A4 1% PLACE_NEAR=R3403.2:1mm
48 IN =I2C_VREFDACS_SCL 6 SCL
MSOP VOUTA 1 VREFMRGN_SODIMMA_DQ A3
V- 1/16W
MF-LF
B4 402
DAC5574
48 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_SODIMMB_DQ
9 A0 VOUTC 4 VREFMRGN_SODIMMS_CA
Addr=0x98(WR)/0x99(RD) 10 A1 VOUTD 5 VREFMRGN_MEMVREG_FBVREF VREFDQ:LDO_DAC
NOTE: MEMVREG and FRAMEBUF share R3405

GND 200 PLACE_NEAR=J3100.1:2.54mm
a DAC output, cannot enable DDRVREF_DAC 1 2
3
both at the same time! 1 CRITICAL
R3401 1%
1/16W
100K MF-LF
OMIT 5% 402
1/16W NC DDRVREF_DAC PP0V75_S3_MEM_VREFDQ_B 29 31 93
R3419 MF-LF VREFDQ:LDO_DAC MIN_LINE_WIDTH=0.3 mm
2 402 C2
B1 U3402 MIN_NECK_WIDTH=0.2 mm
SHORT MAX4253 R3406 VOLTAGE=0.75V
1 2 PP3V3_S3_VREFMRGN_CTRL V+ UCSP
MIN_LINE_WIDTH=0.3 mm C1
133
VREFMRGN_DQ_SODIMMB_BUF
Page Notes
NONE MIN_NECK_WIDTH=0.2 mm 1 2
NONE VOLTAGE=3.3V CRITICAL
NONE DDRVREF_DAC C3 C4
1% PLACE_NEAR=R3405.2:1mm
402 DDRVREF_DAC 1/16W
16
C3402 1 V- MF-LF
Power aliases required by this page: 0.1UF VCC
B4 402
- =PP3V3_S3_VREFMRGN 20%
NC
10V
2 U3401
- =PPVTT_S3_DDR_BUF CERM
402 PCA9557 VREFCA:LDO_DAC
- =PPDDR_S3_MEMVREF QFN
6
DDRVREF_DAC R3409
(OD) P0 NC 1
R3402 200 PLACE_NEAR=J2900.126:2.54mm
3 A0 P1 7 VREFMRGN_DQ_SODIMMA_EN 1 2
Signal aliases required by this page: 100K CRITICAL
Addr=0x30(WR)/0x31(RD) 4
A1 P2 9 VREFMRGN_DQ_SODIMMB_EN 5% 1%
- =I2C_VREFDACS_SCL 5 10 VREFMRGN_CA_SODIMMA_EN
1/16W 1/16W
A2 P3 MF-LF MF-LF
- =I2C_VREFDACS_SDA 11 VREFMRGN_CA_SODIMMB_EN 2 402
DDRVREF_DAC 402
PP0V75_S3_MEM_VREFCA_A
P4 DDRVREF_DAC 27 93
C -
-
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA =I2C_PCA9557D_SCL 1
P5
P6
12
13
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
C3404
0.1UF
20%
1
A2
B1
V+
U3403
MAX4253
VREFCA:LDO_DAC
R3410
VOLTAGE=0.75V
C
48 IN SCL 10V UCSP
CERM 2 133
BOM options provided by this page: 48 BI =I2C_PCA9557D_SDA 2
SDA P7 14
NC 402
A1 VREFMRGN_CA_SODIMMA_BUF 1 2
DDRVREF_DAC - Stuffs Apple margining circuit.

15 A3 A4 1% PLACE_NEAR=R3409.2:1mm
THRM RESET* V- 1/16W
VREFDQ:LDO - LDO outputs sent to DQ inputs. MF-LF
PAD GND B4 402
VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
17
8
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO_DAC
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO - LDO outputs sent to CA inputs. R3411
200 PLACE_NEAR=J3100.126:2.54mm
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs. 1 2
1%
24 IN PCA9557D_RESET_L DDRVREF_DAC CRITICAL 1/16W
MF-LF
1
RST* on ’platform reset’ so that system R3407 402
PP0V75_S3_MEM_VREFCA_B
100K NCDDRVREF_DAC VREFCA:LDO_DAC MIN_LINE_WIDTH=0.3 mm
29 93
watchdog will disable margining. 5%

C2
B1 U3403 MIN_NECK_WIDTH=0.2 mm
1/16W MAX4253 R3412 VOLTAGE=0.75V
MF-LF V+ UCSP
NOTE: Margining will be disabled across all 2 402 C1 VREFMRGN_CA_SODIMMB_BUF 1
133
2
soft-resets and sleep/wake cycles.
C4 1% PLACE_NEAR=R3411.2:1mm
31 7 =PPDDR_S3_MEMVREF C3
V- 1/16W
MF-LF
B4 402
CRITICAL PLACE_NEAR=Q3420.6:1mm NC
PLACE_NEAR=Q3420.6:2mm
VREFDQ:M1_M3 VREFDQ:M1_M3
VREFDQ:M1_M3
Q3420 1
R3421 DDRVREF_DAC
1
C3420 1
SSM6N15FEAPE 0.1UF 1K R3408
1% DDRVREF_DAC
MEMRESET_ISOL_LS5V_L 10% 100K
2
31 26 SOT563 1/16W CRITICAL

2
16V
MF-LF 5% C3405 1
G
X5R
402 2
402 1/16W
0.1UF DDRVREF_DAC
MF-LF DDRVREF_DAC
2 402
20%
10V C2
B1 U3404
2 MAX4253 R3414
S
PPCPU_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A CERM

V+
B
93 9 27 31 93 402 UCSP
33.2K
B
6
1
C1 VREFMRGN_MEMVREG_BUF 1 2 DDRREG_FB OUT 6 68

VREFDQ:M1_M3
C4 1%
1 C3
R3422 V- 1/16W
MF-LF
1K B4 402
PLACE_NEAR=R3421.2:1mm 1%
1/16W
MF-LF
2 402
NOTE: CPU DAC output step sizes:

DDR3 (1.5V) 7.70mV per step CRITICAL
=PPDDR_S3_MEMVREF
DDR3L (1.35V) 6.99mV per step VREFMRGN_FRAMEBUF_BUF
31 7 DDRVREF_DAC
DDRVREF_DAC 1
CRITICAL PLACE_NEAR=Q3420.3:1mm R3413 NCDDRVREF_DAC
VREFDQ:M1_M3 PLACE_NEAR=Q3420.3:2mm VREFDQ:M1_M3 R3416 1 100K B1 U3404 DDRVREF_DAC Required zero ohm resistors when no VREF margining circuit stuffed
0 A2
5% MAX4253
Q3420 VREFDQ:M1_M3 1
R3441 5% 1/16W V+ UCSP
1
R3417
1/16W MF-LF PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SSM6N15FEAPE 1 C3440 1K MF-LF
2
402 A1 0
1% 402 5%
MEMRESET_ISOL_LS5V_L 0.1UF 2
5
31 26 SOT563 10% 1/16W A3 A4 1/16W 116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3403,R3405 VREFDQ:LDO

MF-LF MF-LF
G
2
16V
402
V- 402
X5R 2 2
402
B4 116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3409,R3411 VREFCA:LDO
VREFMRGN_MEMVREG_FBVREF_R
NC VREFMRGN_FRAMEBUF_BUF_R
S
93 9 PPCPU_MEM_VREFDQ_B PP0V75_S3_MEM_VREFDQ_B 29 31 93
3
4
VREFDQ:M1_M3 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
1
R3442 DDRVREF_DAC
1
114S0218 4 RES,MTL FILM,1K,1%,0402,SM,LF R3421,R3422,R3441,R3442 VREFDQ:M1_DAC
1K R3415
1%
PLACE_NEAR=R3441.2:1mm 1/16W 100K 114S0171 2 RES,MTL FILM,332,1%,0402,SM,LF R3404,R3406 VREFDQ:M1_DAC
MF-LF 5%
402 1/16W
2
MF-LF
402
2
A MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef)
SYNC_MASTER=J31_ANNE SYNC_DATE=06/09/2011 A
PAGE TITLE
DAC Channel: A B C C D D
DDR3/FRAMEBUF VREF MARGINING
DRAWING NUMBER SIZE
PCA9557D Pin: 1 2 3 4 5 6
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) R
3.0.0
Margined target: 0.300V - 1.200V (+/- 450mV) 1.000V - 2.000V (+/- 500mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.000V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF) PROPRIETARY PROPERTY OF APPLE INC.
VRef current: +3.4mA - -3.4mA (- = sourced) +61uA - -61uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
34 OF 132
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C3531
1 2 0.1UF PCIE_AP_R2D_C_P IN 16 96
1 2 10% 16V PCIE_AP_R2D_C_N IN 16 96
10% 16V 0201 X5R-CERM 0201
X5R-CERM
0.1UF C3530
D D
R3510
0 3V S3 WLAN FET
1 2 PCIE_AP_D2R_P OUT 16 96
5% 1/20W MF 201
R3511 PCIE_AP_D2R_N OUT 16 96
0 MOSFET TPCP8102
1 2
5% 1/20W MF 201
CHANNEL P-TYPE
RDS(ON) 20-30 MOHM @2.5V
LOADING 1 A (EDP)
CRITICAL
Q3550
WIFI_EVENT_L OUT 6 45 46 DMP2018LFK
DFN2563-6
155S0367
L3504 MIN_LINE_WIDTH=1 mm
2
D
XW3552
S
FERR-120-OHM-3A SM MIN_LINE_WIDTH=1 mm
1
PCIE_AP_R2D_P PP3V3_WLAN PP3V3_WLAN_F
4
96 6 46 6 32 MIN_NECK_WIDTH=0.5 mm
1 2 2 1 =PP3V3_S3_WLAN 7 32
MIN_LINE_WIDTH=1 mm
0603
G
PP3V3_WLAN_R
1
C PCIE_AP_R2D_N C3522 1
C3521 1
C3551 1 R3551
C
3
96 6
10K
0.1uF 0.1uF 0.033UF
5%
516S0582 20%
10V
20%
10V
10%
16V
1/16W
2 2 2 MF-LF
CERM CERM C3550 X5R
CRITICAL 402 402

0.1UF
402 R3550 2
402
PLACE_NEAR=J3501.29:2.54MM PLACE_NEAR=J3501.29:2.54MM 33K

J3501 96 PCIE_AP_D2R_R_P 1 2 P3V3WLAN_SS 1 2 PM_WLAN_EN_L IN 74
CRITICAL
500913-0302
F-ST-SM
96 PCIE_AP_D2R_R_N
L3501
330-OHM-80MA
AIRPORT 10%
16V
X5R
5%
1/16W
MF-LF
402
32 31 DLP11S 402-1
SYM_VER-1
4 3 PCIE_CLK100M_AP_P IN 16 96
2 1
4 3 101 6 PCIE_CLK100M_AP_CONN_P
6 5 101 6 PCIE_CLK100M_AP_CONN_N 1 2 PCIE_CLK100M_AP_N IN 16 96
8 7 PLACE_NEAR=J3501.11:2.54mm
10 9
BTPWR:S4
AP_TEMP_SMB_SCL_PD 12 11
=PP3V3_S4_BT 7 32 CRITICAL =BT_WAKE_L OUT 46
AP_TEMP_SMB_SDA_PD 14 13
Q3510
1
R3520 16 15
5%
51 18
20
17
19
BLUETOOTH 1
NOSTUFF
R3517
BTPWR:S3
R3518 1 1 C3510 1
BTPWR:S4
R3514
D 3 SSM3K15AMFVAPE
1/16W 0.1UF
MF-LF 15K 0 15K VESM
2 402
22 21 95 6 USB_BT_CONN_P 1% 5%
10%
1%
9
6.3V
1/20W 1/20W 2 X5R 1/20W
24 23 95 6 USB_BT_CONN_N MF MF VCC MF
R3521 1
26 25 29 2 201
201 2
201
2 201
1 G S 2
51 28 27 PP3V3_S3RS4_BT_F
1
Y+ M+ 5 USB_BT_WAKEP
5% 6
1/16W 30 MIN_NECK_WIDTH=0.2 mm L3505 BTPWR:S4 2
Y- U3510 M- 4 USB_BT_WAKEN
MF-LF MIN_LINE_WIDTH=0.5 mm
402 2 1
C3532 2 1 =PP3V3_S4_BT
NOSTUFF1 1
NOSTUFF PI3USB102ZLE BTPWR:S4 NOSTUFF
0.01UF 7 32 R3515 R3516 TQFN
D+ 7 USB_BT_N 1 1
34 33 10%
FERR-120-OHM-1.5A 15K 15K CRITICAL
BI 8 95 R3512 R3513
16V 6 USB_BT_P
2 CERM 1% 1% D- BI 8 95 15K 15K
0402-LF
B 402
2
1/20W
MF
201
2
1/20W
MF
201
10 SEL OE* 8
2
1%
1/20W
MF
201
2
1%
1/20W
MF
201
Supervisor & CLKFREG # ISolation B
BTPWR:S4 GND Delay = 60 ms +/- 20%
3
R3519
0 PP3V3_WLAN_F =PP3V3_S3_WLAN
74 45 26 17 IN PM_SLP_S4_L 1 2 BTMUX_SEL 32 7 32
5%
1/20W NOSTUFF SEL OUTPUT
MF CRITICAL
1
201 C3511 1 1
R3553
1
R3554
0.01UF L USB_BT_WAKE VDD
10%
100K 232K 1
C3540
10V H USB_BT 1% 1%
U3540 0.1uF
X5R 2 1/16W 1/16W
MF-LF MF-LF 20%
201 SLG4AP016V 10V
2 402 2 402 2 CERM
TDFN 402
P3V3WLAN_VMON
2 SENSE +
PCIE_WAKE_L 6 17 24
0.7V -
OUT
518S0815 DLY
6 AP_RESET_CONN_L
4 RESET* AP_RESET_L
CRITICAL MR* 3
IN 24
J3502 AP_PWR_EN
819Q-3506-K281 EN 6
IN 18 23 74
F-RT-SM1
6 AP_CLKREQ_Q_L OUT 8
OUT 16
8 7 IN (OD)
AP_CLKREQ_L
THRM
6
6 PP5V_S3_ALSCAMERA_F 1
PAD GND
MIN_LINE_WIDTH=0.5 mm R3555
5
5
=I2C_ALS_SCL IN 48 MIN_NECK_WIDTH=0.2 mm
275 mA peak 100K
4
=I2C_ALS_SDA BI 48 1%
206 mA nominal max 1/16W
USB_CAMERA_CONN_P
ALS
95 6 MF-LF
3
2 402
A 2
1
95 6 USB_CAMERA_CONN_N
PLACE_NEAR=J3502.6:2.54MM SYNC_MASTER=J30_MLB SYNC_DATE=11/11/2011 A
PAGE TITLE
7
CRITICAL
L3507
CAMERA L3508
FERR-120-OHM-1.5A X19/ALS/CAMERA CONNECTOR
DRAWING NUMBER SIZE
90-OHM 2 1 =PP5V_S3_ALSCAMERA
DLP0NS
SYM_VER-1 0402-LF
7

4 3 REVISION
USB_CAMERA_P BI 18 95
1
C3552
R
3.0.0
0.1uF NOTICE OF PROPRIETARY PROPERTY: BRANCH
20%
1 2 USB_CAMERA_N 10V
BI 18 95 2 CERM THE INFORMATION CONTAINED HEREIN IS THE
402 PROPRIETARY PROPERTY OF APPLE INC.
PLACE_NEAR=J3502.2:2.54MM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
35 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
OMIT_TABLE
96 8 IN PCIE_TBT_R2D_C_P<0> C3600 1 2
V19 V21
C3640 1 2 PCIE_TBT_D2R_P<0> OUT 8 96
10% 6.3V X5R 201 96 PCIE_TBT_R2D_P<0> PER_0_P U3600 PET_0_P 96 PCIE_TBT_D2R_C_P<0> 10% 6.3V X5R 201
0.1UF T19 T21
0.1UF
96 PCIE_TBT_R2D_N<0> PER_0_N T29 PET_0_N 96 PCIE_TBT_D2R_C_N<0>
96 8 IN PCIE_TBT_R2D_C_N<0> C3601 1 2 C3641 1 2 PCIE_TBT_D2R_N<0> OUT 8 96
10% 6.3V X5R 201 FCBGA 10% 6.3V X5R 201
0.1UF 0.1UF
(SYM 1 OF 2)
96 8 IN PCIE_TBT_R2D_C_P<1> C3602 1 2 C3642 1 2 PCIE_TBT_D2R_P<1> OUT 8 96
PCIE GEN2
PCIE_TBT_R2D_P<1> P19 P21 PCIE_TBT_D2R_C_P<1>
10% 6.3V X5R 201 96 PER_1_P PET_1_P 96 10% 6.3V X5R 201
0.1UF M19 M21
0.1UF
96 PCIE_TBT_R2D_N<1> PER_1_N PET_1_N 96 PCIE_TBT_D2R_C_N<1>
C3603 C3643
RECEIVE
TRANSMIT
96 8 IN PCIE_TBT_R2D_C_N<1> 1 2 1 2 PCIE_TBT_D2R_N<1> OUT 8 96
10% 6.3V X5R 201 10% 6.3V X5R 201
0.1UF 0.1UF
96 8 IN PCIE_TBT_R2D_C_P<2> C3604 1 2
K19 K21
C3644 1 2 PCIE_TBT_D2R_P<2> OUT 8 96
PCIE_TBT_R2D_P<2> PER_2_P PET_2_P PCIE_TBT_D2R_C_P<2>
D
10% 6.3V X5R 201 96 96 10% 6.3V X5R 201
0.1UF 0.1UF
D 96 8 IN PCIE_TBT_R2D_C_N<2> C3605 1 2
10% 6.3V X5R 201

96 PCIE_TBT_R2D_N<2> H19
PER_2_N PET_2_N H21 96 PCIE_TBT_D2R_C_N<2>
C3645 1 2
10%
PCIE_TBT_D2R_N<2>
6.3V X5R 201
OUT 8 96
0.1UF 0.1UF
96 8 IN PCIE_TBT_R2D_C_P<3> C3606 1 2
F19 F21
C3646 1 2
PCIE_TBT_D2R_P<3> OUT 8 96
10% 6.3V X5R 201 96 PCIE_TBT_R2D_P<3> PER_3_P PET_3_P 96 PCIE_TBT_D2R_C_P<3> 10% 6.3V X5R 201
0.1UF D19 D21
0.1UF
96 PCIE_TBT_R2D_N<3> PER_3_N PET_3_N 96 PCIE_TBT_D2R_C_N<3>
96 8 IN PCIE_TBT_R2D_C_N<3> C3607 1 2 C3647 1 2 PCIE_TBT_D2R_N<3> OUT 8 96
10% 6.3V X5R 201 10% 6.3V X5R 201
0.1UF 0.1UF
B21
=PP3V3_TBT_RTR 7 33 34 35
TP_TBT_MONDC0 MONDC0
6
WAKE* F1 TBT_PCIE_WAKE_L R3651 2 1
5% 1/16W MF-LF 402
10K
TP_TBT_MONDC1 A20
6 MONDC1 E6
PERST* TBT_RESET_L IN 35
DEBUG: For monitoring current/voltage
E14 TBT_RSENSE
K17 RSENSE
6 TP_TBT_MONOBSP MONOBSP
6 TP_TBT_MONOBSN M17
MONOBSN R3655 1
1K
DEBUG: For monitoring clock 1%
35 34 33 7 =PP3V3_TBT_RTR 1/16W
MF-LF
402
2
E16 TBT_RBIAS
RBIAS
1 1
C3690 1
R3692 1 R3623 1 1
R3622 1
R3621
R3690 R3691 1UF 3.3K 10K 10K 10K
3.3K 3.3K 10%
5% 5% 5% 5%
POWER ON RESET
6.3V
5% 5% CERM 2 1/16W 1/16W 1/16W 1/16W Not used in host mode.
1/16W 1/16W 402 CRITICAL MF-LF MF-LF MF-LF MF-LF K1
MF-LF MF-LF 402 402 402 402 PCIE_RST_0* TP_TBT_PCIE_RESET0_L 6
2 2 2 2
402 2 2 402 OMIT_TABLE
CLK REQUEST
8 J2
P3 PCIE_RST_1* TP_TBT_PCIE_RESET1_L 6
VCC 35 OUT =TBT_CLKREQ_L PCIE_CLKREQ_0* K3
N4 PCIE_RST_2* TP_TBT_PCIE_RESET2_L 6
1
R3693 TBT_GPIO<1> PCIE_CLKREQ_1* J4
(TBT_SPI_MOSI) 5 D U3690 Q 2 (TBT_SPI_MISO) M3 PCIE_RST_3* TP_TBT_PCIE_RESET3_L 6
3.3K TBT_GPIO<2> PCIE_CLKREQ_2*
C (TBT_SPI_CLK) 6 C
M95320-RMB6TG
MLP
5%
1/16W TBT_RSVD L4
PCIE_CLKREQ_3* TDI T3 JTAG_TBT_TDI IN 8 19
=PP3V3_TBT_RTR C
MISC
MF-LF R4 7 33 34 35
JTAG_TBT_TMS
JTAG
2 402 P1 TMS IN 16
(TBT_SPI_CS_L) 1 S_L 98 TBT_SPI_MOSI EE_DI R2
TCK JTAG_TBT_TCK
EEPROM
M1 IN 8
98 TBT_SPI_MISO EE_DO T1
1
R3698
TBTROM_WP_L 3 W_L N2 TDO JTAG_TBT_TDO OUT 8
98 TBT_SPI_CS_L EE_CS* 10K
L2 5%
TBTROM_HOLD_L 7 HOLD_L 98 TBT_SPI_CLK EE_CLK REFCLK_100_IN_P H17 PCIE_CLK100M_TBT_P IN 16 96 1/16W
G16 MF-LF
VSS THM A2 REFCLK_100_IN_N PCIE_CLK100M_TBT_N IN 16 96 402
R3695
PAD TP_TBT_THERM_DP THERM_DP 2
806
CLOCKS
Use B1 GND ball for THERM_DN P17
4 9
E4 XTAL_25_IN SYSCLK_CLK25M_TBT_R 1 2 SYSCLK_CLK25M_TBT IN 24
TBT_TEST_EN TEST_EN
TEST PORT
R16 TP_TBT_XTAL25OUT
P5 XTAL_25_OUT 1%
TP_TBT_TEST_POINT_0 TEST_POINT_0 1/16W
1 TP_TBT_TEST_POINT_1 N6
TEST_POINT_1 TMU_CLK_OUT U2 TBT_TMU_CLK_OUT R3696 1 MF-LF
R3625 1K
402
TP_TBT_TEST_POINT_2 M5 E2 TBT_TMU_CLK_IN
0 TEST_POINT_2 TMU_CLK_IN 5%
5% L6 1/16W
1/16W TBT_TEST_POINT_3 TEST_POINT_3 NO STUFF MF-LF
MF-LF 402 2
2
402 R3699 1
10K
5%
AA4 1/16W
R3629 1 98 33 6 DP_TBTSNK0_ML_P<3> DPSNK0_ML_LANE_3P MF-LF
Y3 402
0 98 33 6 DP_TBTSNK0_ML_N<3> DPSNK0_ML_LANE_3N 2
SNK0 AC Coupling 5%
1/16W AA6
MF-LF 98 33 6 DP_TBTSNK0_ML_P<2> DPSNK0_ML_LANE_2P
98 81 6 IN DP_TBTSNK0_ML_C_P<0> C3620 1 2 DP_TBTSNK0_ML_P<0> 6 33 98 402 2 Y5
10% 16V 98 33 6 DP_TBTSNK0_ML_N<2> DPSNK0_ML_LANE_2N
SINK PORT 0
0.1uF X5R 402
98 81 6 IN DP_TBTSNK0_ML_C_N<0> C3621 1 2 DP_TBTSNK0_ML_N<0> 6 33 98 98 33 6 DP_TBTSNK0_ML_P<1> AA8

DPSNK0_ML_LANE_1P
10% 16V Y7 AA18
0.1uF X5R 402 98 33 6 DP_TBTSNK0_ML_N<1> DPSNK0_ML_LANE_1N DPSRC0_ML_LANE_3P TP_DP_TBTSRC_ML_CP<3> 6
Y17 TP_DP_TBTSRC_ML_CN<3>
DPSRC0_ML_LANE_3N 6
98 81 6 IN DP_TBTSNK0_ML_C_P<1> C3622 1 2 DP_TBTSNK0_ML_P<1> 6 33 98 98 33 6 DP_TBTSNK0_ML_P<0> AA10
DPSNK0_ML_LANE_0P
10% 16V Y9 AA16
0.1uF X5R 402 98 33 6 DP_TBTSNK0_ML_N<0> DPSNK0_ML_LANE_0N DPSRC0_ML_LANE_2P TP_DP_TBTSRC_ML_CP<2> 6
98 81 6 IN DP_TBTSNK0_ML_C_N<1> C3623 1 2 DP_TBTSNK0_ML_N<1> 6 33 98 V1 DPSRC0_ML_LANE_2N Y15 TP_DP_TBTSRC_ML_CN<2> 6

DP_TBTSNK0_AUXCH_P DPSNK0_AUX_CHP
SOURCE PORT 0
10% 16V 98 33 6
0.1uF
B
X5R 402
98 33 6 DP_TBTSNK0_AUXCH_N W2
DPSNK0_AUX_CHN DPSRC0_ML_LANE_1P AA14 TP_DP_TBTSRC_ML_CP<1> 6
B
DISPLAY
98 81 6 IN DP_TBTSNK0_ML_C_P<2> C3624 1 2 DP_TBTSNK0_ML_P<2> 6 33 98 V5 DPSRC0_ML_LANE_1N Y13 TP_DP_TBTSRC_ML_CN<1> 6
10% 16V 86 82 OUT DP_TBTSNK0_HPD DPSNK0_HOT_PLUG_DET
0.1uF X5R 402 AA12
DPSRC0_ML_LANE_0P TP_DP_TBTSRC_ML_CP<0> 6
98 81 6 IN DP_TBTSNK0_ML_C_N<2> C3625 1 2 DP_TBTSNK0_ML_N<2> 6 33 98 Y11
10% 16V R3630 1 DPSRC0_ML_LANE_0N TP_DP_TBTSRC_ML_CN<0> 6
0.1uF X5R 402 V9
100K 98 33 6 DP_TBTSNK1_ML_P<3> DPSNK1_ML_LANE_3P W16
5% DPSRC0_AUX_CHP TP_DP_TBTSRC_AUXCH_CP 6
98 81 6 IN DP_TBTSNK0_ML_C_P<3> C3626 1 2
DP_TBTSNK0_ML_P<3> 6 33 98 1/16W 98 33 6 DP_TBTSNK1_ML_N<3> U8
DPSNK1_ML_LANE_3N U16
10% 16V MF-LF DPSRC0_AUX_CHN TP_DP_TBTSRC_AUXCH_CN 6
0.1uF X5R 402 402 V11 100pF SRF > 40MHz
2
98 33 6 DP_TBTSNK1_ML_P<2> DPSNK1_ML_LANE_2P
98 81 6 IN DP_TBTSNK0_ML_C_N<3> C3627 1 2 DP_TBTSNK0_ML_N<3> 6 33 98 U10 DPSRC0_HOT_PLUG_DET V3 DP_TBTSRC_HPD
10% 16V 98 33 6 DP_TBTSNK1_ML_N<2> DPSNK1_ML_LANE_2N BYPASS=U3600.Y19::2mm
SINK PORT 1
0.1uF X5R 402
V13 Y19 BYPASS=U3600.Y19::5.08mm
98 33 6 DP_TBTSNK1_ML_P<1> DPSNK1_ML_LANE_1P DP_ATEST TBT_DP_ATEST
98 81 6 BI DP_TBTSNK0_AUXCH_C_P C3628 1 2 DP_TBTSNK0_AUXCH_P 6 33 98 98 33 6 DP_TBTSNK1_ML_N<1> U12
DPSNK1_ML_LANE_1N DP_RES_0 Y21
10% 16V
0.1uF X5R 402
DP_TBTSNK1_ML_P<0> V15 DP_RES_1 AA20 TBT_DP_RES C3685 1 1
C3686
98 33 6 DPSNK1_ML_LANE_0P
98 81 6 BI DP_TBTSNK0_AUXCH_C_N C3629 1 2 DP_TBTSNK0_AUXCH_N 6 33 98
U14
100PF 0.01UF
10% 16V 98 33 6 DP_TBTSNK1_ML_N<0> DPSNK1_ML_LANE_0N 5%
50V
10%
16V
0.1uF X5R 402 R3685 1 1
R3632 CERM 2 2 CERM
DP_TBTSNK1_AUXCH_P V7 402 402
98 33 6 DPSNK1_AUX_CHP 14.0K 100K
1% 5%
SNK1 AC Coupling 98 33 6 DP_TBTSNK1_AUXCH_N U6
DPSNK1_AUX_CHN 1/16W 1/16W
MF-LF MF-LF
402 402
98 81 6 IN DP_TBTSNK1_ML_C_P<0> C3630 1 2 DP_TBTSNK1_ML_P<0> 6 33 98 86 82 OUT DP_TBTSNK1_HPD U4
DPSNK1_HOT_PLUG_DET 2 2
10% 16V
0.1uF X5R 402
98 81 6 IN DP_TBTSNK1_ML_C_N<0> C3631 1 2 DP_TBTSNK1_ML_N<0> 6 33 98 R3631 1

10% 16V
0.1uF X5R 402 100K A6 A14
5% 98 87 6 OUT TBT_R2D_C_P<0> PRT0_T29T_P PRT2_T29T_P TBT_R2D_C_P<2> OUT 8 98
1/16W
98 81 6 IN DP_TBTSNK1_ML_C_P<1> C3632 1 2 DP_TBTSNK1_ML_P<1> 6 33 98 MF-LF 98 87 6 OUT TBT_R2D_C_N<0> A4
PRT0_T29T_N PRT2_T29T_N A12 TBT_R2D_C_N<2> OUT 8 98
10% 16V 402
PORT2
0.1uF 2
X5R 402
PORT0
TBT_D2R_P<0> C4 C12 TBT_D2R_P<2>

98 87 IN PRT0_T29R_P PRT2_T29R_P IN 8 98
C3633
PORTS
98 81 6 IN DP_TBTSNK1_ML_C_N<1> 1 2 DP_TBTSNK1_ML_N<1> 6 33 98
C2 C10
10% 16V 98 87 IN TBT_D2R_N<0> PRT0_T29R_N PRT2_T29R_N TBT_D2R_N<2> IN 8 98
0.1uF X5R 402
A TBT_LSEO<0> J6 G4 TBT_LSEO<2>
T29_0_LSEO T29_2_LSEO
98 81 6 IN DP_TBTSNK1_ML_C_P<2> C3634
0.1uF
1 2
10%
X5R
16V
402
DP_TBTSNK1_ML_P<2> 6 33 98
87
87
OUT
IN TBT_LSOE<0> K5
T29_0_LSOE T29_2_LSOE H3 TBT_LSOE<2>
OUT
IN
8
8 SYNC_MASTER=T29_REF
PAGE TITLE
DP_TBTSNK1_ML_C_N<2> C3635 1 2 DP_TBTSNK1_ML_N<2>
98 81 6 IN
0.1uF
10%
X5R
16V
402
6 33 98
98 87 6 OUT TBT_R2D_C_P<1> A10
PRT1_T29T_P PRT3_T29T_P A18 TBT_R2D_C_P<3> OUT 8 98 Thunderbolt Host (1 of 2)
TBT_R2D_C_N<1> A8 A16 TBT_R2D_C_N<3>
98 87 6 OUT PRT1_T29T_N PRT3_T29T_N OUT 8 98 DRAWING NUMBER SIZE
98 81 6 DP_TBTSNK1_ML_C_P<3> C3636 1 2
DP_TBTSNK1_ML_P<3> 6 33 98
PORT1
PORT3
IN TBT_D2R_P<1> C8 C16 TBT_D2R_P<3>

10% 16V 98 87 IN PRT1_T29R_P PRT3_T29R_P IN 8 98
0.1uF X5R 402 C6 C14 REVISION
TBT_D2R_N<1> PRT1_T29R_N PRT3_T29R_N TBT_D2R_N<3>
98 81 6 IN DP_TBTSNK1_ML_C_N<3> C3637 1 2
10% 16V
DP_TBTSNK1_ML_N<3> 6 33 98
98 87 IN IN 8 98 R
3.0.0
0.1uF X5R 402 87 OUT TBT_LSEO<1> G6
T29_1_LSEO T29_3_LSEO G2 TBT_LSEO<3> OUT 8 NOTICE OF PROPRIETARY PROPERTY: BRANCH
TBT_LSOE<1> H5 H1 TBT_LSOE<3>
87 IN T29_1_LSOE T29_3_LSOE IN 8 THE INFORMATION CONTAINED HEREIN IS THE
98 81 6 BI DP_TBTSNK1_AUXCH_C_P C3638 1 2 DP_TBTSNK1_AUXCH_P 6 33 98 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
0.1uF
10%
X5R
16V
402 98 48 BI I2C_TBT_SDA F3
T29_SDA NOTE: All unused LSOE/EO pairs should be aliased I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
36 OF 132
98 81 6 BI DP_TBTSNK1_AUXCH_C_N C3639 1 2 DP_TBTSNK1_AUXCH_N 6 33 98 98 48 OUT I2C_TBT_SCL F5
T29_SCL together. Other signals okay to float (TP/NC). III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
0.1uF
10%
X5R
16V
402 IV ALL RIGHTS RESERVED 33 OF 105
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D CRITICAL
=PP3V3_TBT_RTR 7 33 35 D
135 mA (Single-Port)
104 7 =PP1V05_TBT_RTR OMIT_TABLE 152 mA (Dual-Port)
2100 mA (Single Port) H9
VCC1P0 U3600 VCC3P3 H7
C3744 1
C3743 1
C3745 1 1
C3746 1
C3747 EDP: 200 mA
2250 mA (Dual Port) H11
VCC1P0 VCC3P3 M7 1UF 1UF 1UF 10UF 10UF
T29 10% 10% 10% 20% 20%
EDP: 3000 mA C3700 1 1
C3705 1
C3706 1
C3707 1
C3708 1
C3709 H13
VCC1P0 FCBGA VCC3P3 K7 6.3V
CERM 2
6.3V
CERM 2
6.3V
CERM 2 2
6.3V
X5R 2
6.3V
X5R
10UF 1UF 1UF 1UF 1UF 1UF K9
VCC1P0 (SYM 2 OF 2) 402 402 402 603 603
20% 10% 10% 10% 10% 10% G10
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V K11 VCC3P3_T29
X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM VCC1P0 G12
603 402 402 402 402 402 K13 VCC3P3_T29
VCC1P0
M9
VCC1P0
M11
VCC1P0 P7
M13 VCC3P3_DP_RX1
VCC1P0 R6
VCC3P3_DP_RX1
C3701 1 1
C3710 1
C3711 1
C3712 1
C3713 1
C3714
10UF 1UF 1UF 1UF 1UF 1UF
H15
VCC1P0_PE P9 C3753 1
C3752 1
C3751 1
C3750 1
VCC3P3_DP_TXRX
VCC
20% 10% 10% 10% 10% 10% K15
VCC1P0_PE 1UF 1UF 1UF 1UF
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V P11 10% 10% 10% 10%
X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM M15 VCC3P3_DP_TXRX 6.3V 6.3V 6.3V 6.3V
603 402 402 402 402 402 VCC1P0_PE CERM 2 CERM 2 CERM 2 CERM 2
E8 402 402 402 402
VCC1P0_PE
E10
VCC1P0_PE
E12
VCC1P0_PE
G14
VCC1P0_PE
R8 P13
VDD1P0_DP_RX1 VDD3P3DP_PLL
R10
VDD1P0_DP_TXRX
1 C3720 1 C3721 1 C3722 R12
VDD1P0_DP_TXRX C3760 1
1UF 1UF 1UF 1UF
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM CERM 2
402 402 402 402
C L3730 L3770
C
FERR-120-OHM-1.5A FERR-120-OHM-1.5A
1 2 PP1V05_TBT_VDD_DPPLL R14 P15 PP3V3_TBT_DPBIAS 1 2
VDD1P0_DP_PLL VCC3P3_DP_TXRXBIAS
MIN_LINE_WIDTH=0.4 mm MIN_LINE_WIDTH=0.4 mm
0402 MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 0402
VOLTAGE=1.05V VOLTAGE=3.3V
1
C3730 C3770 1
2.2UF G8
VSS VSSDP T5 2.2UF
20% 20%
6.3V J8 T7 6.3V
2 CERM VSS VSSDP CERM 2
402-LF J10 T9 402-LF
VSS VSSDP
J12 T11
VSS VSSDP
J14 T15
VSS VSSDP
L8 T17
VSS VSSDP
L10 V17
VSS VSSDP
L12 W4
VSS VSSDP
L14 W6
VSS VSSDP
N8 W8
VSS VSSDP
N10 W10
VSS VSSDP
N12 W12
VSS VSSDP
N14 W14
VSS VSSDP
Y1
VSSDP
AA2
VSSDP
B1
VSSPE T13
B3 VSSDP_PLL
VSSPE
GND
B5 F9
VSSPE VSSPE
B7 F11
VSSPE VSSPE
B9 F13
VSSPE VSSPE
B B11
B13
VSSPE
VSSPE
VSSPE
VSSPE
F15
F17
B
B15 G18
VSSPE VSSPE
B17 G20
VSSPE VSSPE
B19 J16
VSSPE VSSPE
C18 J18
VSSPE VSSPE
C20 J20
VSSPE VSSPE
D1 L16
VSSPE VSSPE
D3 L18
VSSPE VSSPE
D5 L20
VSSPE VSSPE
D7 N16
VSSPE VSSPE
D9 N18
VSSPE VSSPE
D11 N20
VSSPE VSSPE
D13 R18
VSSPE VSSPE
D15 R20
VSSPE VSSPE
D17 U18
VSSPE VSSPE
E18 U20
VSSPE VSSPE
E20 W18
VSSPE VSSPE
F7 W20
VSSPE VSSPE
A SYNC_MASTER=T29_REF SYNC_DATE=06/14/2011 A
PAGE TITLE
Thunderbolt Host (2 of 2)
DRAWING NUMBER SIZE

REVISION
R
3.0.0
37 OF 132
Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes SI8409DB:
Power aliases required by this page: CRITICAL

Vds(max):
Vgs(max):
-30V
+/-12V
Thunderbolt 15V Boost Regulator
- =PPVIN_SW_TBTBST (8-13V Boost Input) TBTBST:Y CRITICAL
Vgs(th): -1.4V
- =PP15V_TBT_REG (15V Boost Output) Q3880 TBTBST:Y
Rds(on): 46mOhm @ 4.5V Vgs
- =PP3V3_S0_P3V3TBTFET (3.3V FET Input)
=PPVIN_SW_TBTBST
SI8409DB L3895
8 7 BGA Id(max): 3.7A @ 70C 10UH-4A-68-MOHM
- =PP3V3_TBT_FET (3.3V FET Output)
8-13V Input 1 2
- =PP3V3_S0_TBTPWRCTL PPVIN_SW_TBTBST TBTBST_BOOST
3
7
Changes required MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
D
- =PP1V05_S0_P1V05TBTFET (1.05V FET Input) PCMB063T-100MS
4
TBTBST:Y TBTBST:Y
2
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
for 2S. SWITCH_NODE=TRUE CRITICAL
- =PP1V05_TBT_FET (1.05V FET Output) TBTBST:Y Voltage not specified here, C3890 1
C3891 1
DIDT=TRUE TBTBST_SNS1
TBTBST:Y add property on another page.
10UF 10UF TBTBST:Y
R3880 1
A
TBTBST:Y
D3895
G
Signal aliases required by this page: 1
C3880 TBTBST:Y 10%
25V
10%
25V 1
470K
D - =TBT_CLKREQ_L 5%
1/16W
0.1UF
10% R3891 1
X5R
805
2 X5R
805
2 R3889
0
POWERDI-123
DFLS230L D
1
25V
27
20
21
38
- =TBT_RESET_L MF-LF 2 X5R
200K 5% K
402 402 1% 1/16W
2
1/16W VIN MF-LF
BOM options provided by this page: MF-LF SW 402 2
TBTBST_PWREN_DIV_L 402 CRITICAL
TBTBST:Y - Stuffs 15V boost circuitry. 2 TBTBST_SNS2
TBTBST:Y <R1> TBTBST:Y
TBTBST_EN_UVLO 25 EN/UVLO SNS1 6 TBTBST:Y
1
R3881 U3890 XW3895
330K SNS2 3 R3890
5%
LT3957 49.9K
SM
1/16W TBTBST_INTVCC 28 INTVCC QFN TBTBST_VSNS_RC 2 1 TBTBST_VSNS 2 1 PLACE_NEAR=C3895.1:2 mm

MF-LF
402 1%
2 1/16W
1 MF-LF
TBTBST_PWREN_L TBTBST_VC 30 VC 402
2 TBTBST:Y
TBTBST:Y
TBTBST:Y TBTBST:Y NC 10
NC TBTBST:Y R3895 1
TBTBST:Y D 3
C3892 1 1
C3887 R3893 1 TBTBST_RT 33 RT 35 1
C3888 137K
10K =PP15V_TBT_REG
Q3805 4.7UF 47PF 1% 36 22PF 1%
1/16W
7 8
10% 5% 5%
SSM3K15FV 1/16W MF-LF
10V
X5R 2 2
50V
CERM MF-LF
TBTBST_SS 32
2
50V
CERM 402
2
Vout = 15.47V
SOD-VESM-HF 402 SS TBTBST:Y TBTBST:Y
805 402 2 402
<Ra> 1
C3897 Max Current = 1A
1 G S 2
TBTBST_VC_RC FBX 31 TBTBST_FBX 1
C3895 4.7UF
TBTBST:Y TBTBST:Y 34
SYNC TBTBST:Y 4.7UF 10%
Freq = 300KHz
TBT_A_HV_EN 10% 50V
88 87 IN 1
TBTBST:Y 1
TBTBST:Y NO STUFF 1 50V 2 X7R-CERM
R3892 1
C3893 R3894 1
C3894 1
C3889 R3896 2 X7R-CERM 1206
1206
73.2K 0.0033UF 41.2K 0.33UF 100PF 15.8K
1%
10%
1%
10%
SGND GND 5%
1% TBTBST:Y TBTBST:Y TBTBST:Y
1/16W 1/16W 1/16W
MF-LF 2
50V
MF-LF 2
6.3V
2
50V
MF-LF C3896 1
C3898 1 1
C3899
23
24
37
12
13
14
15
16
17
CERM CERM-X5R CERM
402 402 402 2
4
2 402 2 402 402 4.7UF 4.7UF 0.001UF
<R2>
GND_TBTBST_SGND
<Rb> 10%
50V
10%
50V
10%
50V
X7R-CERM 2 X7R-CERM 2 2 X7R
MIN_LINE_WIDTH=0.5 mm 1206 1206 402
UVLO(falling) = 1.22 * (R1 + R2) / R2 MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
UVLO(rising) = UVLO(falling) + (2uA * R1)
SGND shorted to
UVLO = 4.55V (falling), 4.95 (rising) Vout = 1.6V * (1 + Ra / Rb)
GND inside package,
C no XW necessary. C
Supervisor & CLKREQ# Isolation TBTBST:Y
6 D Q3888 TBTBST:Y
7 =PP3V3_S0_TBTPWRCTL
SSM6N37FEAPE 1
=PP3V3_TBT_RTR 7 33 34 SOT563 R3888
330K
5%
1/16W
C3800 1
CRITICAL 1
R3807 MF-LF
1
0.1UF 1
S G 2 Max Vgs: 10V 2
402
10% VDD 100K
Platform (PCIe) Reset 25V 5%
TBTBST_SHDN_DIV
X5R
402
2
U3800 1/16W
MF-LF
24 IN =TBT_RESET_L SLG4AP016V 2
402 TBTBST:Y
TBTBST:Y
TDFN PP1V05_TBT 7
1
R3887 3 D Q3888
+ SENSE
2 2 330K
R3803 5% SSM6N37FEAPE
10K - 0.7V 1/16W SOT563
5% MF-LF
1/16W 402
2
MF-LF
Open-Drain GPIO 402 DLY
1
RESET* 4 TBT_RESET_L 4
S G 5
OUT 33
19 IN TBT_SW_RESET_L 3 MR*
DLY = 60 ms +/- 20% SMC_DELAYED_PWRGD IN 45 46 92
24 IN TBT_PWR_EN 6 EN
=TBT_CLKREQ_L IN 33
16 OUT TBT_CLKREQ_L 8 OUT
(OD) IN 7 TBT_CLKREQ_ISOL_L
MAKE_BASE=TRUE
Pull-ups provided by SB page. THRM
GND PAD
5
B B
3.3V Thunderbolt Switch
U3810
7 =PP3V3_S0_P3V3TBTFET TPS22924 =PP3V3_TBT_FET 7
CSP
A2 A1 Max Current = 2A (85C)
B2 VIN VOUT B1
CRITICAL U3810
C3810 1 C2 ON
1UF GND Part TPS22924C
10%
C1
6.3V
CERM 2 Type Load Switch
402
R(on) 18.3 mOhm Typ
@ 2.5V 24 mOhm Max
1
R3816
0
5%
1/16W
MF-LF
402
2
TBT_PWR_EN_RC
1.05V Thunderbolt Switch
U3815
7 =PP1V05_S0_P1V05TBTFET TPS22920 =PP1V05_TBT_FET 7
CSP
A2 A1 Max Current = 4A (85C)
B2 B1
VIN VOUT
A C2
CRITICAL
C1 U3815 SYNC_MASTER=T29_REF SYNC_DATE=06/22/2011 A
Part TPS22920 PAGE TITLE
C3815 1 D2 ON
1UF GND Type Load Switch
Thunderbolt Power Support
10%
DRAWING NUMBER SIZE
D1
6.3V
CERM
402
2
R(on) 8 mOhm Typ
@ 1.05V 11.5 mOhm Max REVISION
NO STUFF
R
3.0.0
C3816 1
1UF THE INFORMATION CONTAINED HEREIN IS THE
10%
6.3V PROPRIETARY PROPERTY OF APPLE INC.
CERM 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
38 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
=PP1V2_ENET_PHY 7
???mA (1000base-T, Caesar V)

72 36 24 7 =PP3V3_ENET_PHY
281mA (1000base-T max power, Caesar IV)
VDD for Card Reader I/O
36 =PP3V3R1V8_ENET_LR_OUT
CRITICAL ENET_SR_LX 72
Internal 1.2V Switching Regulator pins.
L3900 CRITICAL
FERR-600-OHM-0.5A ENET_SR_VFB 72
L3920
D
1
SM
2 PP3V3_S3_ENET_PHY_XTALVDDH
VOLTAGE=3.3V C3900 1 PP1V2_ENET_PHY_AVDDL
FERR-600-OHM-0.5A
1 2
D
0.1UF MIN_NECK_WIDTH=0.2 mm SM
10% VOLTAGE=1.2V
16V
X7R-CERM
402
2
C3921 1 1
C3920
CRITICAL 0.1UF 4.7UF
10% 10%
L3905 16V
2 2
6.3V
CRITICAL
FERR-600-OHM-0.5A X7R-CERM X5R-CERM
402 603
L3925
1 2 PP3V3_S3_ENET_PHY_BIASVDDH FERR-600-OHM-0.5A
SM MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 1 C3905 PP1V2_ENET_PHY_PCIEPLL 1 2
0.1UF MIN_NECK_WIDTH=0.2 mm SM
10% VOLTAGE=1.2V
16V
2 X7R-CERM
402
C3926 1 1
C3925
CRITICAL 0.1UF 4.7UF
10% 10%
L3910 16V
2 2
6.3V
CRITICAL
FERR-600-OHM-0.5A X7R-CERM X5R-CERM
402 603
L3930
1 2 PP3V3_S3_ENET_PHY_AVDDH FERR-600-OHM-0.5A
SM MIN_NECK_WIDTH=0.2 mm 1 2
1
C3910 1
C3911 PP1V2_ENET_PHY_GPHYPLL
VOLTAGE=3.3V R3910 1 MIN_LINE_WIDTH=0.4 mm
SM
4.7K 0.1UF 0.1UF MIN_NECK_WIDTH=0.2 mm
10% 10% VOLTAGE=1.2V
5% 16V 16V
1/16W
MF-LF
2 X7R-CERM 2 X7R-CERM C3931 1 1 C3930
402 402
402
2
0.1UF 4.7UF
10% 10%
16V 6.3V
X7R-CERM 2 2 X5R-CERM
402 603
R3940 1
1
R3941 C3915 1 1
C3916
4.7UF 0.1UF CRITICAL
4.7K 4.7K
C3936 C3935
42
48
37
17
20
56
62
14
15
16
13
39
45
51
29
32
36
35
61
10% 10% 1 1
5% 5% LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
7
6.3V 16V
1/16W 1/16W 2 2
C
X5R-CERM X7R-CERM 0.1UF 10UF the card reader on-chip I/O.
C
BIASVDDH
XTALVDDH
SR_VDD
SR_VDDP
SR_LX
SR_VFB
GPHY_PLLVDDL
MF-LF MF-LF 603 402
=PP3V3_S0_ENETPHY 10% 10%
AVDDH AVDDL VDDC
PCIE_PLLVDDL
7 402
2 2
402 VDDO 16V
2 2
6.3V
Connect only to U3900 pin 20.
X7R-CERM X5R
402 805
1
R3942 =PP3V3R1V8_ENET_LR_OUT 36
C3950 1K
0.1uF 5% Current
1/16W
96 16 PCIE_ENET_D2R_N 1 2
MF-LF
Limiting
OUT
402 Resistor
10%
2
U3900 PP3V3R1V8_ENET_LR_OUT_REG
16V C3951 ENET_VMAIN_PRSNT 58 VMAIN_PRSNT (IPD) BCM57765B0 TRD0_P 40 ENET_MDI_P<0> BI 37 97 MAKE_BASE=TRUE
X5R
0.1uF
402 QFN-8X8
TRD0_N 41 ENET_MDI_N<0> BI 37 97
96 16 OUT PCIE_ENET_D2R_P 1 2 MIN_NECK_WIDTH=0.2 mm
96 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N TRD1_P 44 ENET_MDI_P<1> BI 37 97
VOLTAGE=1.8V
10% 96 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENET_MDI_N<1> BI 37 97

16V
X5R 46 ENET_MDI_P<2>
1 C3970 1 C3971 1
C3972
C3955 TRD2_P BI 37 97
4.7UF 0.1UF 0.1UF
402 96 PCIE_ENET_R2D_P 33 PCIE_RXD_P
0.1uF TRD2_N 47 ENET_MDI_N<2> BI 37 97
10%
6.3V
10%
16V
10%
16V
96 PCIE_ENET_R2D_N 34 PCIE_RXD_N 2 X5R-CERM 2 X7R-CERM 2 X7R-CERM
96 16 IN PCIE_ENET_R2D_C_P 1 2
TRD3_P 50 ENET_MDI_P<3> BI 37 97 603 402 402
10%
96 16 IN PCIE_CLK100M_ENET_P 31 PCIE_REFCLK_P TRD3_N 49 ENET_MDI_N<3> BI 37 97
16V C3956 96 16 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
X5R
402
0.1uF 5
GPIO_0/CR_ACT_LED*
(IPD)
96 16 IN PCIE_ENET_R2D_C_N 1 2
97 30 IN ENET_RESET_L 11 PERST* (IPD)
NC
GPIO_1/LR_OUT 8
10% ENET_CLKREQ_L 12 CLKREQ* GPIO_2/MEDIA_SENSE 9 ENET_MEDIA_SENSE

R3943 16V
16 OUT (OD) OUT 24
0 X5R
NOTE: "IPx" == Programmable pull-up/down
24 OUT =ENET_WAKE_L 1 2 402 ENET_WAKE_R_L 3 WAKE* (OD)
(IPx) SD_DETECT o1 SDCONN_DETECT_L IN 30
(See note) 5%
SD_DETECT can only be used active low due to errata.
1/16W
MF-LF 30 24 IN ENET_LOW_PWR 4 LOW_PWR (IPD) (IPU) CR_CMD 26 SDCONN_CMD IN 30 97
WAKE# 402
CR_CLK 21 SDCONN_CLK OUT 30 97

Must isolate from PCIe WAKE# if PHY BCM57765_SMB_CLK 6 SMB_CLK
is powered-down in S3/S5. Standard BCM57765_SMB_DATA 10 SMB_DATA (IPD) CR_DATA0 25 SDCONN_DATA<0> BI 30 97
N-channel FET isolation suggested. CR_DATA1 24 SDCONN_DATA<1> BI 30 97

BCM57765_SCLK 66 SCLK_SPD1000LED*
B If PHY is always powered then alias
36
36 BCM57765_MISO 64 SI/EEDATA
CR_DATA2 23 SDCONN_DATA<2> BI 30 97
B
(IPU)
=ENET_WAKE_L to PCIE_WAKE_L. CR_DATA3 22 SDCONN_DATA<3> BI 30 97
36 BCM57765_MOSI 65 SO_LINKLED*
36 BCM57765_CS_L 63 CS*/EECLK
(IPU)
TP_BCM57765_SPD100LED_L 2 SPD100LED*/SERIAL_DO (OD) CR_DATA6 54 SDCONN_DATA<6> BI 30 97
TP_BCM57765_TRAFFICLED_L 67 TRAFFICLED*/SERIAL_DI (OD) CR_DATA7 55 SDCONN_DATA<7> BI 30 97
MS_INS* 59 TP_CE_L_MS_INS_L
No MS (Memory Stick) Insert feature needed.
(IPU)
24 IN SYSCLK_CLK25M_ENET 18 XTALI
CR_LED*/CR_BUS_PWR 60 ENET_CR_PWREN OUT 30 Control signal to light LED or control SD bus power.
19 XTALO
NC CR_WP* 57 SDCONN_WP IN 30
BCM57765_RDAC 38 RDAC SR_DISABLE 68 BDM57765_SR_DISABLE R3980 1K 1 2

THRM_PAD 5% 1/16W MF-LF 402
PHY Non-Volatile Memory
69
1
R3965
1.24K
ROM contains MAC address, PCIe config 1%
BCM57765 supports both active-levels for WP.
1/16W
info as well as code for Bonjour proxy. MF-LF SR_DISABLE must be pulled down to use
2 402 internal SR. IPD has a race condition.
Required for proper PHY operation.
(Required ROM size TBD)
72 36 24 7 =PP3V3_ENET_PHY
C3990
6
VCC 0.1UF
10%
16V
U3990 2 X7R-CERM
AT45DB011D 402
SOIC-8S1
36 BCM57765_SCLK 2
SCK SI 1 BCM57765_MOSI 36
A 36 BCM57765_CS_L 4 CS*
OMIT
SYNC_MASTER=K91_ERIC SYNC_DATE=10/11/2010 A
PAGE TITLE
5
WP*
SO 8
NOSTUFF
BCM57765_MISO 36
ETHERNET PHY (CAESAR IV)
1 1 DRAWING NUMBER SIZE
3 RESET* R3990 R3997 051-9585 D
GND
5%
4.7K
5%
4.7K Apple Inc. REVISION
7
1/16W 1/16W R
MF-LF MF-LF 3.0.0
2 402 2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: Pull-down on SO plus internal pull-ups on
other 3 SPI pins configures ENET for the PROPRIETARY PROPERTY OF APPLE INC.
Atmel AT45DB011D (1Mbit) ROM. If a different I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 39 OF 132
ROM is used then the straps must change. II NOT TO REPRODUCE OR COPY IT
NOTE: ENETM requires SI pull-down instead of SO.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
(NONE)

(NONE)
BOM options provided by this page:

(NONE)
D D
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1 C4000 1 C4002 1 C4004 1 C4006

0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10%
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
402-1 402-1 402-1 402-1
CRITICAL
T4000
SM
97 36 BI ENET_MDI_P<0> 1 12 101 ENETCONN_P<0>
97 36 BI ENET_MDI_N<0> 2 11 101 ENETCONN_N<0>

CRITICAL
3 10 ENET_CTAP0
J4000
RJ45-M97-3
TX F-RT-TH
TLA-6T213HF 9
C 4 9 ENET_CTAP1 10
C
97 36 BI ENET_MDI_N<1> 5 8 101 ENETCONN_N<1> 1
97 36 BI ENET_MDI_P<1> 6 7 101 ENETCONN_P<1> 3
RX 4
5
CRITICAL 6
T4001
SM
7
97 36 BI ENET_MDI_N<2> 1 12 101 ENETCONN_N<2> 8
97 36 ENET_MDI_P<2> 2 11 101 ENETCONN_P<2> 11

BI
12
3 10 ENET_CTAP2
TX
514-0636
TLA-6T213HF
4 9 ENET_CTAP3
97 36 BI ENET_MDI_N<3> 5 8 101 ENETCONN_N<3>
97 36 BI ENET_MDI_P<3> 6 7 101 ENETCONN_P<3>

RX
Transformers should be
mirrored on opposite R40001 R40011 1
R4002 1
R4003
sides of the board 75 75 75 75
5% 5% 5% 5% CRITICAL
1/16W 1/16W 1/16W 1/16W
B MF-LF
402 2
MF-LF
402 2
MF-LF
2 402
MF-LF
2 402
C4008
1000PF
B
ENET_BOB_SMITH_CAP 1 2
MIN_NECK_WIDTH=0.25 mm 10%
2KV
CERM
1206
PLACE_NEAR=T4001.1:5mm
PLACE_NEAR=T4000.5:5mm
6 5 7 4 9 2 10 1 6 5 7 4 9 2 10 1
NC
IO
NC
IO
NC
IO
NC
IO
NC
IO
NC
IO
NC
IO
NC
IO
D4001 D4000
GND
GND
RCLAMP0524P RCLAMP0524P
SLP2510P8 SLP2510P8
3 3
CRITICAL CRITICAL
NOSTUFF NOSTUFF
A SYNC_MASTER=K91_TRINHNI SYNC_DATE=05/26/2010 A
PAGE TITLE
Ethernet Connector
DRAWING NUMBER SIZE

REVISION
R
3.0.0
40 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_FW_FWPHY 7 38 39 40
7 mA I/O
138 mA
C4120 1
C4121 1
C4122 1
C4123 1
C4124 1
1UF 1UF 1UF 1UF 1UF

10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402 402
L4130
D 114 mA FireWire PHY

PP3V3_FW_FWPHY_VDDA
120-OHM-0.3A-EMI
1 2
D
MIN_NECK_WIDTH=0.2 MM 0402-LF
VOLTAGE=3.3V
C4130 1
C4131 1
C4132 1
1UF 1UF 1UF

10% 10% 10%
6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM 2
402 402 402
L4110 L4135
R4100 120-OHM-0.3A-EMI 120-OHM-0.3A-EMI
0 25 mA PCIe SerDes 17 mA PCIe SerDes
39 7 =PP1V0_FW_FWPHY 1 2 PP1V0_FW_R 1 2 PP1V0_FW_FWPHY_AVDD PP3V3_FW_FWPHY_VP25 1 2
MIN_LINE_WIDTH=0.4 MM MIN_LINE_WIDTH=0.4 MM MIN_LINE_WIDTH=0.4 MM
135 mA 5% MIN_NECK_WIDTH=0.2 MM 0402-LF MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 0402-LF
1/16W VOLTAGE=1.0V VOLTAGE=1.0V VOLTAGE=3.3V
MF-LF
402
1 C4110 1 C4111 C4135 1 C4136 1
1UF 1UF 1UF 1UF

10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM CERM 2 CERM 2
402 402 402 402
110 mA Digital Core 0 mA VReg PWR
1
C4100 1
C4101 1
C4102 1
C4103 1
C4104 1
C4105 1
C4106 C4141 1 1
C4140
1UF 1UF 1UF 1UF 1UF 1UF 1UF 0.1UF 1UF
10% 10% 10% 10% 10% 10% 10% 20% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 10V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM CERM 2 2 CERM
402 402 402 402 402 402 402 402 402
C C
PLACE_NEAR=U1800.AV34:2.54mm
C41701
B12
C13
E10
H12
M12
N11
C12
G12
L11
A12
L10
K12
10%
2 16V PCIE_FW_R2D_C_N
A1
B1
E2
H2
K2
L1
N3
C1
F1
J1
L3
M2
D5
D6
D8
L5
L6
L9
IN 16 96
0.1UF X5R 402-1
PLACE_NEAR=U1800.AU34:2.54mm
VDD10 VDD33 VDDH VP VP25 VREG_PWR C41711 10%
2 16V PCIE_FW_R2D_C_P IN 16 96
OMIT 0.1UF
NC
B13 ATBUSB PCIE_RXD0N N8 96 PCIE_FW_R2D_N X5R 402-1
CRITICAL
NC
A13 ATBUSH PCIE_RXD0P N7 96 PCIE_FW_R2D_P PLACE_NEAR=U1800.BG36:2.54mm
U4100 C41751
NC A11 ATBUSN PCIE_TXD0N N5 96 PCIE_FW_D2R_C_N 10%
2 16V PCIE_FW_D2R_N OUT 16 96
0.1UF
FW643 PCIE_TXD0P N6 96 PCIE_FW_D2R_C_P X5R 402-1
40 IN =FW_PHY_DS0 F12 DS0 (IPD) NT-19
C41761 10%
2 16V
BGA
PCIE_FW_D2R_P OUT 16 96
40 IN =FW_PHY_DS1 E12 DS1 (IPD) NT-20 0.1UF
REFCLKN N9 PCIE_CLK100M_FW_N IN 16 96
X5R 402-1
40 IN =FW_PHY_DS2 E13 DS2 (IPD) NT-21 PCI EXPRESS PHY
REFCLKP N10 PCIE_CLK100M_FW_P IN 16 96
97 40 BI FW_P0_TPA_N B8 TPA0N
97 40 BI FW_P0_TPA_P A8 TPA0P
NT-4 (IPU) TCK M4 TP_FW643_TCK 6
97 40 BI FW_P1_TPA_N B5 TPA1N
NT-3 (IPU) TDI N2 TP_FW643_TDI 6
97 40 BI FW_P1_TPA_P A5 TPA1P TEST CONTROLLER =PP3V3_FW_FWPHY 7 38 39 40
(IPU) TDO M1 TP_FW643_TDO 6
40 BI FW_P2_TPA_N B3 TPA2N
NT-1 (IPU) TMS M3 TP_FW643_TMS 6
40 BI FW_P2_TPA_P A3 TPA2P 1394 PHY FW643_LDO
97 40 BI FW_P0_TPB_N B9 TPB0N NT-2 (IPU) TRST* N1 FW643_TRST_L R4165 1
1
R4166
97 40 BI FW_P0_TPB_P A9 TPB0P 10K 10K
5% 5%
97 40 BI FW_P1_TPB_N B6 TPB1N 1/16W 1/16W
MF-LF MF-LF
FW_P1_TPB_P A6 TPB1P 402 2
2 402
97 40 BI
NT-10 (IPD) WAKE* C2 =FW_PME_L OUT 8 39
40 BI FW_P2_TPB_N B4 TPB2N
40 =PPVP_FW_PHY_CPS FIXME!!! - TYPO IN SYMBOL REGCTL REGCLT D13 FW643_REGCTL
40 BI FW_P2_TPB_P A4 TPB2P
POWER MANAGEMENT VAUX_DETECT E1 FW643_VAUX_DETECT
R4160 1 40 BI FW_P0_TPBIAS B7 TPBIAS0 NT-12 (IPD) VAUX_DISABLE D2 TP_FW643_VAUX_ENABLE 6
B 200K
1%
1/16W
40 39
40
BI
BI
FW_P1_TPBIAS
FW_P2_TPBIAS
C3
A2
TPBIAS1
TPBIAS2
NT-13 (OD) CLKREQN L2 =FW_CLKREQ_L OUT 39
1
R4164
10K
B
MF-LF 5%
402 1/16W
2 FW643_R0 B11 R0 MF-LF
PLACE_NEAR=U4100.B10:2mm
FW643_TPCPS B10 TPCPS 2 402
NT-16 (IPD) SCIFCLK G2 TP_FW643_SCIFCLK 6
SCIF NT-14 (IPD) SCIFDAIN G1 TP_FW643_SCIFDAIN 6

C4150 TP_FW643_NAND_TREE K1 NAND_TREE NT-OUT
R4150 NT-17 SCIFDOUT H1 TP_FW643_SCIFDOUT 6
22PF FW643_REXT L8 REXT
412 NOTE: NT-xx notes show NT-15 (IPD) SCIFMC F2 TP_FW643_SCIFMC 6
1 2 FW_CLK24P576M_XO 1 2 FW_CLK24P576M_XO_R F13 XO
NAND tree order.
5%
CRITICAL 1% FW_CLK24P576M_XI G13 XI NT-9
1/16W
50V
Y4150 MF-LF
1
CERM 402 TP_FW643_SE M13 SE (IPD)

402 NC 24.576MHZ R4161 1 1
R4170
6
SERIAL EEPROM NT-7 SCL N12 FW643_SCL
2
NC SM-3.2X2.5MM 6 TP_FW643_SM N13 SM (IPD) CONTROLLER

C4151 2.94K 191 NT-6 SDA M11 TP_FW643_SDA 6
4
1% 1% TP_FW643_MODE_A J2 MODE_A (IPD) NT-18

3
22PF 1/16W 1/16W

MF-LF MF-LF 6 TP_FW643_CE L13 CE (IPD)
1 2
402 402
2 2 6 TP_FW643_FW620_L D12 FW620* (IPU) MISCELLANEOUS
5% TP_FW643_JASI_EN D1
50V
6 JASI_EN (IPD) NT-11
CERM 6 TP_FW643_AVREG A10 AVREG CHIP RESET NT-5 PERST* N4 FW_RESET_L IN 39
402
6 TP_FW643_VBUF H13 VBUF
FW643_PU_RST_L K13 1
FW_RESET* (IPU) NT-8 R4163
10K
TP_FW643_OCR10_CTL J12 OCR_CTL_V10 5%
R4162 1 1
C4162 J13 OCR_CTL_V12
1/16W
470K NC (Reserved) MF-LF
402
0.33UF 2
5%
1/16W 10% VSS VREG_VSS
6.3V
MF-LF 2
L12
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
CERM-X5R
402 402
2
PAGE TITLE
FireWire LLC/PHY (FW643)

DRAWING NUMBER SIZE

REVISION
R
3.0.0
41 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes FireWire Port Power Switch
CRITICAL
- =PPBUS_S5_FWPWRSW (FW VP FET Input)
Q4260 CRITICAL CRITICAL
- =PPBUS_FW_FET (FW VP FET Output)
FDC638P_G F4260 D4260
- =PP3V3_FW_P3V3FWFET (3.3V FET Input) SM
1.1A-24V SBR3U30P1 =PPBUS_FW_FET 7
- =PP3V3_FW_FET (3.3V FET Output) 6 PPBUS_FW_FWPWRSW_F 1 2 PPBUS_FW_FWPWRSW_D A K
- =PP3V3_FW_FWPHY (PHY 3.3V Power) 7 =PPBUS_S5_FWPWRSW Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection) 5
4
- =PP3V3_S0_FWLATEVG 2
VOLTAGE=12.6V MINISMDC110H24 VOLTAGE=12.6V PWRDI123
- =PP3V3_S0_FWPWRCTL 1
- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail) 1 1
R4262 R4260 C4260 1
- =PP1V05_FW_P1V0FWFET (1.0V FET Input) 10K 300K
D - =PP1V0_FW_FET_R (1.0V FET Output)

5%
1/16W
MF-LF 4
5%
1/16W
MF-LF
0.1UF
10%
25V
X5R 2
3 D
- =PP1V0_FW_FWPHY (PHY 1.0V) 402
2 2
402 402
(SYM-VER2)
Signal aliases required by this page: FWPORT_FASTOFF_L_DIV 5 S SOT-363 FWPORT_PWREN_L_DIV
BSS8402DW
- =FW_CLKREQ_L G
Q4262
1
- =FW_PME_L R4263 CRITICAL
10 D
BOM options provided by this page: 5%
1/16W 3
(NONE) MF-LF
402
2
FWPORT_FASTOFF_L
1
R4261
6 470K
5%
Supervisor & CLKREQ# Isolation
D CRITICAL 1/16W
MF-LF 40 39 38 7 =PP3V3_FW_FWPHY
402
40 7 =PP3V3_S0_FWLATEVG Q4262 2
7 =PP3V3_S0_FWPWRCTL
2 G BSS8402DW FWPORT_PWREN_L
SOT-363
S (SYM-VER1)
CRITICAL
D C4290 1 CRITICAL 1
R4290
1
1 3
NO STUFF 0.1UF
Q4261 VDD 100K
C4261 1 10%
25V 5%
SSM3K15FV 0.1UF
10%
X5R
402
2
U4290 1/16W
MF-LF
SOD-VESM-HF
25V 24 IN =FW_RESET_L SLG4AP016V 2
402
X5R 2
402 TDFN =PP1V0_FW_FWPHY 7 38
1 G S
+ SENSE
2 2 2
R4283
40 FWPORT_PWR_EN 10K - 0.7V
IN
5%
1/16W
MF-LF
402 DLY
1
C FW_RESET_R_L 3 MR*
RESET* 4 FW_RESET_L
DLY = 60 ms +/- 20%
OUT 38
C
39 24 IN FW_PWR_EN 6 EN
=FW_CLKREQ_L IN 38
16 OUT FW_CLKREQ_L 8 OUT
(OD) IN 7 FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
Pull-up provided by another page. THRM
GND PAD
9
7 =PP1V05_S0_FWPWRCTL
FireWire Port 5K Pull-Down Detect
R4275 1 All FireWire devices require 5K pull-down on TPB pair.
1K
5% Host can detect as load on TPBIAS signal.
1/16W
MF-LF Current source only active when FW_PWR_EN is low.
402 2
FW_PWR_EN_L
3.3V FW Switch
U4201
6 1
R4270 R4271 1 7 =PP3V3_FW_P3V3FWFET TPS22924 =PP3V3_FW_FET 7
CRITICAL CSP
330K 56K FW_5KPD_DET_L A2 A1 Max Current = 1.7A (85C)
D Q4275 5% 5% MAKE_BASE=TRUE
1/16W 1/16W B2 VIN VOUT B1
DMB53D0UV MF-LF MF-LF
SOT-563 2 402
402 2 3 CRITICAL CRITICAL
39 24 IN FW_PWR_EN 2 G
FW_5KPD_DET_RC 5 Q4275 C4201 1 C2 ON U4201 & U4202
DMB53D0UV 1UF GND
10%
SOT-563 Part TPS22924C
C1
6.3V
2
CRITICAL 3 6 CRITICAL C4270 1
4
CERM
402
S Type Load Switch
Q4270 Q4270 0.1UF
BC847CDXV6TXG
5 FWDET_MIRROR 2
BC847CDXV6TXG
10%
16V
R(on) 18 mOhm Typ
B B
1 SOT563 SOT563 X5R 2
402
4 1
50 mOhm Max
Max Output: 2A
FW_P1_TPBIAS_R FWDET_EMIT
1.0V FW Switch
R4272 1 R4273 1 U4202
1K 12K 7 =PP1V05_FW_P1V0FWFET TPS22924 PP1V05_FW_FET
5% 5% CSP MIN_LINE_WIDTH=0.4 mm
1/16W 1/16W A2 A1 MIN_NECK_WIDTH=0.2 mm
MF-LF MF-LF VIN VOUT VOLTAGE=1.05V
402 2 402 2 B2 B1
PLACE_NEAR=C4360.1:2 mm CRITICAL LSI FireWire PHY requires 1.0V.
FW_P1_TPBIAS
C4202 1 C2 ON 1
R4202 To avoid an extra power supply,
40 38 IN 1UF GND 0.549 1.05V is used with a series R
10%
1%
C1
6.3V
CERM 2 1/16W to reduce voltage.
402 MF
FireWire PHY WAKE# Support 2

402
=PP1V0_FW_FET_R 7
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
40 39 38 7 =PP3V3_FW_FWPHY Dual-purpose output:
1) 5K Pull-down Detect when FW_PWR_EN is low.

2) FW643 WAKE# (PME#) when PHY is powered.
R4277 1
1
R4276
10K 100K FW_PME_L OUT 8 19
5% 5%
1/16W 1/16W Pull-up provided on another page.
MF-LF MF-LF
402
2 2
402 3 CRITICAL
FW_WAKE 5 Q4276
DMB53D0UV
NO STUFF
A
SOT-563
6
D
C4276
0.1UF
10%
1
4
SYNC_MASTER=K91_MLB
PAGE TITLE
16V
X5R
402
2
FireWire Port & PHY Power
G DRAWING NUMBER SIZE
=FW_PME_L FW643_WAKE_L 2
38 8 IN 8
MAKE_BASE=TRUE
CRITICAL Apple Inc. 051-9585 D
REVISION
Q4276
DMB53D0UV
R
3.0.0
S NOTICE OF PROPRIETARY PROPERTY: BRANCH
SOT-563
42 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes FW643 TPCPS Leakage Protection Unused FireWire Ports FireWire PHY Config Straps
FW643 has internal leakage path from TPCPS pin to VDD33. Disabled per LSI instructions Configures PHY for:
- =PPVP_FW_PORT1
FET blocks current to TPCPS until VDD33 is powered. (All unused port signals TP/NC) - Port "1" Bilingual (1394B)
- =PPVP_FW_PHY_CPS_FET (From Port)
- =PPVP_FW_PHY_CPS (To PHY) 40 39 38 7 =PP3V3_FW_FWPHY
- =PP3V3_FW_FWPHY
BSS8402DW
CRITICAL
- =PP3V3_S0_FWLATEVG
Q4300
(SYM-VER2)
38 IN FW_P0_TPBIAS NC_FW0_TPBIAS
SOT-363
R4382 1
1
MAKE_BASE=TRUE NO_TEST=TRUE R4380
97 38 BI FW_P0_TPA_P NC_FW0_TPAP 6 10K 10K
- =FW_PHY_DS0 MAKE_BASE=TRUE NO_TEST=TRUE 1% 1%
1/16W 1/16W
- =FW_PHY_DS1 97 38 BI FW_P0_TPA_N NC_FW0_TPAN MF-LF MF-LF
=PPVP_FW_PHY_CPS_FET PPVP_FW_CPS
D - =FW_PHY_DS2
7
MAKE_BASE=TRUE NO_TEST=TRUE 402 2 2 402
D
D
FW_P0_TPB_P NC_FW0_TPBP
3
From Port MIN_NECK_WIDTH=0.2 mm 97 38 BI 6
NOTE: This page is expected to contain VOLTAGE=12.6V MAKE_BASE=TRUE NO_TEST=TRUE FWPHY_DS0 =FW_PHY_DS0 OUT 38
the necessary aliases to map the 97 38 BI FW_P0_TPB_N NC_FW0_TPBN 6
R4311 1 =PPVP_FW_PHY_CPS 38 MAKE_BASE=TRUE NO_TEST=TRUE FWPHY_DS1 =FW_PHY_DS1 OUT 38
G
FireWire TPA/TPB pairs to their MAKE_BASE=TRUE
470K To FW643
appropriate connectors and/or to FW_P2_TPBIAS NC_FW2_TPBIAS FWPHY_DS2 =FW_PHY_DS2
5
5% 38 IN 6 OUT 38
1/16W MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
properly terminate unused signals. MF-LF
402 38 BI FW_P2_TPA_P NC_FW2_TPAP 6
2 1
BOM options provided by this page:
MAKE_BASE=TRUE NO_TEST=TRUE R4381
CPS_EN_L_DIV 38 BI FW_P2_TPA_N NC_FW2_TPAN 6 10K
(NONE) MAKE_BASE=TRUE NO_TEST=TRUE 1%
1/16W
1 38 BI FW_P2_TPB_P NC_FW2_TPBP 6 MF-LF
1394b implementation based on Apple R4312 MAKE_BASE=TRUE NO_TEST=TRUE
2
402
FireWire Design Guide (FWDG 0.6, 5/14/03) 330K 38 BI FW_P2_TPB_N NC_FW2_TPBN 6

5% MAKE_BASE=TRUE NO_TEST=TRUE
1/16W
MF-LF
402 2
CPS_EN_L
6
CRITICAL
D
40 39 38 7 =PP3V3_FW_FWPHY Q4300
2 G BSS8402DW
SOT-363
S (SYM-VER1)
C C
CRITICAL
Cable Power
Termination L4310
FERR-250-OHM Note: Trace PPVP_FW_PORT1 must handle up to 5A
Place close to FireWire PHY 7 =PPVP_FW_PORT1
1 2 PPVP_FW_PORT1_F
39 38 IN FW_P1_TPBIAS SM MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V
1
C4314
B 0.01UF
10%
B
1 C4360 2
50V
X7R
0.33UF 402
10%
6.3V (FW_PORT1_TPB_N)
2 CERM-X5R
402
(FW_PORT1_TPB_P)
"Snapback" & "Late VG" Protection

SIGNAL_MODEL=EMPTY
PORT 1
SIGNAL_MODEL=EMPTY 39 7 =PP3V3_S0_FWLATEVG BILINGUAL
1 1
R4360 R4361 CRITICAL
56.2 56.2 PLACE_NEAR=U4350.1:2 mm
1% 1% J4310
1/16W 1/16W C4350 1
1394B-M97
1
MF-LF MF-LF
0.1UF VCC F-RT-TH
2 402 402 2 10%
TPB- TPB(R)
FW_P1_TPA_P FW_PORT1_TPA_P
16V
X5R 2 U4350 (FW_PORT1_TPB_N) 1 TPB-
97 38 BI
MAKE_BASE=TRUE
402 TPD4S1394 (FW_PORT1_BREF) 9 TPB<R> OUTPUT
LLP
FW_P1_TPA_N FW_PORT1_TPA_N TP_FWLATEVG_VCLMP 3 8 2 TPB+ VP
97 38 BI VCLMP D1+ (FW_PORT1_TPB_P) TPB+
MAKE_BASE=TRUE 7
D1- 8 VP
FW_P1_TPB_P FW_PORT1_TPB_P FWPORT_PWR_EN 4
97 38 BI 39 OUT FWPWR_EN 7
MAKE_BASE=TRUE
CRITICAL D2+ 6 NC SC/NC NC
97 38 BI FW_P1_TPB_N FW_PORT1_TPB_N (GND) 6 VG

R4350 1
SIGNAL_MODEL=EMPTY MAKE_BASE=TRUE D2- 5
SIGNAL_MODEL=EMPTY GND (FW_PORT1_TPA_N) 3 TPA- VG TPA-
100K
2
1
R4362 R4363
1 5% FW_PORT1_AREF 5 TPA<R> INPUT
1/16W TPA(R)
56.2 56.2 MF-LF (FW_PORT1_TPA_P) 4 TPA+ TPA+
1% 1% 402 2
1/16W 1/16W
MF-LF MF-LF
402 402 10
2 2 PLACE_NEAR=J4310.5:2 mm
11
FW_PORT1_TPB_C C4319 1
12 CHASSIS
0.1uF GND
A 1 C4364 R4364
1 (FW_PORT1_TPA_N) 10%
50V
X7R 2
13
SYNC_MASTER=T27_REF SYNC_DATE=06/10/2010 A
4.99K (FW_PORT1_TPA_P) 603-1 PAGE TITLE
220pF 514S0605
5%
25V
1%
1/16W 1 FireWire Connector
2 CERM MF-LF
402 2
R4319 AREF needs to be isolated from all DRAWING NUMBER SIZE
402 1M
5%
1/16W
local grounds per 1394b spec
MF-LF REVISION
When a bilingual device is connected to a
2
402
beta-only device, there is no DC path

R
3.0.0
between them (to avoid ground offset issue)
PLACE_NOTE=J4310.5:2 mm BREF should be hard-connected to logic THE POSESSOR AGREES TO THE FOLLOWING: PAGE
ground for speed signaling and connection I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
43 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Q4590
ODD Power Control DMP2018LFK
CRITICAL SATA ODD Connector
7 =PP5V_S3_ODD DFN2563-6
6 PP5V_SW_ODD
D
S
VOLTAGE=5V
1
1 C4595 1
4
R4596
100K 0.068UF
10%
95 6 SATA_ODD_R2D_P C4521 1 2 GND_VOID=TRUE SATA_ODD_R2D_C_P IN 16 95
G
5% 10V 0.01UF 10% 16V CERM 402
1/16W CERM 2
J4500
3
Note: 3.3V must be S0 if 5V is S3 or S5 to MF-LF 402
ensure the drive is unpowered in S3/S5.
402
2
C4596 54722-0164 95 6 SATA_ODD_R2D_N C4520 1 2 GND_VOID=TRUE SATA_ODD_R2D_C_N IN 16 95
F-ST-SM
R4595 0.01UF 0.01UF 10% 16V CERM 402
100K 1 2
ODD_PWR_EN_LS5V_L 1 2 ODD_PWR_SS 1 2
D 5%
1/16W 10%
16V
3
5
4
6
D
41 7 =PP3V3_S0_ODD D 6 MF-LF
Q4596 402 CERM
402
7 8
SSM6N37FEAPE 9 10
R45971 SOT563
11 12
100K 13 14
5%
1/16W 15 16
MF-LF
402 2
2 G S 1 95 6 SATA_ODD_D2R_C_N C4526 1 2 GND_VOID=TRUE SATA_ODD_D2R_N OUT 16 95
0.01UF 10% 16V CERM 402
ODD_PWR_EN CRITICAL
516S0616 95 6 SATA_ODD_D2R_C_P C4525 1 2 GND_VOID=TRUE SATA_ODD_D2R_P OUT 16 95
41 7 =PP3V3_S0_ODD 0.01UF 10% 16V CERM 402
Q4596 D 3 1
R4590
SSM6N37FEAPE 33K
SOT563 5%
1/16W
MF-LF
5 G S
402 2
SATA OOB Comparator
4 Notes:
45 6 OUT SMC_ODD_DETECT
19 IN ODD_PWR_EN_L OOBD2R was OOB_TEMP, from SSD, to SMC
Note: Indicates disc presence. OOBR2D was TEMP_CTL, from SMC, to SSD
7 =PP3V3_S0_SMC
1 C4580
SATA HDD Connector (Gen3) 41 7 =PP1V5_S0_RDRVR 0.1UF
20%
1
R4585
1K
5%
1 1 10V
R4581 R4583 2 CERM
402
1/16W
MF-LF
CRITICAL 100K 49.9K
2 402
5% 1%
R4599 1/16W
MF-LF
1/16W
MF-LF
0.001 402 402 U4580
C L4500
FERR-70-OHM-4A
1%
1W
MF-1
0612
2 2
SSD_OOB1V0REF 3
VCC+
5
LMV331
SC70-5
R4586
0
C
PP5V_S0_HDD_FLT 1 2 PP5V_S0_HDD_R 1 2 =PP5V_S0_HDD 4 SMC_SSD_OOBD2R_R_L 1 2 SMC_SSD_OOBD2R_L
6
MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
7
R4582 OUT 46
0603 3 4 3.3K 5%
MIN_NECK_WIDTH=0.4MM MIN_NECK_WIDTH=0.4MM
SSD_OOBD2R_FTL_L 1 2 SSD_OOBD2R_R_L 1 GND 1/16W
VOLTAGE=5V CRITICAL VOLTAGE=5V 41 IN
PLACE_NEAR=J4501.9:3MM MF-LF
ISNS_HDD_P OUT 101 103 5% 2 402
1/16W
ISNS_HDD_N 1
2
C4501 2
C4502 OUT 101 103 MF-LF
402 R4584 1 C4584
=PP3V3_S0_HDD 7 100K
0.1UF 0.1UF
NOSTUFF 20% 20% SATA Redriver 5% 0.1UF
20%
1
10V 10V 1/16W

1 10V
C4537
1
CERM 1
CERM R4538 Internally PD ~150K
MF-LF 2 CERM
402 402 100K 2 402 402
100UF PLACE_NEAR=L4500.1:2MM PLACE_NEAR=L4500.2:2MM 5% Write:0xB6 Read:0xB7
20%
10V 1/16W
X5R-CERM MF-LF
1206 2 402
2
PLACE_NEAR=J4501.9:10MM ADDR1 ADD0 Address (R/W)

6 SSD_OOBR2D_L R4537 1 2 SMC_SSD_OOBR2D_L IN 46 41 7 =PP1V5_S0_RDRVR
453 1% 1/16W MF-LF 402
L L 0x96/0x97 NO STUFF
NOSTUFF
L4539 L H 0x98/0x99
R45131 R45151
1
6 SSD_OOBD2R_L 1 2 SSD_OOBD2R_FTL_L 41 4.7K 4.7K

OUT
C4538 FERR-220-OHM 0402
H L 0xB6/0xB7
5%
1/16W
5%
1/16W
100UF MF-LF MF-LF
20%
10V
6 SYS_LED_ANODE_R R4531 1 2 SYS_LED_ANODE IN 6 46 402 2 402 2
X5R-CERM 4.7 5% 1/16W MF-LF 402 H H 0xB8/0xB9
SATARDRVR_I2C_ADDR0 41
1206
C4531 1
2
PLACE_NEAR=J4501.10:10MM
0.001UF SATARDRVR_I2C_ADDR1 41
10%
50V
CERM 2 =PP1V5_S0_RDRVR =PP1V5_S0_RDRVR
402 41 7 41 7
=PP5V_S3_IR 7 44 IR_RX_OUT 6 44
1 C4514 1 C4519 C4518 & C4517 Placement Note:
OUT 0.1UF 0.01UF
R45101 20%
2 10V
CERM
20%
16V
2 CERM
It is critical that these two should be near
1
R4532 4.7K
B 5%
0
J4501 D2R Passive DeEmphasis
5%
1/16W
MF-LF
402
402
to U1800 pin AM1 and AM3.
B
1/16W 402 2
MF-LF 54722-0224 VALUE: 4.5 DB
2 402 F-ST-SM NOSTUFF
6 PP5V_S3_IR_R 1 2 R4536 1 2 GND_VOID=TRUE
MIN_LINE_WIDTH=0.5MM 68.1 1% 1/20W MF 201 PLACE_NEAR=U1800.AM1:5MM

3 4 GND_VOID=TRUE
VOLTAGE=5V
5 6
95 6 SATA_HDD_D2R_C_P C4536 1 2 GND_VOID=TRUE 95 SATA_HDD_D2R_RC_P C4516 1 2 GND_VOID=TRUE
95 SATA_HDD_D2R_RDRIN_P 95 SATA_HDD_D2R_RDROUT_P C4518 1 2 SATA_HDD_D2R_P 16 95
7 8 OUT
5.0PF 0201 +/-0.1PF C0G 25V 0.01UF 10% 16V CERM 402 0.01UF 10% 16V CERM 402
1 C4532 9 10
0.1UF
10% 11 12 95 6 SATA_HDD_D2R_C_N C4535 1 2 GND_VOID=TRUE
95 SATA_HDD_D2R_RC_N C4515 1 2 GND_VOID=TRUE
95 SATA_HDD_D2R_RDRIN_N 95 SATA_HDD_D2R_RDROUT_N C4517 1 2 SATA_HDD_D2R_N OUT 16 95
2 16V
X7R-CERM 13 14 5.0PF 0201 +/-0.1PF C0G 25V 0.01UF 10% 16V CERM 402 0.01UF 10% 16V CERM 402
402
15 16 PLACE_NEAR=U1800.AM3:5MM
R4535 GND_VOID=TRUE
16
1 2 GND_VOID=TRUE
6
GND_VOID 17 18 GND_VOID
68.1 1% 1/20W MF 201
GND_VOID 19 20 GND_VOID
VDD
21 22
U4510
R4534 1 2 GND_VOID=TRUE
PS8521A
516S0687 41.2 1% 1/20W MF 201
TQFN PLACE_NEAR=U4510.12:5MM
1 15 GND_VOID=TRUE
CRITICAL A_INP GND_VOID GND_VOID A_OUTP
95 6 SATA_HDD_R2D_N C4534 1 2 GND_VOID=TRUE
95 SATA_HDD_R2D_RC_N C4511 1 2 GND_VOID=TRUE
95 SATA_HDD_R2D_RDROUT_N 2
A_INN GND_VOID GND_VOID A_OUTN 14 95 SATA_HDD_R2D_RDRIN_N C4513 1 2 SATA_HDD_R2D_C_N IN 16 95
15PF 5% 25V NPO 201 0.01UF 10% 16V CERM 402 0.01UF 10% 16V CERM 402
4 B_OUTN GND_VOID GND_VOID B_INN 12
95 6 SATA_HDD_R2D_P C4533 1 2 GND_VOID=TRUE 95 SATA_HDD_R2D_RC_P C4510 1 2 GND_VOID=TRUE

95 SATA_HDD_R2D_RDROUT_P 5 B_OUTP GND_VOID GND_VOID B_INP 11 95 SATA_HDD_R2D_RDRIN_P C4512 1 2 SATA_HDD_R2D_C_P IN 16 95
15PF 5% 25V NPO 201 0.01UF 10% 16V CERM 402 0.01UF 10% 16V CERM 402
23 16 IN SATARDRVR_EN 7 EN REXT 20 SATARDRVR_REXT PLACE_NEAR=U4510.11:5MM

GND_VOID=TRUE
R4533 1 2 GND_VOID=TRUE
41.2 1% 1/20W MF 201 41 IN SATARDRVR_I2C_ADDR0 8 B_PRE0/I2C_ADDR0 A_PRE1/SCL_CTL 19 =SATARDRVR_I2C_SCL IN 48
41 IN SATARDRVR_I2C_ADDR1 9 APRE0/I2C_ADDR1 B_PRE1/SDA_CTL 17 =SATARDRVR_I2C_SDA BI 48
A R2D Passive DeEmphasis

SATARDRVR_I2C_EN_L 10 I2C_EN* SYNC_MASTER=J31_YONAS SYNC_DATE=11/17/2011 A
1 PAGE TITLE
VALUE: 3.0 DB SATARDRVR_TEST 18 TEST R4512
GND THRM
3.74K
1%
SATA Redriver/Conn, IR, SIL
PAD 1/16W DRAWING NUMBER SIZE
1
R4511
MF-LF
051-9585 D
3
13
21
0
2
402
Apple Inc. REVISION
5%
1/16W
MF-LF
338S0907
R
3.0.0
2
402 CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH
45 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D USB Port Power Switch D

USB Port A (Front Port)
CRITICAL
CRITICAL
U4600
TPS2561DR L4605
FERR-120-OHM-3A
SON
7 =PP5V_S3_USB 2
IN_0 OUT1 9 PP5V_S3_USB_A_ILIM 1 2 PP5V_S3_USB_A_F
3 IN_1 OUT2 8 MIN_NECK_WIDTH=0.2 mm 0603 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V VOLTAGE=5V
USB_EXTB_OC_L 10 7 USB_ILIM PP5V_S3_USB_B_ILIM
C4605 1
23 OUT FAULT1* ILIM 43
0.01UF
23 OUT USB_EXTA_OC_L 6
FAULT2* MIN_NECK_WIDTH=0.2 mm
20%
16V CRITICAL CRITICAL
VOLTAGE=5V
4
EN1
CERM
402
2
L4600 J4600
90-OHM-100MA
DLP11S
USB-3.0-J30
74 =USB_PWR_EN 5
EN2 THRM SYM_VER-1
F-RT-TH
GND PAD USB_EXTA_MUXED_N
R4600 1
4 3
CRITICAL 95
1
1 C4695 1 C4617 1
VBUS
C4690 1 1 C4691 23.2K
11
C4696 1%
10UF 10UF 95 USB_EXTA_MUXED_F_N 2
10UF 0.1UF 220UF-35MOHM 1/16W
20% 20% D-
20% 20% 20% MF-LF
6.3V
2
6.3V
2 95 USB_EXTA_MUXED_P 1 2 95 USB_EXTA_MUXED_F_P 3
6.3V
2 2
10V
2 6.3V 402
X5R X5R D+
X5R CERM POLY-TANT 2 603 603 4
603 402 CASE-B2-SM1 GND
95 6 USB3_EXTA_RX_F_N 5
2 5 3 4 STDA_SSRX-
95 6 USB3_EXTA_RX_F_P 6
NC
IO
NC
IO
STDA_SSRX+
6 VBUS 7
GND_DRAIN
95 6 USB3_EXTA_TX_F_N 8
Current limit per port (R4600): 2.18A min / 2.63A max 1 GND
95 6 USB3_EXTA_TX_F_P 9
STDA_SSTX-
STDA_SSTX+
D4600 10
RCLAMP0582N
C SLP1210N6
CRITICAL
11
12 C
13
14
SHIELD
15
GND_VOID=TRUE 16
CRITICAL 17
18
L4610
80OHM-25%-100MA
0504
L2
Mojo SMC Debug Mux 95 18 6 OUT USB3_EXTA_RX_N 4 3
1
95 18 6 OUT USB3_EXTA_RX_P 2
L1
7 =PP3V42_G3H_SMCUSBMUX
MOJO:YES
MOJO:YES 1
R4650
C4650 1 10K
5%
9
0.1UF 1/16W
20%
10V VCC MF-LF
2
CERM 2 402
SMC_DEBUGPRT_RX_L 402 5 1
46 45 IN M+ Y+
SMC_DEBUGPRT_TX_L 4 2
46 45 OUT M- U4650 Y-
PI3USB102ZLE
TQFN GND_VOID=TRUE
95 18 BI USB_EXTA_P 7 D+
6
CRITICAL CRITICAL
95 18 BI USB_EXTA_N D-
MOJO:YES L4620
B 8 OE* SEL 10 SMC_DEBUGPRT_EN_L IN 45
80OHM-25%-100MA
0504
B
GND_VOID=TRUE
GND SEL=0 Choose SMC C4620 L2
SEL=1 Choose USB 0.1UF
3
SIGNAL_MODEL=MOJO_MUX
95 18 6 IN USB3_EXTA_TX_N 1 2 95 6 USB3_EXTA_TX_C_N 4 3
C4621
10% 6.3V
X5R 201
0.1UF
1
95 18 6 IN USB3_EXTA_TX_P 1 2 95 6 USB3_EXTA_TX_C_P 2
MOJO:NO L1
R4651 10% 6.3V
0 X5R 201
1 2 GND_VOID=TRUE
5
5%
1/16W MOJO:NO
MF-LF
402 R4652
0
1 2 CRITICAL
5%
1/16W
MF-LF
D4610
GND
NC
402
ESD3V3U4ULC-IP4292CZ10
PGTSLP91-XSON-COMBO
6
7
8
9
A SYNC_MASTER=J31_LINDA SYNC_DATE=09/21/2011 A
PAGE TITLE
External A USB3 Connector

DRAWING NUMBER SIZE

REVISION
R
3.0.0
46 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D USB Port B (Back Port) D
CRITICAL
L4705
FERR-120-OHM-3A
42 PP5V_S3_USB_B_ILIM 1 2 PP5V_S3_USB_B_F
0603 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
C4705 1
0.01UF
20% CRITICAL CRITICAL
16V
CERM
402
2
L4700 J4700
90-OHM-100MA
DLP11S
USB-3.0-J30
SYM_VER-1 F-RT-TH
95 25 BI USB_EXTB_MUX_N 4 3
1
VBUS
95 USB_EXTB_F_N 2
D-
95 25 USB_EXTB_MUX_P 1 2 95 USB_EXTB_F_P 3
BI D+
4
GND
95 6 USB3_EXTB_RX_F_N 5
2 5 3 4 STDA_SSRX-
95 6 USB3_EXTB_RX_F_P 6
NC
IO
NC
IO
STDA_SSRX+
6 VBUS 7
GND_DRAIN
95 6 USB3_EXTB_TX_F_N 8
1 GND STDA_SSTX-
95 6 USB3_EXTB_TX_F_P 9
STDA_SSTX+
D4700 10
C RCLAMP0582N
SLP1210N6
CRITICAL
11
12
C
13
14
SHIELD
15
GND_VOID=TRUE 16
CRITICAL 17
18
L4710
80OHM-25%-100MA
0504
L2
95 18 6 OUT USB3_EXTB_RX_N 4 3
1
95 18 6 OUT USB3_EXTB_RX_P 2
L1
GND_VOID=TRUE
CRITICAL
B L4720
80OHM-25%-100MA
B
0504
GND_VOID=TRUE
C4720 L2
0.1UF
95 18 6 USB3_EXTB_TX_N 1 2 95 6 USB3_EXTB_TX_C_N 4 3
IN
C4721
10% 6.3V
X5R 201
0.1UF
1
95 18 6 IN USB3_EXTB_TX_P 1 2 95 6 USB3_EXTB_TX_C_P 2
L1
10% 6.3V
X5R 201
GND_VOID=TRUE
5
CRITICAL
D4710
GND
NC
ESD3V3U4ULC-IP4292CZ10
PGTSLP91-XSON-COMBO
6
7
8
9
NOTE: Swapped pin4 and 5, pin6 and 7 for layout.
PAGE TITLE
External B USB3 Connector

DRAWING NUMBER SIZE

REVISION
R
3.0.0
47 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IR SUPPORT
D 41 7 =PP5V_S3_IR
D
1 C4801
0.1UF
10%
16V
2 X7R-CERM
402
14
VCC
U4800
CY7C63803-LQXC
QFN
USB_IR_P 12 P1.0/D+ P0.0 7

95 8 BI
DIFFERENTIAL_PAIR=USB2_TPAD NC
95 8 BI USB_IR_N 13 P1.1/D- P0.1 6
NC
DIFFERENTIAL_PAIR=USB2_TPAD
IR_VREF_FILTER 15 P1.2/VREG INT0/P0.2 5
NC
16 P1.3/SSEL INT1/P0.3 4
NC NC
17 P1.4/SCLK INT2/P0.4 3 R4800
1
C4803 NC NC 100
1UF NC
18 P1.5/SMOSI TIO0/P0.5 2 45 IR_RX_OUT_RC 1 2 IR_RX_OUT IN 6 41
10% 19 P1.6/SMISO TIO1/P0.6 1 5%
2
10V NC NC 1/16W
X5R MF-LF
402-1 8
NC CRITICAL 402
9
OMIT
NC 1 C4804
10
NC P/N 338S0633
0.001UF
20 10%
NC NC 2
50V
21 CERM
NC 402
22
NC
C NC
23
24
C
NC THRML
PAD VSS
25
11
B B
PAGE TITLE
Front Flex Support

DRAWING NUMBER SIZE

REVISION
R
3.0.0
48 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
U4900
LM4FSXAH5BB
BGA
96 89 47 16 6 BI LPC_AD<0> B13 LPC0AD0 (1 OF 2) AIN00 E2 SMC_ADC0 IN 46
96 89 47 16 6 BI LPC_AD<1> A13 LPC0AD1 AIN01 E1 SMC_ADC1 IN 46
96 89 47 16 6 BI LPC_AD<2> C12 LPC0AD2 OMIT_TABLE AIN02 F2 SMC_ADC2 IN 46
96 89 47 16 6 BI LPC_AD<3> D11 LPC0AD3 AIN03 F1 SMC_ADC3 IN 46
96 24 IN LPC_CLK33M_SMC H12 LPC0CLK AIN04 B3 SMC_ADC4 IN 46
96 89 47 16 6 IN LPC_FRAME_L D12 LPC0FRAME* AIN05 A3 SMC_ADC5 IN 46
24 IN SMC_LRESET_L C13 LPC0RESET* AIN06 B4 SMC_ADC6 IN 46 =PP3V3_S5_SMC 7 46 82
47 16 6 BI LPC_SERIRQ (OD) H13 LPC0SERIRQ AIN07 A4 SMC_ADC7 IN 46
47 17 6 OUT PM_CLKRUN_L (OD) G11 LPC0CLKRUN* AIN08 B5 SMC_ADC8 IN 46 L4901

LPC_PWRDWN_L F13 A5 SMC_ADC9 30-OHM-1.7A
47 17 6 IN LPC0PD* AIN09 IN 46
19 OUT SMC_RUNTIME_SCI_L F12 LPC0SCI* AIN10 B6 SMC_ADC10 NC FOR STACK BRD

IN 46
1 2 PP3V3_S5_SMC_VDDA
46 OUT SMC_WAKE_SCI_L B12 PK5 AIN11 A6 SMC_ADC11 NC FOR STACK BRD
IN 46 0402 MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
AIN12 C1 SMC_ADC12 IN 46
1
R4902
1 C4901
SMBUS_SMC_0_S0_SCL SMC_ADC13
1 C4902 1 C4903 1 C4904 1 C4905 1 C4906 0.1UF
99 48 BI (OD) E10 I2C0SCL AIN13 C2
IN 46
1UF 0.1UF 0.1UF 0.1UF 0.1UF 1M U4900 10%
20% 10% 10% 10% 10% 5% 10V
99 48 BI SMBUS_SMC_0_S0_SDA (OD) D13 I2C0SDA AIN14 B1 SMC_ADC14 IN 46 6.3V 10V 10V 10V 10V 1/20W
LM4FSXAH5BB 2 X5R-CERM
2 X5R 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM MF 0201
99 48 BI SMBUS_SMC_1_S0_SCL (OD) M4 I2C1SCL AIN15 B2 SMC_ADC15 IN 46
0201 0201 0201 0201 0201 2
201
BGA
99 48 BI SMBUS_SMC_1_S0_SDA (OD) N2 I2C1SDA AIN16 G2 SMC_ADC16 NC FOR STACK BRD
IN 46 (2 OF 2)
SMBUS_SMC_2_S3_SCL N8 G1 SMC_ADC17 SMC_RESET_L G10 C10 SMC_TCK
99 48 6 BI (OD) I2C2SCL AIN17 NC FOR STACK BRD
IN 46 65 47 46 6 IN RST* SWCLK/TCK 6 46 47
SMBUS_SMC_2_S3_SDA M8 H1 SMC_ADC18 A10 SMC_TMS

99 48 6 BI (OD) I2C2SDA AIN18 NC FOR STACK BRD
IN 46 SWDIO/TMS 6 46 47
SMBUS_SMC_3_SCL L8 H2 SMC_ADC19 WIFI_EVENT_L B11 A11 SMC_TDO

99 48 BI (OD) I2C3SCL AIN19 NC FOR STACK BRD
IN 46 46 32 6 BI (OD) PK4/RTCCLK SWO/TDO 6 46 47
C 99 48
46
BI
BI
SMBUS_SMC_3_SDA
SMBUS_SMC_4_ASF_SCL
(OD)
NC FOR ENG PKG

K8
N7
I2C3SDA
I2C4SCL
AIN20
AIN21
B7
A7
SMC_ADC20
SMC_ADC21
NC FOR STACK BRD
NC FOR STACK BRD

IN
IN
46
46
1
C4907
0.1UF
1
C4908
0.1UF
1
C4909
0.1UF
SMC_WAKE_L
NC_SMC_HIB_L
N13
M12
WAKE*
HIB*
TDI B10 SMC_TDI 6 46 47
C
SMBUS_SMC_4_ASF_SDA NC FOR ENG PKG M7 I2C4SDA AIN22 B8 SMC_ADC22 NC FOR STACK BRD 10% 10% 10% OMIT_TABLE NC A2
46 BI IN 46
2
10V
2
10V
2
10V NC
SMBUS_SMC_5_G3_SCL N4 A8 SMC_ADC23 X5R-CERM X5R-CERM X5R-CERM SMC_CLK32K M10
99 48 6 BI (OD) I2C5SCL AIN23 1.2V FOR ENG PKG
IN 46
0201 0201 0201 46 IN XOSC0
99 48 6 BI SMBUS_SMC_5_G3_SDA (OD) N3 I2C5SDA NC_SMC_XOSC1 N10 XOSC1
C0- K2 CPU_PROCHOT_L IN 10 46 69 93 VDDA D3
52 OUT SMC_FAN_0_CTL H11 PM6/FAN0PWM0 C0+ K1 SMC_VCCIO_CPU_DIV2 46 46 SMC_EXTAL G12 OSC0

SMC_FAN_0_TACH L13 L2 SMC_S5_PWRGD_VIN SMC_XTAL G13 D2 PP3V3_S5_AVREF_SMC
52 IN PM7/FAN0TACH0 C1- 46 46 OSC1 VREFA+ 6 46
52 OUT SMC_FAN_1_CTL C11 PK6/FAN0PWM1 PC5/C1+ L1 SPI_DESCRIPTOR_OVERRIDE_L OUT 24 VREFA- D1

A12
XW4900
52 IN SMC_FAN_1_TACH PK7/FAN0TACH1 T3CCP1/PJ5/C2- C5 CPU_CATERR_L IN 10 93 K12 VBAT 103 50 SM
G3 49
46 OUT SMC_MPM5_LED_PWR NC FOR STACK BRD PN2/FAN0PWM2 T3CCP0/PJ4/C2+ D5 CPU_THRMTRIP_3V3 IN 46
C3 46 GND_SMC_AVSS 2 1
46 SMC_MPM5_LED_CHG NC FOR STACK BRD D10 PN3/FAN0TACH2 D7 GNDA E3

OUT PLACE_NEAR=U4900.A1:4MM
M2 SMC_PM_G2_EN E6
SSI0CLK/PA2 OUT 46 74
SMC_SYS_KBDLED L11 M3 PM_DSW_PWRGD E8 A1

54 OUT PN4/FAN0PWM3 SSI0FSS/PA3 OUT 17
SMC_T25_EN_L N12 L4 SMC_DELAYED_PWRGD E9 C7

46 OUT PN5/FAN0TACH3 SSI0RX/PA4 OUT 35 46 92
46 BI SYS_TDM_ONEWIRE N11
PN6/FAN0PWM4 SSI0TX/PA5 N1 SMC_PROCHOT OUT 46
F10 VDD D9
SYS_ONEWIRE M11 J7 E5
64 IN PN7/FAN0TACH4
HISIDE_ISENSE_OC J4 F11 SMC_DEBUGPRT_RX_L J9 F9
1
C4920 1 C4921
46 IN PH2/FAN0PWM5 U1RX/B0 IN 42 46
0.01UF 1UF
SMC_ODD_DETECT J2 E11 SMC_DEBUGPRT_TX_L J10 H5 10% 20%
41 6 IN (OD) PH3/FAN0TACH5 U1TX/PB1 OUT 42 46 10V 6.3V
H9 2 X5R 2 X5R
T0CCP0/PB6 F4 SMC_SYS_LED OUT 46
GND 201 0201
CPU_PECI_R C4 F3 SMC_GFX_THROTTLE_L PP1V2_S5_SMC_VDDC J1 J5
46 BI PECI0RX T0CCP1/PB7 BI 82 46
MIN_LINE_WIDTH=0.25MM J6 J8
46 OUT SMC_PECI_L C6 PECI0TX MIN_NECK_WIDTH=0.1MM
VOLTAGE=1.2V PLACE_NEAR=U4900.D2:1MM
SSI1RX/PF0 M9 SPI_SMC_MISO NC FOR STACK BRD 46 K13 VDDC J11 PLACE_NEAR=U4900.D1:1MM
IN PLACE_NEAR=U4900.D2:1MM
64 46 6 IN SMC_BIL_BUTTON_L M13 PP0/IRQ116 SSI1TX/PF1 N9 SPI_SMC_MOSI NC FOR STACK BRD
OUT 46 D6 K11 PLACE_NEAR=U4900.D1:1MM
SMC_DP_HPD_L L12 L10 SPI_SMC_CLK
46 IN PP1/IRQ117 SSI1CLK/PF2 NC FOR STACK BRD
OUT 46
SMC_PME_S4_WAKE_L M5 K10 SPI_SMC_CS_L

46 IN PP2/IRQ118 SSI1FSS/PF3 NC FOR STACK BRD
OUT 46
SMC_PME_S4_DARK_L J12 L9 S5_PWRGD

PP3/IRQ119 PF4
B
46
74 46
IN
OUT SMC_S4_WAKESRC_EN J13
L5
PP4/IRQ120 PF5 K9 PM_PCH_SYS_PWROK
IN
IN
74
17 23 92 B
NC PP5/IRQ121
NC FOR ENG PKG
NC
D8 PP6/IRQ122 WT0CCP0/PG4 K7 SMC_DEBUGPRT_EN_L OUT 42
64 53 46 IN SMC_LID K6 PP7/IRQ123 WT0CCP1/PG5 L7 SMC_GFX_OVERTEMP IN 46 82

1 C4910 1 C4911 1 C4912 1 C4913 1 C4914 1 C4915 1 C4916 1 C4917
1.0UF 1.0UF 1.0UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 10% 10% 10% 10% 10%
ENET_ASF_GPIO D4 K3 ALL_SYS_PWRGD 10V 10V 10V 10V 10V 10V 10V 10V
46 OUT (OD) PQ0/IRQ124 WT2CCP0/PH0 IN 23 74 89 92 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
SMS_INT_L E4 K4 SMC_THRMTRIP 0201-1 0201-1 0201-1 0201 0201 0201 0201 0201
55 IN PQ1/IRQ125 WT2CCP1/PH1 OUT 46
NOSTUFF
64 46 IN SMC_BC_ACOK F5 PQ2/IRQ126
46 IN G3_POWERON_L N5 PQ3/IRQ127 WT3CCP0/PH4 J3 PM_PWRBTN_L OUT 17 23
PM_SLP_S3_L N6 H4 PM_SYSRST_L
74 26 17 6 IN PQ4/IRQ128 WT3CCP1/PH5 OUT 6 17 24
PM_SLP_S4_L K5 H3 MEM_EVENT_L
74 32 26 17 IN PQ5/IRQ129 WT4CCP0/PH6 (OD)
BI 27 29 46
PM_SLP_S5_L M6 G4 SMC_ADAPTER_EN
74 17 IN PQ6/IRQ130 WT4CCP1/PH7 IN 17 46 74
SMC_ONOFF_L L6
53 46 6 IN PQ7/IRQ131
T1CCP0/PJ0 C9 SMC_OOB1_RX_L NC FOR ENG PKG
IN 46
SMC_RX_L L3 B9 SMC_OOB1_TX_L
47 46 6 IN U0RX T1CCP1/PJ1 OUT 46
SMC_TX_L M1 A9 IR_RX_OUT_RC
47 46 6 OUT U0TX T2CCP0/PJ2 NC FOR ENG PKG
IN 44
T2CCP1/PJ3 C8 BDV_BKL_PWM NC FOR ENG PKG

OUT 46
E13 USB0DM
NC
NC
E12 USB0DP WT5CCP1/PM3 H10 SMC_BATLOW_L OUT 46 74
NOTE:
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
A NOTE:
Unused pins have "SMC_Pxx" names. Unused SYNC_MASTER=J31_YONAS SYNC_DATE=12/19/2011 A
PAGE TITLE
pins designed as outputs can be left floating,
those designated as inputs require pull-ups. SMC DRAWING NUMBER SIZE

REVISION
R
3.0.0
49 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
93 69 45 10 BI CPU_PROCHOT_L
SMC Reset "Button", Supervisor & AVREF Supply 45 SMC_ADC0 SMC_CPU_VSENSE
MAKE_BASE=TRUE
49
Q5059
SMC12 PECI Support
45 SMC_ADC1 SMC_CPU_ISENSE 50 SSM6N15AFE
82 46 45 7 =PP3V3_S5_SMC MAKE_BASE=TRUE 6 D SOT563 =PPVCCIO_S0_SMC 7 46
=PPVIN_S5_SMCVREF SMC_ADC2 SMC_GPU_HI_ISENSE CRITICAL

7 45 50
MAKE_BASE=TRUE CRITICAL
Desktops: 5V
SMC_ADC3 SMC_DCIN_VSENSE
Mobiles: 3.42V
45
MAKE_BASE=TRUE
49
Q5050
D 3
1
R5000 SMC_ADC4 SMC_DCIN_ISENSE
3
45 50 SSM3K15AMFVAPE
C5020 1
100K
MAKE_BASE=TRUE
1 S G 2
0.47UF V+ VIN SMC_ADC5 SMC_PBUS_VSENSE VESM
5% 45 49
10%
6.3V U5010 1/16W MAKE_BASE=TRUE SMC_PROCHOT IN 45
CERM-X5R 2 MF-LF
402 VREF-3.3V-VDET-3.0V 402 45 SMC_ADC6 SMC_HDD_ISENSE 103
2
DFN
MAKE_BASE=TRUE 1 G S 2
D 53 46 45 6
53 IN
IN
SMC_TPAD_RST_L
SMC_ONOFF_L
6
7
MR1*
MR2*
(IPU)
SN0903048 RESET* 5 SMC_RESET_L OUT 6 45 47 65 45 SMC_ADC7 SMC_BMON_ISENSE
MAKE_BASE=TRUE
50 19 OUT PM_THRMTRIP_L_R
Q5059 45 IN SMC_PECI_L 1
R5052
0
2 SMC_PECI_L_R
D
(IPU) PP3V3_S5_AVREF_SMC 6 45 45 SMC_ADC8 SMC_CPU_HI_ISENSE 50
SSM6N15AFE 5%
SMC_MANUAL_RST_L 4 DELAY CRITICAL REFOUT 8
MAKE_BASE=TRUE 3 D From SMC. 1/16W
VOLTAGE=3.3V 45 SMC_ADC9 SMC_OTHER_HI_ISENSE 50
SOT563 MF-LF
1 1
OMIT THRM CRITICAL 402
GND PAD MAKE_BASE=TRUE R5053 R5051
1
R5001 45 SMC_ADC10 SMC_MEM_ISENSE 49 1.6K 330
C5001 1
9
MAKE_BASE=TRUE 5% 5%
0 0.01UF C5025 1 1
C5026 SMC_ADC11 SMC_CPUVCCIO_ISENSE
1/16W 1/16W
5% 10% 10uF 0.01UF 45 49 MF-LF MF-LF
1/10W 16V 20% 10%
MAKE_BASE=TRUE
4 S G 5 402
2 2 402
MF-LF CERM 2 6.3V 16V
2 603 402 X5R 2 2 CERM 45 SMC_ADC12 SMC_AXG_VSENSE 49 NOSTUFF
603 402 MAKE_BASE=TRUE
SILK_PART=SMC_RST SMC_THRMTRIP IN 45 46
45 SMC_ADC13 SMC_CPUVCCSA_ISENSE 49
MAKE_BASE=TRUE
PLACEMENT_NOTE=Place R5001 on BOTTOM side GND_SMC_AVSS 45 49 50 103
MIN_LINE_WIDTH=0.4MM 45 SMC_ADC14 SMC_GPU_VSENSE 49
MR1* and MR2* must both be low to cause manual reset.

VOLTAGE=0V
MAKE_BASE=TRUE
Q5057
45 SMC_ADC15 SMC_GPU_ISENSE 49 3 D SSM6N15AFE R5054
Used on mobiles to support SMC reset via keyboard. MAKE_BASE=TRUE
SOT563 43
NOTE: Internal pull-ups are to VIN, not V+. 45 SMC_ADC16 SMC_GPU_FB_VSENSE 103 CRITICAL 45 OUT CPU_PECI_R 1 2 CPU_PECI BI 10 19 93
MAKE_BASE=TRUE
5%
45 SMC_ADC17 SMC_CPUVCCSA_VSENSE 49
To SMC. 1/16W From/To CPU/PCH.
MAKE_BASE=TRUE MF-LF
402
45 SMC_ADC18 SMC_AXG_ISENSE 50 S G 5
4
SMC_ADC19
MAKE_BASE=TRUE
SMC_GPU_FB_ISENSE
SMC12 SPI Support
Debug Power "Buttons" 45
MAKE_BASE=TRUE
103
SMC_GFX_OVERTEMP IN 45 82
Series resistors are no stuffed until the
45 SMC_ADC20 SMC_GPU_1V05_ISENSE 103
MAKE_BASE=TRUE topology of 2 SPI Masters are verified.
Note:
SMC_ONOFF_L OUT 6 45 46 53 45 SMC_ADC21 SMC_PCH_ISENSE 103
R5021
ADC10 and ADC11 are MAKE_BASE=TRUE NO STUFF
OMIT OMIT share with comparators
0
SMC_ADC22 SMC_AIRPORT_ISENSE SPI_SMC_MISO 1 2 SPI_MLB_MISO
R5016 1 1
R5015
45
MAKE_BASE=TRUE
103
R5013 45 IN
OUT 47 56
on Stack Board. 0 5%
0 0 46 45 SMC_ADC23 SMC_CPUMEM_ISENSE_R 1 2 SMC_CPUMEM_ISENSE 103 NO STUFF R5022 1/16W
5% 5% MAKE_BASE=TRUE MF-LF
1/10W 1/10W 5% 0 402
MF-LF MF-LF 45 ENET_ASF_GPIO NC_ENET_ASF_GPIO 1/20W 45 IN SPI_SMC_MOSI 1 2 SPI_MLB_MOSI OUT 47 56
603 603 MAKE_BASE=TRUE MF PLACE_NEAR=U6100.5:1MM
C SILK_PART=PWR_BTN
PLACE_SIDE=BOTTOM
2 2
SILK_PART=PWR_BTN
PLACE_SIDE=TOP
45 SMC_MPM5_LED_PWR NC_SMC_MPM5_LED_PWR
MAKE_BASE=TRUE
201
SMC_PACKAGE:PROD
45 SPI_SMC_CLK
5%
1/16W
MF-LF
402
R5023
1
0
2
NO STUFF
SPI_MLB_CLK 47 56
C
SMC_MPM5_LED_CHG NC_SMC_MPM5_LED_CHG IN OUT
45 PLACE_NEAR=U6100.6:1MM
MAKE_BASE=TRUE 5%
NO STUFF R5024 1/16W
19 SMC_SCI_L SMC_WAKE_SCI_L 45 MF-LF
MAKE_BASE=TRUE 46 45 OUT CPU_THRMTRIP_3V3 0 402
45 IN SPI_SMC_CS_L 1 2 SPI_MLB_CS_L OUT 47 56
45 SMC_T25_EN_L NC_SMC_T25_EN_L PLACE_NEAR=U6100.1:1MM
MAKE_BASE=TRUE 5%
1/16W
SYS_TDM_ONEWIRE NC_SYS_TDM_ONEWIRE 3 MF-LF
45
MAKE_BASE=TRUE R5058 402
Q5058 3.3K
SMC Crystal Circuit 45 SMC_OOB1_RX_L SMC_SSD_OOBD2R_L
MAKE_BASE=TRUE
41
MMBT3904LP-7
1 PM_THRMTRIP_B_L 1 2 PM_THRMTRIP_L IN 10 19 93 82 46 45 7 =PP3V3_S5_SMC
DFN1006-3 5%
SMC USB Clock require 12 MHz. 45 SMC_OOB1_TX_L SMC_SSD_OOBR2D_L 41 CRITICAL 1/20W
MAKE_BASE=TRUE 2 MF
201
65 49 =CHGR_ACOK SMC_BC_ACOK 45 46 64
MAKE_BASE=TRUE
53 46 45 6 SMC_ONOFF_L R5070 10K 1 2
HISIDE_ISENSE_OC NC_HISIDE_ISENSE_OC 5% 1/20W MF 201
R5010
45
MAKE_BASE=TRUE 45 G3_POWERON_L R5072 10K 1 2
5% 1/20W MF 201
2.49K 45 SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCL 64 53 45 SMC_LID R5071 100K 1 2
SMC_XTAL 1 2 SMC_XTAL_R MAKE_BASE=TRUE 5% 1/20W MF 201
45
47 45 6 SMC_TX_L R5073 10K 1 2
1% SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SDA 5% 1/20W MF 201
45
SMC_RX_L R5074 100K
1/20W
MF
201 Y5010 45 BDV_BKL_PWM
MAKE_BASE=TRUE
NC_BDV_BKL_PWM
SCM12 Eng Pkg Support 47 45 6
45 42 SMC_DEBUGPRT_TX_L R5075 10K

1
1
2
2
5% 1/20W MF 201
3.2X2.5MM-SM MAKE_BASE=TRUE 5% 1/20W MF 201
12.000MHZ-30PPM-10PF Eng Package requires 1.2V ON SMC_ADC23 pin. 45 42 SMC_DEBUGPRT_RX_L R5076 100K 1 2
SMC_PME_S4_DARK_L SDCONN_STATE_CHANGE_SMC 5% 1/20W MF 201
45 SMC_EXTAL 1 3
45
MAKE_BASE=TRUE
24 30
47 45 6 SMC_TMS R5077 10K 1 2
R5012 45 PP1V2_S5_SMC_VDDC 47 45 6 SMC_TDO R5078 10K 1 2
5% 1/20W MF 201
NC 2 4
NC 22 5% 1/20W MF 201
17 IN PM_CLK32K_SUSCLK_R 1 2 SMC_CLK32K OUT 45 47 45 6 SMC_TDI R5079 10K 1 2
PLACE_NEAR=U1800.N14:5MM 5% 1/20W MF 201
1
C5010 CRITICAL 1
C5011 5% 1
R5099 47 45 6 SMC_TCK R5080 10K 1 2
1/20W
12PF
5%
12PF
5%
MF 0 64 45 6 SMC_BIL_BUTTON_L R5081 10K 1 2
5% 1/20W MF 201
201 5% 5% 1/20W MF 201
2
50V
CERM 2
50V
CERM 1/16W 64 46 45 SMC_BC_ACOK R5087 470K 1 2
MF-LF 5% 1/20W MF 201
402 402
2 402
45 SMC_S5_PWRGD_VIN R5092 100K 1 2
5% 1/20W MF 201
SMC_ADC23 SMC_PACKAGE:ENG
B
46 45
R5014 10K
B
46 7 =PPVCCIO_S0_SMC 45 29 27 MEM_EVENT_L 1 2
5% 1/20W MF 201
46 45 CPU_THRMTRIP_3V3 R5017 100K 1 2
5% 1/20W MF 201
1
R5097 Notes:
100K
1% OOBD2R was OOB_TEMP, from SSD, to SMC
System (Sleep) LED Circuit 1/16W
MF-LF
402 47 6 SMC_ROMBOOT
OOBR2D was TEMP_CTL, from SMC, to SSD
2
45 SMC_VCCIO_CPU_DIV2 1
R5088
7 =PP5V_S3_SYSLED
1K
5%
S4 HPD SMC Wake Source 1

R5096
1/20W
MF
2 201
R5031 1
1 100K
R5030 1% 74 45 17 SMC_ADAPTER_EN R5085 10K 1 2
523 20 1/16W 5% 1/20W MF 201
=PP3V3_S4_SMC 1% 1% MF-LF
7 46
1/16W 1/16W
2
402 46 45 SMC_THRMTRIP R5086 10K 1 2
1
MF-LF
402 2
MF-LF
2 402 74 45 SMC_S4_WAKESRC_EN R5090 100K 1 2
5% 1/20W MF 201
R5020 92 45 35 SMC_DELAYED_PWRGD R5091 100K 1 2

5% 1/20W MF 201
100K SYS_LED_ILIM 5% 1/20W MF 201

5% 74 45 SMC_PM_G2_EN R5093 100K 1 2
1/20W 5% 1/20W MF 201
MF
2 201 SYS_LED_L_VDIV
SMC_DP_HPD_L 45
BATLOW# Isolation
OUT
Q5020 1
SSM3K15AMFVAPE
R5032 PP3V3_WLAN
D 3
1.47K 6 5 4 CRITICAL
32 6
VESM 1% 7 =PP3V3_S5_SMCBATLOW =PP3V3_SUS_SMC 7
CRITICAL
1/16W
MF-LF D B E Q5030 45 32 6 WIFI_EVENT_L R5089 10K 1 2
402 2 DMB54D0UV 5% 1/20W MF 201
Q5040
SOT-563 SSM3K15AMFVAPE
=PP3V3_S4_SMC 7 46 R5040
1
A SYS_LED_L VESM
DP_A_EXT_HPD
1 G S 2
1 Q1
Q2
100K
5%
CRITICAL
1
87 86 IN R5082 1/20W
MF
PAGE TITLE
G
100K
5%
1/20W
S G C
201 2
SMC Support
MF DRAWING NUMBER SIZE
S
SMC_BATLOW_L PM_BATLOW_L
2
201 1 2 3 74 45 IN OUT 17
2
53 IN =PSOC_WAKE_L SMC_PME_S4_WAKE_L OUT 45 REVISION
Internal 20K pull-up on
MAKE_BASE=TRUE
R5041 PM_BATLOW_L in PCH.
R
3.0.0
32 IN =BT_WAKE_L 45 IN SMC_SYS_LED SYS_LED_ANODE OUT 6 41
1
0
2
5% NOSTUFF PROPRIETARY PROPERTY OF APPLE INC.
1/16W THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF-LF
50 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LPC+SPI Connector
CRITICAL
LPCPLUS_CONN:YES
J5100
55909-0374
M-ST-SM
7 =PP3V3_S5_LPCPLUS 31 32
7 =PP5V_S0_LPCPLUS
1 2 LPC_CLK33M_LPCPLUS IN 6 24 96
96 89 45 16 6 BI LPC_AD<0> 3 4 LPC_AD<2> BI 6 16 45 89 96
96 89 45 16 6 BI LPC_AD<1> 5 6 LPC_AD<3> BI 6 16 45 89 96
7 8
47 6 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 6 19 56
47 6 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 6 47
96 89 45 16 6 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 6 47
45 17 6 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 6 16 45
46 45 6 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 6 17 45
24 6 IN LPCPLUS_RESET_L 19 20 SMC_TDI OUT 6 45 46
46 45 6 OUT SMC_TDO 21 22 SMC_TCK OUT 6 45 46
TP_SMC_TRST_L 23 24 SMC_RESET_L OUT 6 45 46 65
TP_SMC_MD1 25 26 SMC_ROMBOOT OUT 6 46
46 45 6 IN SMC_TX_L 27 28 SMC_RX_L OUT 6 45 46

29 30 LPCPLUS_GPIO OUT 6 19
C 33 34 C
516S0573
SPI Bus Series Termination

SPI_ALT_MISO 6 47
SPI_ALT_MOSI 6 47
SPI_ALT_CLK 6 47
SPI_ALT_CS_L 6 47
LPCPLUS_R:YES LPCPLUS_R:YES LPCPLUS_R:YES LPCPLUS_R:YES

1 1 1 1
R5128 R5127 R5126 R5125 PLACE_NEAR=J5100.14:5mm
0 47 47 47 PLACE_NEAR=J5100.12:5mm
5% 5% 5% 5% PLACE_NEAR=J5100.9:5mm
1/16W 1/16W 1/16W 1/16W PLACE_NEAR=J5100.11:5mm
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
2 2 2 2
PLACE_NEAR=U1800.AV3:5mm R5110 R5120

15 47
96 16 IN SPI_CS0_R_L 1 2 96 SPI_CS0_L 1 2 SPI_MLB_CS_L OUT 46 56
5% 5% PLACE_NEAR=R5125.2:5mm
B
1/16W 1/16W
B PLACE_NEAR=U1800.BA2:5mm R5111
15
MF-LF
402 R5121
47
MF-LF
402
96 16 IN SPI_CLK_R 1 2 96 SPI_CLK 1 2 SPI_MLB_CLK OUT 46 56
1/16W 1/16W
MF-LF MF-LF
PLACE_NEAR=U1800.AY1:5mm R5112 402 R5122 402
15 47
96 16 IN SPI_MOSI_R 1 2 96 SPI_MOSI 1 2 SPI_MLB_MOSI OUT 46 56
1/16W 1/16W
MF-LF MF-LF
402 R5123 402
15
96 16 OUT SPI_MISO 1 2 SPI_MLB_MISO IN 46 56
5% PLACE_NEAR=U6100.2:5mm
1/16W
MF-LF
402
PAGE TITLE
LPC+SPI Debug Connector

DRAWING NUMBER SIZE

REVISION
R
3.0.0
51 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH SMBus "0" Connections SMC "0" SMBus Connections SMC "5" SMBus Connections
48 7 =PP3V3_S0_SMBUS_PCH 7 =PP3V3_S0_SMBUS_SMC_0_S0 7 =PP3V42_G3H_SMBUS_SMC_5
R5200 1
1
R5250 1
1
R5280 1
1
Panther Point R5201 SO-DIMM "A" SMC R5251 GPU Temp (Ext) SMC R5281 Battery Charger
1K 1K 4.7K 4.7K 2.0K 2.0K
5% 5% J2900 5% 5% 5% 5%
U1800 1/16W 1/16W U4900 1/16W 1/16W EMC1414-A: U5550 U4900 1/16W 1/16W ISL6258 - U7000
MF-LF MF-LF (Write: 0xA0 Read: 0xA1) MF-LF MF-LF MF-LF MF-LF
(MASTER) 402
2 2
402 (MASTER) 402
2 2
402 (Write: 0x98 Read: 0x99) (MASTER) 402
2 2
402 (Write: 0x12 Read: 0x13)
99
SMBUS_PCH_CLK =I2C_SODIMMA_SCL SMB_0_S0_CLK SMBUS_SMC_0_S0_SCL =I2C_GPUTHMSNS_SCL SMB_5_CLK SMBUS_SMC_5_G3_SCL =SMBUS_CHGR_SCL
D
96 16 27 45 51 65
D 96 16
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
=I2C_SODIMMA_SDA 27 SMB_0_S0_DATA
MAKE_BASE=TRUE
99
45 SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
=I2C_GPUTHMSNS_SDA 51 SMB_5_DATA
MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SDA
MAKE_BASE=TRUE
=SMBUS_CHGR_SDA 65
VRef DACs SO-DIMM "B" GPU Temp (Int) Battery

J3100
U3300 KEPLER: U8000 J6955
(Write: 0xA4 Read: 0xA5) Battery
(Write: 0x98 Read: 0x99) (Write: 0x82 Read: 0x83) (See Table)
Battery Manager - (Write: 0x16 Read: 0x17)
31 =I2C_VREFDACS_SCL =I2C_SODIMMB_SCL 29 GPU_SMB_CLK_R 82 =SMBUS_BATT_SCL 64
Battery LED Driver - (Write: 0x36 Read: 0x37)
31 =I2C_VREFDACS_SDA =I2C_SODIMMB_SDA 29 GPU_SMB_DAT_R 82 Battery Temp - (Write: 0x92 Read: 0x93) =SMBUS_BATT_SDA 64
Margin Control
U3301 SMC "3" SMBus Connections
(Write: 0x30 Read: 0x31)
31 =I2C_PCA9557D_SCL 7 =PP3V3_S3_SMBUS_SMC_3
31 =I2C_PCA9557D_SDA
1 1
SMC R5290 R5291 Sensor ADC A
4.7K 4.7K
5% 5%
U4900 1/16W 1/16W U5930
SATA Redriver LED BACKLIGHT MF-LF MF-LF
(MASTER) 402 2
2 402
U9701
U4510 99
(WRITE: 0x58 READ: 0x59) SMB_3_CLK 45 SMBUS_SMC_3_SCL =I2C_SMC_ADCS_SCL 104
C 41
(Write: 0xB6 Read: 0xB7)
=SATARDRVR_I2C_SCL =I2C_BKL_1_SCL 90 SMC "2" SMBus Connections SMB_3_DATA 99

45
MAKE_BASE=TRUE
SMBUS_SMC_3_SDA
MAKE_BASE=TRUE
=I2C_SMC_ADCS_SDA 104
C
NOTE: SMC RMT bus remains powered and may be active in S3 state
41 =SATARDRVR_I2C_SDA =I2C_BKL_1_SDA 90
7 =PP3V3_S3_SMBUS_SMC_2_S3
XDP Connectors Mikey SMC R5270 1 1

R5271 Trackpad T29 SMBus Connections
1K 1K
J2500 & J2550 U6880 5% 5%
U4900 1/16W 1/16W J5800
(MASTER) (Write: 0x72 Read: 0x73) MF-LF MF-LF
(MASTER) 402 2 (Write: 0x90 Read: 0x91) =PP3V3_S0_T29I2C
2 402
7
23 =SMBUS_XDP_SCL =I2C_MIKEY_SCL 63
SMB_2_S3_CLK SMBUS_SMC_2_S3_SCL =I2C_TPAD_SCL 54
MAKE_BASE=TRUE
23 =SMBUS_XDP_SDA =I2C_MIKEY_SDA 63
R5230 1
SMB_2_S3_DATA SMBUS_SMC_2_S3_SDA =I2C_TPAD_SDA 1
MAKE_BASE=TRUE
54
T29 IC R5231 T29 Port A MCU
4.7K 4.7K
SDRVI2C:SB 5% 5%
1
U3600 1/16W 1/16W J9330
SDRVI2C:SB
R5236 (MASTER)
MF-LF
402
MF-LF
402 (Write: 0x26 Read: 0x27)
1
0 DP SDRV "A" J3401 2 2
R5237 5%
1/20W ALS 98 33 I2C_TBT_SCL =I2C_TBTAMCU_SCL 87
0 MF U9310 (Write: 0x72 Read: 0x73) MAKE_BASE=TRUE
5%
2 201 I2C_TBT_SDA =I2C_TBTAMCU_SDA
1/20W (Write: 0x94 Read: 0x95) Lid Angle Detect 98 33 87
MF MAKE_BASE=TRUE
201 2 (Write: 0x32 Read: 0x33)
48 I2C_DPSDRVA_SCL =I2C_DPSDRVA_SCL 48 87
MAKE_BASE=TRUE =I2C_ALS_SCL 32
48 I2C_DPSDRVA_SDA =I2C_DPSDRVA_SDA 48 87 SDRVI2C:MCU

MAKE_BASE=TRUE =I2C_ALS_SDA 32 SDRVI2C:MCU
R5234 1 1
0 R5235
5% 0 DP SDRV "A"
1/20W 5%
MF 1/20W
U9310
B PCH "SMLink 0" Connections Digital SMS
201 2 MF
2 201
(Write: 0x94 Read: 0x95) B
LIS331DLH: U5920
48 I2C_DPSDRVA_SCL =I2C_DPSDRVA_SCL 48 87
(Write: 0x30 Read: 0x31) MAKE_BASE=TRUE
48 7 =PP3V3_S0_SMBUS_PCH
48 I2C_DPSDRVA_SDA =I2C_DPSDRVA_SDA 48 87
=I2C_SMC_SMS_SCL 55 MAKE_BASE=TRUE
=I2C_SMC_SMS_SDA 55
R5210 1
1
Panther Point R5211
8.2K 8.2K
5% 5%
U1800 1/16W 1/16W
MF-LF MF-LF
(MASTER) 402
2 2
402
SML_PCH_0_CLK
96 16
MAKE_BASE=TRUE SMC "1" SMBus Connections
96 16 SML_PCH_0_DATA
MAKE_BASE=TRUE
7 =PP3V3_S0_SMBUS_SMC_1_S0
R5260 1
1
SMC R5261 CPU Temp
4.7K 4.7K
PCH "SMLink 1" Connections U4900
5%
1/16W
5%
1/16W EMC1414-A: U5570
MF-LF MF-LF
(MASTER) 402
2 2
402 (Write: 0x98 Read: 0x99)
48 7 =PP3V3_S0_SMBUS_PCH 99
SMB_1_S0_CLK 45 SMBUS_SMC_1_S0_SCL =I2C_CPUTHMSNS_SCL 51
MAKE_BASE=TRUE
99
NO STUFF NO STUFF SMB_1_S0_DATA 45 SMBUS_SMC_1_S0_SDA =I2C_CPUTHMSNS_SDA 51
MAKE_BASE=TRUE
R5220 1
1
Panther Point R5221
8.2K 8.2K R5223
5% 5%
A U1800
1/16W
MF-LF
402
2 2
1/16W
MF-LF
402
0
5%
1/16W
MF-LF T29 Temp
402 PAGE TITLE
SML_PCH_1_CLK 1 2
96 16
MAKE_BASE=TRUE EMC1412-A: U5520 SMBus Connections
96 16 SML_PCH_1_DATA 1 2 (Write: 0x90 Read: 0x91) DRAWING NUMBER SIZE
MAKE_BASE=TRUE
R5222 =I2C_T29THMSNS_SCL Apple Inc. 051-9585 D
0 REVISION
5%
1/16W
MF-LF
=I2C_T29THMSNS_SDA
R
3.0.0
SMLink 1 is slave port to 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
access PCH & CPU via PECI. PROPRIETARY PROPERTY OF APPLE INC.
52 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU Core Load Side Current Sense (IG0C)
Gain: 130.2x, EDP: 25 A
Rsense: 0.001 (R8940)
Gain Number needs Updating! PBUS Voltage Sense & Enable (VP0R)
V across Rsense: 25 mV NOSTUFF
PLACE_NEAR=U4900.B2:5MM
Gain needed: 132.0x CRITICAL
R5359
4.53K
84 IN GFXIMVP6_IMON 1 2 Q5300
1% NTUD3169CZ
1/20W SOT-963
MF N-CHANNEL
201 6 PBUSVSENS_EN_L
104 103 50 49 7 =PP3V3_S0_ISNS
LOADISNS:YES Enables PBUS VSense D
divider when in S0.
1
C5350 1
D LOADISNS:YES
CRITICAL
0.1UF
20%
10V 74 IN =PBUSVSENS_EN 2 G
R5302
100K
1%
D
U5350 2 CERM S 1/16W
MF-LF
402
5 OPA333DCKG4 402 2
1 1
+ SC70-5 R5358 PLACE_NEAR=U4900.A3:5MM
V+ 4.53K 3 PBUS_S0_VSENSE
4 ISNS_GPU_IOUT 1 2 SMC_GPU_ISENSE OUT 46
1% D
3 V- 1/20W
R5303 1
- MF 1
C5358
2
201
0.22UF G
27.4K
7 =PPBUS_S0_VSENSE 5 1%
ISNS_GPU_INV LOADISNS:YES 20%
6.3V LOADISNS:YES S 1/20W
PLACE_NEAR=U4900.B2:5MM 2 X5R MF
1 0201 4
201
2
Rthevenin = 4573 Ohms
R5350
499K P-CHANNEL SMC_PBUS_VSENSE 46
OUT
1%
1/20W
MF R5357 R5301 1 PLACE_NEAR=U4900.A3:5MM
201 1M GND_SMC_AVSS 45 46 49 50 103 100K R5304
1
2 1 2 1%
1
C5304
LOADISNS:YES 1/16W 5.49K 0.22UF
1% LOADISNS:YES MF-LF 1%
20%
1/20W 402 1/20W
MF 2 6.3V
MF 2 X5R
SIGNAL_MODEL=EMPTY 201 201 2 0201
SIGNAL_MODEL=EMPTY PBUSVSENS_EN_L_DIV GND_SMC_AVSS 45 46 49 50 103
PLACE_NEAR=U4900.A3:5MM
CPU VCCIO 1.05V Load Side Current Sense (IC1C)

Gain: 161.5x, EDP: 20 A
Rsense: 0.001 (R7640)
DC-In Voltage Sense & Enable (VD0R)
104 103 50 49 7 =PP3V3_S0_ISNS
V across Rsense: 20 mV
CRITICAL
Gain needed: 165x
LOADISNS:YES Enables DC-In VSense
LOADISNS:YES CRITICAL Q5310
LOADISNS:YES NTUD3169CZ
SIGNAL_MODEL=EMPTY U5320 PLACE_NEAR=U4900.A6:5MM divider when AC present. SOT-963
R5323
C 101 71 IN CPUVCCIOS0_CS_P 1
6.19K
2 101 ISNS_CPUVCCIO_R_P
1
+
V+
5 OPA333DCKG4
SC70-5 R5327
4.53K R5393
NOSTUFF N-CHANNEL 6 DCINVSENS_EN_L C
1% 4 ISNS_CPUVCCIO_IOUT 1 2 SMC_CPUVCCIO_ISENSE 46 0 DCIN_VSENSE_EN D
OUT =CHGR_ACOK
1/20W
MF 1%
65 46 IN 1 2
R5312 1
201 3 V- 1/20W
PLACE_NEAR=U4900.A6:5MM
5% 100K
- MF 1
C5327 1/20W 2 G
R5324 2
201 MF S
1%
1/16W
6.19K 0.22UF 74 PM_SUS_EN 201 MF-LF
CPUVCCIOS0_CS_N 1 2 ISNS_CPUVCCIO_R_N 20% IN
101 71 IN 6.3V LOADISNS:YES R5394 402 2
2 1
X5R
1%
0201
0 PLACE_NEAR=U4900.F1:5MM
1/20W 1
R5325 1 2 3 DCIN_S5_VSENSE
MF
201 1M 5%
D
1% 1/20W
1
LOADISNS:YES 1/20W
R5326 MF
R5313
MF 201
SIGNAL_MODEL=EMPTY 1M GND_SMC_AVSS 27.4K
2 201
45 46 49 50 103
1 2 7 =PPDCIN_S5_VSENSE 5 G 1%
LOADISNS:YES S 1/20W
1% LOADISNS:YES MF
1/20W 201 2 Rthevenin = 4573 Ohms
MF 4
201
P-CHANNEL SMC_DCIN_VSENSE 46
OUT
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
R5311 1 PLACE_NEAR=U4900.F1:5MM
100K 1
1%
R5314 1
C5314
5.49K
CPU VCCSA Load Side Current Sense (IC2C) 1/16W
MF-LF
402
1%
1/20W
0.22UF
20%
2 6.3V
Gain: 549x, EDP: 6A MF 2 X5R
201 2 0201
Rsense: 0.001 (R7140)
104 103 50 49 7 =PP3V3_S0_ISNS
V across Rsense: 6mV LOADISNS:YES PDCINVSENS_EN_L_DIV GND_SMC_AVSS 45 46 49 50 103
Gain needed: 550x 1

C5360 PLACE_NEAR=U4900.F1:5MM
LOADISNS:YES LOADISNS:YES 0.1UF
CRITICAL
20%
SIGNAL_MODEL=EMPTY 10V LOADISNS:YES
U5360 2 CERM PLACE_NEAR=U4900.C2:5MM
R5363 402
VCCSAS0_CS_P 1
1.82K
2 101 ISNS_CPUVCCSA_R_P
1 +
5 OPA333DCKG4
SC70-5 R5367 CPU Core Voltage Sense (VC0C) CPU VCCSA Voltage Sense (VC2C)
101 66 IN V+ 4 ISNS_CPUVCCSA_IOUT
4.53K
1 2 SMC_CPUVCCSA_ISENSE
B
1%
B OUT 46
1/16W XW5320 R5320 XW5380
MF-LF 1%
402 3 V- 1/20W
PLACE_NEAR=U4900.C2:5MM SM
4.53K
SM
- MF 1
C5367 =PPVCORE_S0_CPU 1 2 CPUVSENSE_IN 1 2 SMC_CPU_VSENSE =PPVCCSA_S0_REG 1 2
R5364 2
201
105 14 12 7 OUT 46 66 7
1.82K 0.22UF PLACE_NEAR=R7510.2:5 MM 1% PLACE_NEAR=U4900.E2:5MM PLACE_NEAR=R7140.1:5 MM

101 66 IN VCCSAS0_CS_N 1 2 ISNS_CPUVCCSA_R_N 20%
LOADISNS:YES 1/20W
1%
2
6.3V
X5R
MF
201
1
C5320
1 0201 0.22UF
1/16W
MF-LF R5365 PLACE_NEAR=U4900.E2:5MM 20%
6.3V
402 1M 2 X5R
1% 0201
LOADISNS:YES
1/16W
MF-LF
R5366
2 402
1M GND_SMC_AVSS 45 46 49 50 103 GND_SMC_AVSS 45 46 49 50 103
SIGNAL_MODEL=EMPTY 1 2
R5380
LOADISNS:YES
1% LOADISNS:YES 4.53K
1/16W CPUVCCSAVSENSE_IN 1 2 SMC_CPUVCCSA_VSENSE OUT 46
SIGNAL_MODEL=EMPTY MF-LF
402 1% PLACE_NEAR=U4900.G1:5MM
1/20W
SIGNAL_MODEL=EMPTY MF 1
C5380
AXG Core Voltage Sense (VN0C) PLACE_NEAR=U4900.G1:5MM
201
0.22UF
20%
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION XW5330
2
6.3V
X5R
SM
R5330 0201
117S0008 3 RES,100K,201 C5358,C5327,C5367 LOADISNS:NO 4.53K
70 7 =PPVCORE_S0_AXG_REG 1 2 AXGVSENSE_IN 1 2 SMC_AXG_VSENSE OUT 46 GND_SMC_AVSS 45 46 49 50 103
PLACE_NEAR=R7550.2:5 MM 1% PLACE_NEAR=U4900.C1:5MM
1/20W
MF
201
1
C5330
DDR 1.5V S3 (Memory) Current Sense (IM0C) PLACE_NEAR=U4900.C1:5MM 0.22UF
20%
6.3V
Gain: 200x, EDP: 9A 2 X5R
0201
Rsense: 0.001 (R5370)
104 103 7 =PP3V3_S3_ISNS
V across Rsense: 9 mV GND_SMC_AVSS 45 46 49 50 103
Gain needed: 336.7x 1

C5370
0.1UF
3
20%
10V
V+ 2 CERM PLACE_NEAR=U4900.B6:5MM
A
402
OUT =PP1V5_S3_DDR_ISNS
7
PLACE_NEAR=R5370.4:10MM
2 4 101 ISNS_1V5_S3_DDR_N
U5370
INA210
R5379
4.53K
GPU Core Voltage Sense (VG0C) SYNC_MASTER=J31_YONAS
PAGE TITLE
R5370 5 IN- SC70OUT 6 ISNS_1V5_S3_DDR_IOUT 1 2 SMC_MEM_ISENSE OUT 46
XW5335
0.001
1%
CRITICAL 1%
1/20W
PLACE_NEAR=U4900.B6:5MM SM
R5335
4.53K
Power Sensors: Load Side
1W
MF-1
101 ISNS_1V5_S3_DDR_P 4 IN+ REF 1 MF
201
1
C5379 7 =PPVCORE_GPU_REG 1 2 GPUVSENSE_IN 1 2 SMC_GPU_VSENSE OUT 46 DRAWING NUMBER SIZE
0612
1 3 PLACE_NEAR=R5370.3:10MM
0.22UF
20%
PLACE_NEAR=R8940.1:5 MM 1%
1/20W
GND 2
6.3V MF 1
C5335 REVISION
=PP1V5_S3_DDR_ISNS_R X5R 201
7 IN 0.22UF R
3.0.0
2
0201
PLACE_NEAR=U4900.B1:5MM 20%
2
6.3V
X5R NOTICE OF PROPRIETARY PROPERTY: BRANCH
0201
GND_SMC_AVSS 45 46 49 50 103 GND_SMC_AVSS 45 46 49 50 103 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
53 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU High Side Current Sense (IC0R)
Gain: 50x, EDP: 22.8 A
Rsense: 0.003 (R5400)
V across Rsense: 68.4 mV
Gain needed: 48.25x
104 103 50 49 7 =PP3V3_S0_ISNS

CPU Core Load Side Current Sense (IC0C)
Gain: 136.1x, EDP: 97 A
1 C5401 Rsense: 3x of 0.00075 (R7510, R7520. R7530), Rsum: 0.00025.
0.1UF V across Rsense: 24.25 mV
3
20%
10V
D 7 OUT =PPVIN_S5_HS_COMPUTING_ISNS
V+
U5400
2 CERM
402
R5403 101 70 69 IN CPUIMVP_ISNS1_P 1

R5456
5.23K
2
Gain needed: 136.1x
D
INA213 4.53K PLACE_NEAR=R7510.3:5MM 1%
2 4 101 ISNS_HS_COMPUTING_N 6 HS_COMPUTING_IOUT
R5400 5 IN- SC70 OUT 1 2 SMC_CPU_HI_ISENSE OUT 46 SIGNAL_MODEL=EMPTY
LOADISNS:YES
1/20W
MF
0.003 CRITICAL 1%
201
2% 1/20W
R5457 LOADISNS:YES
0.5W 101 ISNS_HS_COMPUTING_P 4 IN+ REF 1 MF 1
C5403 50 7 =PP3V3_S0_IMVPISNS PLACE_NEAR=U5450.5:3MM
MF 201
0.22UF 5.23K
CRITICAL 0612
1 3 101 70 69 IN CPUIMVP_ISNS2_P 1 2
GND
PLACE_NEAR=U4900.B5:5MM 20%
6.3V 1%
LOADISNS:YES 1 C5450
2 PLACE_NEAR=R7520.3:5MM CRITICAL
7 =PPVIN_S5_HS_COMPUTING_ISNS_R X5R
SIGNAL_MODEL=EMPTY 1/20W LOADISNS:YES 0.1UF
IN
2
0201 MF 20%
LOADISNS:YES 10V
201
U5450 2 CERM
R5458 R5452 OPA333DCKG4 402
5
5.23K 3.57K 1
+ R5451
CPUIMVP_ISNS3_P 1 2 101 CPUIMVP_ISNS_P 1 2 101 CPUIMVP_ISUM_R_P SC70-5
GND_SMC_AVSS 45 46 49 50 103
101 70 69 IN V+ 4.53K
PLACE_NEAR=R7530.3:5MM 1% 1% 4 CPUIMVP_ISUM_IOUT 1 2 SMC_CPU_ISENSE OUT 46
SIGNAL_MODEL=EMPTY 1/20W 1/16W
MF MF-LF 1%
LOADISNS:YES
201 402 3 V- 1/20W
- MF 1
C5451
GPU High Side Current Sense (IG0R) R5470
5.23K
R5453
3.57K
2
201
0.22UF LOADISNS:YES
Gain: 200x, EDP: 5.2 A (Kepler) 101 70 69 IN CPUIMVP_ISNS1_N 1 2 101 CPUIMVP_ISNS_N 1 2 CPUIMVP_ISUM_R_N LOADISNS:YES 20%
6.3V PLACE_NEAR=U4900.E1:5MM
PLACE_NEAR=U4900.E1:5MM 2 X5R
Rsense: 0.003 (R5410) PLACE_NEAR=R7510.4:5MM 1% 1%
1 0201
SIGNAL_MODEL=EMPTY
LOADISNS:YES
1/20W
MF
1/16W
MF-LF R5454
201 402 732K
Gain needed: 211.54x (Kepler) R5471 1%
LOADISNS:YES 1/16W
R5455
5.23K MF-LF
101 70 IN CPUIMVP_ISNS2_N 1 2
2
402 732K GND_SMC_AVSS 45 46 49 50 103
1 2
104 103 50 49 7 =PP3V3_S0_ISNS PLACE_NEAR=R7520.4:5MM 1% LOADISNS:YES
SIGNAL_MODEL=EMPTY 1/20W SIGNAL_MODEL=EMPTY 1% LOADISNS:YES
LOADISNS:YES MF 1/16W SIGNAL_MODEL=EMPTY
1
C5411 201 MF-LF
402
0.1UF R5472
3
20% 5.23K
10V CPUIMVP_ISNS3_N 1 2
V+ 2 CERM 101 70 IN
402
7 OUT =PPVIN_S5_HS_GPU_ISNS PLACE_NEAR=R7530.4:5MM 1%
U5410 R5413 SIGNAL_MODEL=EMPTY 1/20W
MF
LOADISNS:YES
INA210 4.53K 201
C R5410
0.003
2%
2 4 101 ISNS_HS_GPU_N 5 IN- SC70
CRITICAL
OUT 6 HS_GPU_IOUT 1
1%
1/20W
2 SMC_GPU_HI_ISENSE
OUT 46
C
0.5W
MF
101 ISNS_HS_GPU_P 4 IN+ REF 1 MF
201
1
C5413
CRITICAL 0612
1 3
0.22UF
20%
AXG Core Load Side Current Sense (IN0C)
GND PLACE_NEAR=U4900.F2:5MM
2
6.3V
Gain: 185.5x, EDP: 46 A
=PPVIN_S5_HS_GPU_ISNS_R X5R PLACE_NEAR=U4900.F2:5MM
7 IN
2
0201
Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375.
Gain needed: 191.3x
GND_SMC_AVSS 45 46 49 50 103
OTHER High Side Current Sense (IO0R) R5466 50 7 =PP3V3_S0_IMVPISNS

LOADISNS:YES
Gain: 50x, EDP: 10.3 A 5.23K
101 70 IN CPUIMVP_ISNS1G_P 1 2
Rsense: 0.005 (R5440)
0.5%
LOADISNS:YES 1
C5460
PLACE_NEAR=R7550.3:5MM CRITICAL
V across Rsense: 51.5 mV SIGNAL_MODEL=EMPTY 1/16W LOADISNS:YES 0.1UF
MF 20%
LOADISNS:YES 10V
Gain needed: 64.1x 402
U5460 2 CERM
R5468 R5462 OPA333DCKG4 402
5.23K 1.33K 1 5
CPUIMVP_ISNS2G_P 1 2 101 CPUIMVP_ISNS1G_R_P 1 2 101 CPUIMVP_ISUMG_R_P
+ SC70-5 R5461
104 103 50 49 7 =PP3V3_S0_ISNS
101 70 IN V+ 4.53K
PLACE_NEAR=R7560.3:5MM 0.5% 1% 4 CPUIMVP_ISUMG_IOUT 1 2 SMC_AXG_ISENSE OUT 46
SIGNAL_MODEL=EMPTY 1/16W 1/16W
1
C5431 LOADISNS:YES MF
402
MF-LF
402 3 V- 1%
1/20W
0.1UF - MF 1
C5461
R5467 R5463 2
3
20% 201
10V
5.23K 1.33K 0.22UF LOADISNS:YES
V+ 2 CERM CPUIMVP_ISNS1G_N CPUIMVP_ISUMG_R_N 20%
402 101 70 IN 1 2 101 CPUIMVP_ISNS1G_R_N 1 2 LOADISNS:YES 6.3V PLACE_NEAR=U4900.H1:5MM
7 OUT =PPVIN_S5_HS_OTHER_ISNS PLACE_NEAR=U4900.H1:5MM 2
U5430 R5433 PLACE_NEAR=R7550.4:5MM 0.5% 1%
1
X5R
0201
INA213 4.53K
SIGNAL_MODEL=EMPTY
LOADISNS:YES
1/16W
MF
1/16W
MF-LF R5464
2 4 101 ISNS_HS_OTHER_N 6 HS_OTHER_IOUT 732K
R5430 5 IN- SC70 OUT 1 2 SMC_OTHER_HI_ISENSE OUT 46 402 402
0.005 1% R5469 1%
2%
CRITICAL
1/20W 5.23K LOADISNS:YES
1/16W
MF-LF
R5465
0.5W ISNS_HS_OTHER_P 4 IN+ REF 1 1
C5433 CPUIMVP_ISNS2G_N 1 2 732K GND_SMC_AVSS
B
MF
B
101
MF 201
101 70 IN 2 402 1 2
45 46 49 50 103
CRITICAL 0612 0.22UF PLACE_NEAR=R7560.3:5MM 0.5%

1 3 20%
GND PLACE_NEAR=U4900.A5:5MM 6.3V PLACE_NEAR=U4900.A5:5MM SIGNAL_MODEL=EMPTY 1/16W LOADISNS:YES 1% LOADISNS:YES
2 LOADISNS:YES MF SIGNAL_MODEL=EMPTY 1/16W SIGNAL_MODEL=EMPTY
=PPVIN_S5_HS_OTHER_ISNS_R X5R 402 MF-LF
7 IN
2
0201 402
GND_SMC_AVSS 45 46 49 50 103
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
117S0008 2 RES,100K,201 C5451,C5461 LOADISNS:NO
Charger (BMON Prod) Current Sense (IPBR) DC-In (AMON) Current Sense (ID0R)
Charger Gain: 36x Charger Gain: 20x
Rsense: 0.010 (R7050) Rsense: 0.020 (R7020)
Max Measured I: 9.2 A Max Measured I: 8.3 A
PLACE_NEAR=U4900.A4:5MM PLACE_NEAR=U4900.B3:5MM
R5422 R5441
45.3K 4.53K
65 IN CHGR_BMON 1 2 SMC_BMON_ISENSE OUT 46 65 IN CHGR_AMON 1 2 SMC_DCIN_ISENSE OUT 46
1% 1%
1/20W 1/20W
A MF
201 1
C5422
0.022UF
MF
201 1
C5441
0.22UF PLACE_NEAR=U4900.B3:5MM
10% 20% PAGE TITLE
6.3V 6.3V
2 2
X5R-CERM
0201 PLACE_NEAR=U4900.A4:5MM
X5R
0201 Power Sensors: High Side, CPU, AXG
DRAWING NUMBER SIZE

GND_SMC_AVSS 45 46 49 50 103 GND_SMC_AVSS 45 46 49 50 103 REVISION
R
3.0.0
54 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Thermal Sensor A:
GPU Proximity, GPU Die, Left Heat Pipe, Right Fin Stack
I2C Write: 0x98, I2C Read: 0x99
R5550
47
7 =PP3V3_S0_GPUTHMSNS 1 2 PP3V3_S0_GPUTHMSNS_R
5% MIN_NECK_WIDTH=0.2 mm
1/20W VOLTAGE=3.3V 1
C5550
D
MF
0.1UF
D
201
10%
2
10V R5551 1 1
R5552
101 81 BI GPU_TDIODE_P X5R-CERM
10K 10K
Thermal Diode: GPU Die 1
0201
5%
1/20W
5%
1/20W
VDD MF MF
Placement Note: C5510 1
201
2 2
201
None. 2200PF U5550

10%
10V
EMC1414
X7R-CERM 2 DFN
0201 2 7 GPUTHMSNS_THM_L
DP1 THERM*/ADDR
SIGNAL_MODEL=EMPTY
101 81 GPU_TDIODE_N PLACE_NEAR=U5550.3:5MM 3 DN1 ALERT* 8 GPUTHMSNS_ALERT_L
BI
GPUTHMSNS_D_P 4 9 =I2C_GPUTHMSNS_SDA
101 DP2 SMDATA BI 48
PLACE_NEAR=Q5501.2:5MM PLACE_NEAR=Q5503.3:5MM 10
Q5501 3 5 DN2 SMCLK =I2C_GPUTHMSNS_SCL BI 48
C5552 1
GND
1 C5501 BC846BMXXH
SOT732-3
2
CRITICAL
1 C5503 Q5503 1 2200PF
THRM_PAD
PLACE_SIDE=BOTTOM
22PF PLACE_SIDE=BOTTOM 22PF 10% 6 11
5% 1 5% BC846BMXXH 10V
2
50V 50V SOT732-3 X7R-CERM
NOSTUFF 2 NOSTUFF 2
CERM
402
CERM
402 2 CRITICAL
SIGNAL_MODEL=EMPTY
0201
Thermal Sensor: GPU Proximity
PLACE_NEAR=Q5501.3:5MM 3 PLACE_NEAR=Q5503.2:5MM PLACE_NEAR=U5550.5:5MM
101 GPUTHMSNS_D_N Placement Note:
Place U5550 on bottom side under GPU
Thermal Diode: Right Fin Stack Thermal Diode: Left Heat Pipe
Placement Note: Placement Note:
Place Q5501 on the bottom side, Place Q5503 under the Left Heat Pipe,
close to the Right Fin Stack. near GPU.
C C
Thermal Sensor B:
CPU Proximity, Memory Proximity, T29/PCH Proximity, LVDS Proximity (Airflow)
I2C Write: 0x98, I2C Read: 0x99
R5570
47
7 =PP3V3_S0_CPUTHMSNS 1 2 PP3V3_S0_CPUTHMSNS_R
1/16W
MF-LF
VOLTAGE=3.3V 1 C5570
402 0.1uF
20%
10V
2 CERM R55711 1
R5572
101 CPUTHMSNS_D1_P 10K 10K
Thermal Diode: Memory Proximity PLACE_NEAR=Q5505.3:5MM PLACE_NEAR=U5570.2:5MM 1
402
5%
1/16W
5%
1/16W
3 VDD MF-LF MF-LF
Placement Note: 402 2 2 402
Place Q5505 on the right side of the DIMM
1
C5505 Q5505 1 C5571 1
U5570
22PF 0.0022uF EMC1414
connector. 5% BC846BMXXH SIGNAL_MODEL=EMPTY 10%
50V 50V DFN
NOSTUFF SOT732-3
2 CERM CERM 2 2 7 CPUTHMSNS_THM_L
402 2 CRITICAL 402 DP1 THERM*/ADDR
PLACE_NEAR=Q5505.2:5MM PLACE_NEAR=U5570.3:5MM 3 8
101 CPUTHMSNS_D1_N DN1 ALERT* CPUTHMSNS_ALERT_L
CPUTHMSNS_D2_P 4 9 =I2C_CPUTHMSNS_SDA
101 DP2 SMDATA BI 48
PLACE_NEAR=Q5502.2:5MM PLACE_NEAR=Q5504.3:5MM PLACE_NEAR=U5570.4:5MM

3 5 10 =I2C_CPUTHMSNS_SCL
Q5502 DN2 SMCLK BI 48
1
C5502 BC846BMXXH 2 1
C5504 C5590 1 GND THRM_PAD
22PF
SOT732-3 CRITICAL
22PF Q5504 1
0.0022uF 6 11
PLACE_SIDE=BOTTOM
5% 1 PLACE_SIDE=BOTTOM 5% 10%
BC846BMXXH SIGNAL_MODEL=EMPTY
50V 50V SOT732-3 50V
NOSTUFF 2 NOSTUFF 2 CERM 2
CERM CERM
Thermal Sensor: CPU Proximity
B 402
PLACE_NEAR=Q5502.3:5MM 3 101 CPUTHMSNS_D2_N
402
PLACE_NEAR=Q5504.2:5MM
2 CRITICAL
402
Placement Note:
B
Place U5570 on bottom side under CPU
Thermal Diode: LVDS Prox (Airflow) Thermal Diode: T29/PCH Proximity
Placement Note: Placement Note:
Place Q5502 on the bottom side, Place between the T29 and PCH.
close to the LVDS connector. Place side is either side.
Thermal Sensor: T29 Die
TP_TBT_THERMDP TBT_THERMDP
MAKE_BASE=TRUE
1
R5520
10K
5%
1/16W
MF-LF
402
A
2
1 2 TBT_THERMDN NOSTUFF SYNC_MASTER=J31_YONAS

PAGE TITLE
PLACE_SIDE=BOTTOM
XW5520
SM PLACE_NEAR=U3600.B1:2mm Thermal Sensors
DRAWING NUMBER SIZE
Note: Use GND pin B1 on U3600 for N leg.
REVISION
R
3.0.0
55 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C Left Fan Right Fan C

7 =PP5V_S0_FAN_LT 7 =PP5V_S0_FAN_RT
7 =PP3V3_S0_FAN_LT 7 =PP3V3_S0_FAN_RT
CRITICAL CRITICAL
J5650 J5660
1 78171-0004 1 78171-0004
R5650 M-RT-SM
R5660 M-RT-SM
47K 5
47K 5
5% 5%
1/16W 1/16W
MF-LF MF-LF
R5655 402 2
1 R5665 402 2
1
47K 47K
45 OUT SMC_FAN_0_TACH 1 2 6 FAN_LT_TACH 2 45 OUT SMC_FAN_1_TACH 1 2 6 FAN_RT_TACH 2
5% 3 5% 3
1/16W 1/16W
MF-LF 4 MF-LF 4
402 402
R5651 1 6 R5661 1 6
100K 100K
5% 5 5% 2
1/16W Q5660 1/16W Q5660
MF-LF MF-LF
402 2
G 2N7002DW-X-G 518S0369 402 2
G 2N7002DW-X-G 518S0369
SOT-363 SOT-363
45 SMC_FAN_0_CTL 4 S D 3 6 FAN_LT_PWM 45 SMC_FAN_1_CTL 1 S D 6 6 FAN_RT_PWM

IN IN
B B
PAGE TITLE
Fan Connectors
DRAWING NUMBER SIZE

REVISION
R
3.0.0
56 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PSOC USB CONTROLLER TMP102

IC PIN NAME
V+
CURRENT
10UA
R_SNS
2.55 KOHM 0.0255 V
V_SNS POWER
0.255E-6 W Keyboard Connector
- USB INTERFACES TO MLB
80UA 0.204 V 16.32E-6 W
- SPI HOST TO Z2
- TRACKPAD PICK BUTTONS 3V3 LDO VDD 60MA (MAX) 10 OHM 0.6 V 36E-3 W
- KEYBOARD SCANNER VOUT 60MA (MAX) 0.2 OHM 0.012 V 0.72E-3 W 54 53 7 =PP3V3_S4_TPAD NC
32
PLACE_SIDE=BOTTOM 53 7 =PP3V42_G3H_TPAD
PSOC VDD 8MA (TYP) 1.5 OHM 0.012 V 96E-6 W 30
R5704 BYPASS=U5701.49:50:11 mm
=PP3V3_S4_TPAD BYPASS=U5701.49:50:8 mm 14MA (MAX) 0.021 V 294E-6 W
D
54 53 7
2
1.5
1 PP3V3_S3_PSOC
BYPASS=U5701.49:50:5 mm
18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W 53 6 WS_KBD1
29
28
D
5% MIN_NECK_WIDTH=0.20MM
1/16W WS_KBD2 27
VOLTAGE=3.3V 53 6
MF-LF
402
1 C5704 1 C5705 1 C5706 WS_KBD3 26
53 6
100PF 0.1UF 4.7UF
R5703 1
5%
50V
10%
16V
20%
6.3V 53 6 WS_KBD4 25
2 CERM 2 X7R-CERM 2 X5R
220K WS_KBD5 24
402 402 603 53 6
5%
1/16W 53 6 WS_KBD6 23
MF-LF
402
2
53 6 WS_KBD7 22
53 6 WS_KBD8 21
46 OUT =PSOC_WAKE_L WS_KBD23 6 53
53 6 WS_KBD9 20
54 6 PICKB_L WS_KBD22 6 53
53 6 WS_KBD10 19
53 BUTTON_DISABLE WS_KBD21 6 53
WS_KBD11 18
54 6 Z2_HOST_INTN WS_KBD20 6 53
R5714 53 6
470 53 6 WS_KBD12 17
53 WS_LEFT_SHIFT_KEY WS_KBD19 6 53 53 WS_KBD15_C 1 2
WS_KBD13 16
53 6
53 WS_LEFT_OPTION_KEY WS_KBD18 6 53 1%
1/16W 53 6 WS_KBD14 15
MF-LF
56 402 6 WS_KBD15_CAP 14
55
54
53
52
51
50
49
48
47
46
45
44
43
6 WS_KBD16_NUM 13
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
WS_KBD17 12
R5715 53 6
10K 53 6 WS_KBD18 11
53 WS_CONTROL_KEY P2_3
1
P2_2 42 WS_KBD17 6 53 53 WS_KBD16N 1 2
10
53 6 WS_KBD19
54 6 Z2_KEY_ACT_L 2
P2_1 CRITICAL P2_0 41 WS_KBD16N 53 1%
1/16W WS_KBD20 9
53 6
NC
3
P4_7 OMIT P4_6 40 WS_KBD15_C 53 MF-LF
402 WS_KBD21 8
53 6
74 IN TPAD_VBUS_EN 4
P4_5 U5701 P4_4 39 WS_KBD14 6 53
53 6 WS_KBD22 7
54 6 Z2_DEBUG3 5
P4_3 CY8C24794 P4_2 38 WS_KBD13 6 53
R5710 WS_KBD23 6
53 6
54 6 Z2_RESET 6
P4_1 MLF P4_0 37 WS_KBD12 6 53 1K
SMC_ONOFF_L 1 2 6 WS_KBD_ONOFF_L 5
46 45 6 OUT
54 6 PSOC_MISO 7
P3_7 (SYM-VER2) P3_6 36 WS_KBD11 6 53
5% 4
54 6 PSOC_F_CS_L 8
P3_5 337S2983 P3_4 35 WS_KBD10 6 53
C5710 1
1/16W
MF-LF 53 6 WS_LEFT_SHIFT_KBD 3
C 54 6
54 6
PSOC_MOSI
PSOC_SCLK
9
10
P3_3
P3_1
P3_2
P3_0
34
33
WS_KBD9
WS_KBD8
6 53
6 53
0.1UF
20%
10V
2
402
53 6
53 6
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
2
1
C
CERM
54 6 Z2_MISO 11
P5_7 P5_6 32 WS_KBD7 6 53 402
54 6 Z2_CS_L 12
P5_5 P5_4 31 WS_KBD1 6 53 PLACEMENT_NOTE=NEAR J5713
31
54 6 Z2_MOSI 13
P5_3 P5_2 30 WS_KBD2 6 53
NC
54 6 Z2_SCLK 14
P5_1 P5_0 29 WS_KBD3 6 53 F-RT-SM
P7_7
P7_0
P1_0
P1_2
P1_4
P1_6
P1_7
P1_5
17 P1_3
18 P1_1
FF14-30A-R11B-B-3H
19 VSS
22 VDD
THRML
20 D+
21 D-
PAD 57
J5713
CRITICAL
15
16
23
24
25
26
27
28
6 TP_PSOC_SCL WS_KBD4 6 53 518S0637

6 TP_PSOC_SDA WS_KBD5 6 53
6 TP_PSOC_P1_3 WS_KBD6 6 53
8 TP_ISSP_SCLK_P1_1 TP_ISSP_SDATA_P1_0 8
ISSP SCLK/I2C SCL ISSP SDATA/I2C SDA

R5701 101
Z2_CLKIN 6 54
24 95
95 8 USB_TPAD_P 1 2 25 USB_TPAD_R_P TP_P7_7 6
5%
1/16W
MF-LF
402
(PP3V3_S3_PSOC) SMC Manual Reset & Isolation
R5702
1
C5702 1
C5703 1
C5701
24 101
95
100PF 0.1UF 4.7UF Left shift, option & control keys combined with power button cause SMC RESET# assertion.
95 8 USB_TPAD_N 1 2 25 USB_TPAD_R_N 5%
50V
10%
16V
20%
6.3V
2 CERM 2 X7R-CERM 2 X5R
5%
402 402 603 Keys ANDed with MSP power to isolate when MSP is not powered. No IPD on OE input pin PP3V3_S4 (symbol error).
1/16W
MF-LF
402
BYPASS=U5701.22:19:5 mm 53 7 =PP3V42_G3H_TPAD
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:11 mm
B 1
C5750
0.1UF
B
10%
CRITICAL 16V
10
2 X7R-CERM
402
VDD
TPAD Buttons Disable U5750

SLG4AP021
TQFN
53 BUTTON_DISABLE 54 53 7 =PP3V3_S4_TPAD 4 OE
(IPD)
Q5701 PLACE THESE COMPONENTS CLOSE TO J5800 OUT_1 9 WS_LEFT_SHIFT_KEY 53

SSM3K15FV D 3 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB 53 6 WS_LEFT_SHIFT_KBD 1 IN_1
(IPD)
SOD-VESM-HF OUT_2 8 WS_LEFT_OPTION_KEY 53
53 6 WS_LEFT_OPTION_KBD 2 IN_2
CRITICAL (IPD)
OUT_3 7 WS_CONTROL_KEY 53
53 6 WS_CONTROL_KBD 3 IN_3
THE TPAD BUTTONS WILL BE DISABLE (IPD)
Pull-up in U5010.
1 G S 2
WHEN THE LID IS CLOSED OUT_ALL# 6 SMC_TPAD_RST_L OUT 46
SMC_LID
LID OPEN => SMC_LID_LC ~ 3.42V
64 46 45 IN
LID CLOSE => SMC_LID_LC < 0.50V THRM
GND PAD
11
PAGE TITLE
WELLSPRING 1
DRAWING NUMBER SIZE

REVISION
R
3.0.0
57 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
D - RIPPLE TO MEET ERS D
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
TPAD:Z2
TPAD:Z2
CRITICAL
CRITICAL TPAD:Z2
L5801
3.3UH-870MA D5802 R5806
SOD-323
0
PP5V_S4_P18V5S5 1 2 P18V5S4_SW A K PP18V5_S4_R 1 2 PP18V5_Z2 6 54
IPD Flex Connector

MIN_LINE_WIDTH=0.50MM MIN_LINE_WIDTH=0.50MM MIN_LINE_WIDTH=0.50MM MIN_LINE_WIDTH=0.50MM
VLF3010AT-SM-HF 5%
R5805 MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
SWITCH_NODE=TRUE B0520WSXG
VOLTAGE=18.5V 1/16W
VOLTAGE=18.5V
0 MF-LF
7 =PP5V_S5_TPAD 2 1 PP5V_S5_P18V5S5_VIN TPAD:Z2 TPAD:Z2 402
1
5%
MIN_NECK_WIDTH=0.20MM C5818 1 R5812 CRITICAL
1/16W VOLTAGE=5V
39PF 1M
J5800
2
MF-LF 1%
402 5%
50V 1/16W
2 MF-LF 55560-0228
VIN CERM
402 TPAD:Z2 TPAD:Z2 53 7 =PP3V3_S4_TPAD M-ST-SM PP18V5_Z2 6 54
402 2
C5819 1 1
C5815
1 L U5805 FB 4 P18V5S4_FB 1UF 1000PF
2 1
TPS61045 TPAD:Z2 10% 5%

53 6 Z2_CS_L 4 3 Z2_KEY_ACT_L 6 53
QFN-1 25V 25V
X5R 2 2 NP0-C0G
NC 3 DO CTRL 5 Z2_BOOST_EN 6 54
1
R5813 603-1 402 53 6 Z2_DEBUG3 6 5 Z2_RESET 6 53
TPAD:Z2 TPAD:Z2 TPAD:Z2
TPAD:Z2 71.5K 53 6 Z2_MOSI 8 7 PSOC_F_CS_L 6 53
C5816 1 1
C5817 CRITICAL 1
1%
Z2_MISO 10 9 PICKB_L
0.1UF 2.2UF SW 8
R5811 1/16W 53 6 6 53
PGND
MF-LF
10% 10% 100K Z2_SCLK 12 11 PSOC_MISO
GND
16V 16V THRML 2
402 53 6 6 53
2 2 1%
X7R-CERM X5R PAD 1/16W 54 6 Z2_BOOST_EN 14 13 PSOC_MOSI 6 53
402 603
MF-LF
Z2_HOST_INTN 16 15 PSOC_SCLK
6
7
9
402 53 6 6 53
2
6 PP5V_S5_CUMULUS 18 17 =I2C_TPAD_SDA 48
VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM 53 6 Z2_CLKIN 20 19 =I2C_TPAD_SCL 48
22 21
C C
NOSTUFF 516S0689
L5800
FERR-120-OHM-1.5A
1 2
PIN 21 IS NC ON CUMULUS FLEX
0402-LF
PLACE_NEAR=J5800.18:3MM PIN 18 IS NC ON Z2 FLEX
NOSTUFF
1
C5800
0.1UF
20%
10V
PLACE_NEAR=J5800.18:3MM 2 CERM
402
Keyboard Backlight Driver & Detection

7 =PP5V_S0_KBDLED CRITICAL
Keyboard Backlight Connector
B L5850
10UH-0.58A-0.35OHM CRITICAL B
7 =PP3V3_S0_TPAD 1 2 KBDLED_SW
1098AS-SM
MIN_LINE_WIDTH=0.3 MM J5815
MIN_NECK_WIDTH=0.25 MM FF18-4A-R11AD-B-3H
R5853 1 C5850 1
SWITCH_NODE=TRUE F-RT-SM
1
470K 1UF
5%
10%
VIN 6 SMC_KDBLED_PRESENT_L 1
J5815 pin 1 is grounded
1/16W 10V 2
MF-LF X5R 2
3
on keyboard backlight flex
402
2 402-1 SW 3
CRITICAL
45 BI SMC_SYS_KBDLED 6 CTRL LED 5 6 KBDLED_ANODE 4
OMIT_TABLE MIN_NECK_WIDTH=0.2 MM
To detect Keyboard backlight, SMC will 1 1
tristate and read SMC_SYS_KBDLED: R5854 U5850 R5855
4.7K 10
5% LT3491 1% 518S0691
If LOW, keyboard backlight present 1/16W DFN 1/16W
MF-LF MF-LF
If HIGH, keyboard backlight not present 2
402
2
402
R5853 always stuffed, R5854 only NO STUFF CAP 4 KBDLED_CAP

grounded when KB BL flex connected. R5852 1 THRML MIN_NECK_WIDTH=0.25 MM
10K GND PAD 1
C5855 1
C5856
5%
7
2
1/16W
0.47UF 0.47UF
MF-LF
10%
50V
10%
50V PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
402 2 CERM-X5R 2 CERM-X5R
2
0603 0603
353S3085 1 IC,STLA02,1-STRING LED DRIVER,2X2DFN-6 U5850 CRITICAL
(SMC_KBDLED_PRESENT_L)
A SYNC_MASTER=J31_LINDA SYNC_DATE=07/01/2011 A
PAGE TITLE
WELLSPRING 2
DRAWING NUMBER SIZE

REVISION
R
3.0.0
58 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
7 =PP3V3_S3_SMS
BYPASS=U5920.14:13:8 mm
CRITICAL
C5926 C5922
14
1 1
1
C
10UF
20%
6.3V
X5R 2 2
0.1UF
10%
6.3V
X5R NC 2
VDD VDD_IO R5920 1
10K
R5925 1
10K
NOSTUFF
C
603 201 3 NC U5920 5% 5%
NC 1/20W 1/20W
BYPASS=U5920.14:13:8 mm R5924 1 LIS331DLH MF MF
10K LGA
201
2
201
2 R5923
5% 10 CS 8 SMS_I2C_SEL 0
1/20W RESERVED 1 2 =I2C_SMC_SMS_SDA BI 48
MF 15
201 5%
2
SDO 7 SMS_ADDR_SELECT 1/20W
MF
45 OUT SMS_INT_L 11 INT1 SDA/SDI/SDO 6 I2C_SMC_SMS_SDA_R 201
TP_SMS_INT2 9 INT2 SCL/SPC 4 I2C_SMC_SMS_SCL_R

GND R5922
R5921 1 0
5
12
13
16
1 2 =I2C_SMC_SMS_SCL IN 48
10K
338S0687 5% 5%
1/20W
1/20W
MF MF
PLACEMENT_NOTE=See schematic for orientation. 201
2
201
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)

Desired orientation when SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
placed on board bottom-side (view thru top):
NOTE: SDA and SCL have internal pull-ups to VDD_IO.
+Y
Front of system
+X
+Z (dn)
B Circle indicates pin 1 location when placed

in correct orientation
B
A SYNC_MASTER=J31_YONAS SYNC_DATE=08/11/2011 A
PAGE TITLE
Digital Accelerometer
DRAWING NUMBER SIZE

REVISION
R
3.0.0
59 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
7 =PP3V3_SUS_ROM
1 CRITICAL
R6101
8
C6100 1
3.3K 0.1UF VDD
5% 20%
1/16W 10V
MF-LF CERM 2
2 402 402 U6100
64MBIT
SOIC
47 46 IN SPI_MLB_CLK 6 SCK SI 5 SPI_MLB_MOSI IN 46 47
SST25VF064C
OMIT
47 46 IN SPI_MLB_CS_L 1 CE*
SO 2 SPI_MLB_MISO OUT 46 47
SPI_WP_L 3 WP*
47 19 6 IN SPIROM_USE_MLB 7 HOLD*
NOTE: If HOLD* is asserted
VSS
4
ROM will ignore SPI cycles.
B B
A SYNC_MASTER=K91_BEN SYNC_DATE=06/08/2010 A
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE

REVISION
R
3.0.0
61 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC
CRITICAL APPLE P/N 353S3199
L6201 =PP5V_S0_AUDIO 8 57
FERR-220-OHM
=PP1V5_S0_AUDIO 1 2 PP1V5_S0_AUDIO_DIG
7 IN
VOLTAGE=1.5V
0402 CRITICAL MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM =PP3V3_S0_AUDIO 7 57 62 63
1
C6210
Replacing 2 0402s with one 0306 4.7UF
20%
6.3V
PP4V5_AUDIO_ANALOG IN 57 63
Low ESL cap 2 X5R CRITICAL
CRITICAL
0306
1 C6216 1 C6215 1
1
C6219 C6214 C6213
D
1
1UF 0.1UF
D 60 59 57
GND_AUDIO_HPAMP MIN_LINE_WIDTH=0.50MM
10UF
20%
16V 2
C6218
0.1UF
1 1CRITICAL
C6217
10%
10V
X5R 2
10%
16V
X5R 2
0.1UF
10%
16V
2 2
10UF
20%
10V
CRITICAL
TANT-POLY 10UF 402-1 402-1 X5R X5R-CERM
63 57 IN PP4V5_AUDIO_ANALOG 2012-LLP 10%

16V
20% 402 0402-1
16V GND_AUDIO_HPAMP
24
46
25
X5R 2 2 57 59 60
9
TANT-POLY
1
C6220 MIN_LINE_WIDTH=0.20MM
402-1 2012-LLP
GND_AUDIO_CODEC
10UF MIN_NECK_WIDTH=0.15MM VD VA_REF VA_HP VA 57 58 63 MIN_NECK_WIDTH=0.2MM
1
R6210 1
C6221 20% VBIAS_DAC
10UF 10V
29 VBIAS_DAC
2.67K 2 X5R-CERM
1%
20%
10V 0402-1 CRITICAL HPOUT_L 38 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_L OUT 60 62
1/16W 2 VHP_FILTP 44 VHP_FILT+
X5R-CERM AUD_HP_PORT_R
U6201 HPOUT_R
MF-LF 40 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM OUT 60 62
0402-1
2
402 VHP_FILTM 41 VHP_FILT-
CS4206B HPREF 39 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM HPAMP_REF 59
IN
QFN
62 IN AUD_DMIC_SDA1 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 NC_AUD_LO1_LP

NC_AUD_GPIO_1 12 GPIO1/DMIC_SDA2 LINEOUT_L1- 34 NC_AUD_LO1_LN
/SPDIF_OUT2
NC_AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_R_P OUT 61 101
Feeding into Woofer amp LO1_R only
61 OUT AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_R_N OUT 61 101
Control for spk amps.

63 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_L_P OUT 61 101
CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_L_N OUT 61 101
CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_R_P OUT 61 101 Feeding into Tweeter amps

45 FLYP
LINEOUT_R2- 33 AUD_LO2_R_N OUT 61 101
C6222 1 1
C6223 43 FLYC
VL_HD - supply for HDA interface 2.2UF 2.2UF
20% 20%
42 FLYN
VL_IF - supply for GPIO, S/PDIF and DMIC 6.3V
CERM
2 2
6.3V
CERM
MICBIAS 16 AUD_CODEC_MICBIAS BI 63
402-LF 402-LF
3 VL_HD
CS4206_FLYN
VCOM 28 CS4206_VCOM MIN_LINE_WIDTH=0.20MM
1 VL_IF
VCOM - filter connection for internal quiescent voltage
C 96 16 IN HDA_BIT_CLK 6 BITCLK
LINEIN_L+
LINEIN_C-
21
22
AUD_LI_P_L
AUD_LI_REF
IN
IN
58
58
C
96 16 IN HDA_SYNC LINEIN_R+ 23 AUD_LI_P_R IN 58
R6211 10 SYNC
39
96 16 OUT HDA_SDIN0 1 2 96 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INP_L IN 63
5% 5 SDO MICIN_L- 17 AUD_MIC_INN_L IN 63

1/16W
MF-LF MICIN_R+ 19 AUD_MIC_INP_R IN 63
402 11 RESET*
96 16 IN HDA_SDOUT MICIN_R- 20 AUD_MIC_INN_R IN 63
96 16 IN HDA_RST_L
62 IN AUD_SPDIF_IN 47 SPDIF_IN
VREF+_ADC 27 CS4206_VREF_ADC
AUD_SPDIF_OUT_CHIP 48 SPDIF_OUT MIN_LINE_WIDTH=0.20MM
R6212 MIN_NECK_WIDTH=0.15MM
39
62 OUT AUD_SPDIF_OUT 1 2 DMIC_SCL 4 AUD_DMIC_CLK OUT 62
5%
1/16W
MF-LF
402 DGND THRM_PAD AGND
49
26
CRITICAL CRITICAL
1 1
C6224 C6225
1UF 10UF
1
10%
20V 2 2
20%
16V R6213
TANT POLY-TANT 100K
CASE-P3-HF CASE-B2-SM 5%
1/16W
60 59 57 GND_AUDIO_HPAMP MF-LF
2 402
63 58 57 GND_AUDIO_CODEC MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
B B
4.5V POWER SUPPLY FOR CODEC

APPLE P/N 353S2234
CRITICAL CRITICAL MIN_LINE_WIDTH=0.40MM
L6200 MIN_LINE_WIDTH=0.40MM
U6200
VOLTAGE=4.5V NOTES ON CODEC usage
FERR-220-OHM MAX8840-4.5V
VOLTAGE=5V
UDFN
57 8 IN =PP5V_S0_AUDIO 1 2 4V5_REG_IN 1 IN OUT 6 PP4V5_AUDIO_ANALOG OUT 57 63
0402
Hpamp of Codec enabled
R6202 DAC1 FSOUTPUT= 1.34VRMS
2.21K BP 4 4V5_NR
63 62 57 7 IN =PP3V3_S0_AUDIO 1 2 4V5_REG_EN 3 SHDN* DAC2/3 FSOUTPUTDIFF= 2.67VRMS
C6202 CRITICAL
1%
GND NC 5
NC DAC2/3 FSOUTPUTSE= 1.34VRMS
1/16W 0.1UF 1
C6203
MF-LF CRITICAL
2
402 CRITICAL 1 2 1UF

1
C6200 MIN_LINE_WIDTH=0.20MM 10%
1UF
1
C6201 MIN_NECK_WIDTH=0.15MM 10%
2
10V
X5R
10% 1UF 16V 402-1
10V 10% X7R-CERM
2 X5R
402-1
XW6200 2
10V
X5R
402
SM 402-1
1 2 GND_AUDIO_CODEC 57 58 63
A SYNC_MASTER=J31_AUDIO SYNC_DATE=10/26/2011 A
PAGE TITLE
2
R6203
AUDIO: CODEC/REGULATOR
100K
1/20W
201
5%
MF
DRAWING NUMBER SIZE

XW6201
SM MIN_LINE_WIDTH=0.50MM
1
1 2 GND_AUDIO_HPAMP 57 59 60 REVISION
VOLTAGE=0V R
3.0.0
62 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS

NET RIN = 18K OHMS
FC = 0.36 HZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6300
R6300 22UF
7.87K
62 IN AUD_LI_L 1 2 AUD_LI_L_DIV 2 1 AUD_LI_P_L OUT 57
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM 1% MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1/16W 20%
MF-LF 10V
402 TANT
C SM-HF-PL
C
R6301 1
21.5K
1%
1/16W
MF-LF
402 2
CRITICAL
C6302
22UF
62 IN AUD_LI_GND 2 1 AUD_LI_REF OUT 57
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
20%
1
R6303 10V
TANT
10 SM-HF-PL
1%
1/16W
MF-LF
2 402
63 57 IN GND_AUDIO_CODEC
R6305 1
21.5K
B 1%
1/16W
MF-LF
B
402 2
CRITICAL
C6303
R6306 22UF
7.87K
62 IN AUD_LI_R 1 2 AUD_LI_R_DIV 2 1 AUD_LI_P_R OUT 57
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM 1% MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1/16W 20%
MF-LF 10V
402 TANT
SM-HF-PL
PAGE TITLE
AUDIO: LINE INPUT FILTER

DRAWING NUMBER SIZE

REVISION
R
3.0.0
63 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D EXTERNAL (HEADSET) MIC INPUT CIRCUITRY D

APN: 353S3066 as of JUly 2011
U6400 should get VDD from battery. Should be powered all the time.
CRITICAL
L6400
FERR-220-OHM VOLTAGE=3.42V
=PP3V42_G3H_AUDIO
1 2
PP3V42_G3H_CHS MIN_NECK_WIDTH=0.175 MM
7
0402
1 C6410 1
C6400 1
C6405
10UF 0.1UF 10UF
20% 10% 20%
6.3V
2 CERM-X5R 2
16V 6.3V CHS_CLAMPI
A1
X5R 2 CERM-X5R
0402-1 402 0402-1
VDD
U6400 R6403
2.21K
R6402
2.21K
R6401
1.02K
TS3A8235YFP 1 2 1 2 1 2 EXT_MIC_BIAS IN 63
C WCSP
RAMPI D4
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
C
MIN_LINE_WIDTH=0.1MM RAMPO D3
MIN_NECK_WIDTH=0.05MM CLAMPI C4 EXT_MIC_P
OUT 63
62 IN AUD_HS_MIC1_HI
CLAMPO B4 CHS_CLAMPO
NOSTUFF
B1 MIC1 MIC D2 1 C6402 1 C6401
FROM HEADSET
C6416
33PF
1 C1 MIC2 REF D1
20%
10UF
6.3V
10UF
20%
6.3V
TO MIKEY & FILTER
5% 2 CERM-X5R 2 CERM-X5R
50V
CERM 2 SCL A3 0402-1 0402-1
402
SDA A4
A2 EXT_MIC_REF OUT 63
62 AUD_HS_MIC2_HI ADDR
IN R6404
MIN_LINE_WIDTH=0.1MM NOSTUFF
GND2
GND1
MIN_NECK_WIDTH=0.05MM 0
CHS_CAP_REF
1 2
GND
5%
R6406
1/16W
CHS_SCL 0
MF-LF
HS_SCL
C3
B3
B2
C2
402 1 2 63
IN
MIN_NECK_WIDTH=0.2MM 5%
62 IN AUD_HS_MIC2_RET 1/16W
CHS_SDA MF-LF
402
62
AUD_HS_MIC1_RET MIN_NECK_WIDTH=0.2MM
IN
R6405
GND_AUDIO_HPAMP 0 R6407
60 57 1 2
0 HS_SDA
5% 1 2 63
1/16W
BI
MF-LF 5%
402 1/16W
B B
MF-LF
402
XW6400
SM
HPAMP_REF
1 2 57
OUT
I2C ADDRESSES: CHS uses SMBus 0 connections
CHS U6400 READ 0111 0111 0x77
CHS U6400 WRITE 0111 0110 0x76
PAGE TITLE
AUDIO: DETECT/MIC BIAS

DRAWING NUMBER SIZE

REVISION
R
3.0.0
64 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
62 57 AUD_HP_PORT_L
IN
CRITICAL
1
C6500
0.1UF
10%
16V
2
X7R-CERM
402
AUD_HP_ZOBEL_L
C R6500
39
1
C
5%
1/16W
MF-LF
402
2
59 57 GND_AUDIO_HPAMP
IN
1
R6510
39
5%
1/16W
MF-LF
402
2
AUD_HP_ZOBEL_R
CRITICAL
1
C6510
0.1UF
10%
16V
2
X7R-CERM
402
62 57 AUD_HP_PORT_R
IN
B B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3X MONO SPEAKER AMPLIFIERS (SSM2375) Gain Pin Gain dB

APN: 353S2958 as of July 2011
Connect to VDD 6
GAIN = +3 DB Rin=80k irrespective of gain Connect to VDD through 47k 12
1ST ORDER FC (L&R) = ~737 HZ Not connected 3
1ST ORDER FC (SUB) = ~90 HZ Connect to GND through 47k 9
Connect to GND 0
D PLACE C6611 CLOSE TO VDD PIN
D
8 PP5V_S0_AUDIO_AMP_L
CRITICAL
1 CRITICAL TWEETER with HPF FC=737Hz
CRITICAL CRITICAL C6612 1 C6611
47UF
L6610 20% 0.1UF
FERR-1000-OHM
C6613 6.3V 2 10%
TANT-POLY 16V
0.0027UF 2 X5R
CASE-A4 MIN_LINE_WIDTH=0.50 MM
1 2 1 2 402-1
AUD_LO2_L_P AUD_SPKRAMP_LIN_P CRITICAL
C2
101 57 IN
0402 NO_TEST=TRUE VDD
10% SPKRCONN_L_OUT_P OUT 6 62 101
50V
CERM
U6610
402 SSM2375
WLCSP
B1 C3
CRITICAL CRITICAL 101 SSM2375L_P IN+ OUT+
L6611 C6614 101 SSM2375L_N A1
IN- OUT- B3
FERR-1000-OHM 0.0027UF
A2 A3
1 2 1 2
SD* GAIN NC MIN_NECK_WIDTH=0.20 MM
101 57 IN AUD_LO2_L_N AUD_SPKRAMP_LIN_N
B2
SPKRCONN_L_OUT_N OUT 6 62 101
0402 NO_TEST=TRUE EDGE
10%
50V
CERM
GND
C1
61 AUD_SPKRAMP_SHUTDOWN_L 402
CRITICAL R6600 1
100K
L6601 5%
FERR-1000-OHM 1/16W
MF-LF
1 2 402 2
57 IN AUD_GPIO_3
0402
C C
PLACE C6621 CLOSE TO VDD PIN
TWEETER with HPF FC=737Hz

CRITICAL CRITICAL
C6622 1 1
C6621
CRITICAL CRITICAL 47UF 0.1UF
20% 10%
L6620 C6623 6.3V 2 2
16V
X5R MIN_LINE_WIDTH=0.50 MM
CRITICAL
C2
TANT-POLY
FERR-1000-OHM 0.0027UF CASE-A4 402-1
VDD
101 57 IN AUD_LO2_R_P 1 2
AUD_SPKRAMP_RIN_P 1 2 SPKRCONN_R_OUT_P OUT 6 62 101
0402
U6620
NO_TEST=TRUE 10% SSM2375
50V WLCSP
CERM B1 C3
402
101 SSM2375R_P IN+ OUT+
A1 B3
CRITICAL CRITICAL 101 SSM2375R_N IN- OUT- MIN_LINE_WIDTH=0.50 MM
L6621 C6624 A2 A3 MIN_NECK_WIDTH=0.20 MM
FERR-1000-OHM SD* GAIN NC
0.0027UF SPKRCONN_R_OUT_N OUT 6 62 101
1 2 1 2 B2
101 57 IN AUD_LO2_R_N AUD_SPKRAMP_RIN_N EDGE
0402 NO_TEST=TRUE 10%
GND
C1
50V
CERM
402
61 AUD_SPKRAMP_SHUTDOWN_L
R6601 1
100K
B 5%
1/16W
MF-LF
B
402 2
PLACE C6631 CLOSE TO VDD PIN
WOOFER with HPF FC=90Hz
CRITICAL CRITICAL
CRITICAL CRITICAL C6632 1 1
C6631
L6630 100UF 0.1UF
FERR-1000-OHM
C6633 20% 10% MIN_LINE_WIDTH=0.50 MM
16V
CRITICAL
C2
0.022UF 6.3V 2 2 X5R

TANT MIN_NECK_WIDTH=0.20 MM
1 2 1 2 402-1
101 57 IN AUD_LO1_R_P AUD_SPKRAMP_SUBIN_P CASE-AL1 VDD
SPKRCONN_S_OUT_P OUT 6 62 101
0402 NO_TEST=TRUE 10%
U6630
25V SSM2375
X7R WLCSP
0402 B1 C3
101 SSM2375S_P IN+ OUT+
CRITICAL CRITICAL A1 B3
101 SSM2375S_N IN- OUT- MIN_LINE_WIDTH=0.50 MM
L6631 C6634
FERR-1000-OHM A2 A3 MIN_NECK_WIDTH=0.20 MM
0.022UF SD* GAIN NC SPKRCONN_S_OUT_N OUT 6 62 101
101 57 AUD_LO1_R_N 1 2 AUD_SPKRAMP_SUBIN_N 1 2
IN B2
0402
EDGE
NO_TEST=TRUE 10%
25V
GND
C1
X7R
0402
A AUD_SPKRAMP_SHUTDOWN_L
SYNC_MASTER=J31_AUDIO SYNC_DATE=10/26/2011 A
61
PAGE TITLE
AUDIO: SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
3.0.0
66 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO JACK 1 LO/HP JACK, SPDIF TX AUD_SPDIF_OUT
IN 57
L6703
FERR-1000-OHM CRITICAL
AUD_HS_MIC1_UNFILT 1 2
AUD_HS_MIC1_HI
OUT 59
0402
2
XW6700
CRITICAL
Place XW on/near Jack pin L6707

MIC CONNECTOR
SM
FERR-120-OHM-2.0A
AUD_HS_MIC2_RET
1
1 2
OUT 59
0402
CRITICAL
D L6702
FERR-1000-OHM CRITICAL
J6780
78171-0003
M-RT-SM
D
AUD_HS_MIC2_UNFILT AUD_HS_MIC2_HI 4
1 2 59
OUT
0402
2
OUT BI_MIC_N
XW6704
101 63 6
1
CRITICAL
Place XW on/near Jack pin
OUT BI_MIC_SHIELD
2
SM
63 6
L6708
OUT BI_MIC_P
101 63 6
3
FERR-120-OHM-2.0A
1
63 62 57 7 =PP3V3_S0_AUDIO 1 2
AUD_HS_MIC1_RET
OUT 59
5
0402
APN: 514-0671
CRITICAL
J6700 AUD_CONNJ1_TIPDET
SPDIF-TXRX-K24 MIN_LINE_WIDTH=0.40MM
F-RT-TH MIN_LINE_WIDTH=0.30MM
MIC 6 AUD_CONNJ1_USMIC DIGI_MIC
DETECT 5 AUD_CONNJ1_USGND_DET MIN_NECK_WIDTH=0.20MM CRITICAL CRITICAL CRITICAL
SWITCH DIGI_MIC
2 L6704 L6783 J6783
LEFT 1 AUD_CONNJ1_LEFT FERR-120-OHM-2.0A
AUD_HP_PORT_R 600-OHM-300MA 78171-0004
RIGHT 3 M-RT-SM
AUD_CONNJ1_RIGHT 1 2
BI 57 60 57 OUT AUD_DMIC_CLK 1 2 CON_DMIC_CLK
MIN_LINE_WIDTH=0.40MM 5
GND 4 AUD_CONNJ1_USGND MIN_NECK_WIDTH=0.20MM 0402 0402
MIN_LINE_WIDTH=0.30MM CRITICAL
AUDIO MIN_NECK_WIDTH=0.20MM CRITICAL
DIGI_MIC L6784 1
7
L6706 600-OHM-300MA 2
A - VIN FERR-120-OHM-2.0A
AUD_HP_PORT_L AUD_DMIC_SDA1 CON_DMIC_SDA
8 1 2 3
B - VCC 1 2
57 OUT
BI 57 60
9 0402 4
C - GND MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM 0402 CRITICAL
OPERATING VOLTAGE 3.3 R6700 DIGI_MIC
L6785
C POF
10 CRITICAL
1
10K
5%
2 AUD_J1_SLEEVEDET_R OUT 63
63 62 57 7 =PP3V3_S0_AUDIO
600-OHM-300MA
1 2
CON_DMIC_PWR
6
C
SOD882 1/16W
SHELL 11 MF-LF 0402
12
CRITICAL ESDALC5-1BM2
402
2 1
SHIELD 1
C6700 1
C6701 CRITICAL DZ6704 L6705
PINS
13
0.1UF 2.2UF
2
6.8V-100PF DZ6700 FERR-1000-OHM CRITICAL
10% 20% DZ6703 402
2
16V
2
6.3V 6.8V-100PF 1 2 AUD_J1_TIPDET_R OUT 63
X5R CERM
402
402-1 402-LF 0402
1 CRITICAL 2 CRITICAL
CRITICAL
2 2
1
DZ6706 DZ6701 J6781
78171-0002
6.8V-100PF
402
6.8V-100PF
402
1
C6705 SPEAKER CONNECTOR APN: 518S0519 M-RT-SM
100PF 3
5%
50V
1 1 2 CERM
402 SPKRCONN_L_OUT_P 1
101 61 6 IN
MIN_NECK_WIDTH=0.20 MM GND_CHASSIS_AUDIO_JACK 8 62 101 61 6 IN SPKRCONN_L_OUT_N 2
VOLTAGE=0V
XW6701
SM CRITICAL
1 2
J6782
78171-0004
XW6702
GND PATCH SM SPEAKER CONNECTOR APN: 518S0521 M-RT-SM
5
1 2
R6701 101 61 6 IN SPKRCONN_S_OUT_P 1
63 62 57 7 =PP3V3_S0_AUDIO 0 101 61 6 IN SPKRCONN_S_OUT_N 2

62 8 GND_CHASSIS_AUDIO_JACK 1 2
101 61 6 IN SPKRCONN_R_OUT_P 3
5%
1/16W 101 61 6 IN SPKRCONN_R_OUT_N 4
B
MF-LF
B APN: 514-0635 402

6
CRITICAL R6749
AUD_J2_OPT_OUT 4.7
J6750 1 2 AUD_SPDIF_IN OUT 57
AUDIO-RCVR-M97 5%
F-RT-TH5 1/16W
MF-LF
DETECT FOR PLUG TYPE 5 402 CRITICAL
SWITCH 2 AUD_CONNJ2_TIPDET L6754
LEFT 1 MIN_LINE_WIDTH=0.40MM FERR-1000-OHM
RIGHT 3 AUD_CONNJ2_RING 1 2 AUD_LI_R 58
BI
GROUND 4
MIN_NECK_WIDTH=0.20MM 0402
CRITICAL
AUDIO
L6756
6 FERR-1000-OHM
A - VDD
B - GND
7 AUD_CONNJ2_TIP 1 2 AUD_LI_L BI 58
8 MIN_LINE_WIDTH=0.40MM
0402
C - VOUT MIN_NECK_WIDTH=0.20MM
CRITICAL
OPERATING VOLTAGE 3.3 L6758
POF 600-OHM-300MA
9 AUD_CONNJ2_SLEEVE 1 2 AUD_LI_GND 58
SHELL 10
MIN_NECK_WIDTH=0.20MM 0402-1
11 CRITICAL
SHIELD CRITICAL
PINS
12 2 L6752
1
C6750 CRITICAL 2
DZ6754 FERR-1000-OHM
1UF DZ6758 6.8V-100PF
10%
10V
402 1 2 AUD_J2_TIPDET_R OUT 63
2 ESDALC5-1BM2
X5R 0402
402-1
SOD882
2
CRITICAL
1
CRITICAL DZ6756
A 2
DZ6757
ESDALC5-1BM2
1
6.8V-100PF
402
1 C6756
SOD882 PAGE TITLE
100PF
1
1
2
5%
50V AUDIO: JACKS
CERM
402 DRAWING NUMBER SIZE
GND_CHASSIS_AUDIO_JACK 8 62 Apple Inc. 051-9585 D

REVISION
R
3.0.0
AUDIO JACK 2 LINE IN JACK, SPDIF RX THE INFORMATION CONTAINED HEREIN IS THE
67 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS PORT B LEFT(HEADSET MIC) I2C addresses: Mikey uses SMBus 0
HP=80HZ, LP=8.82KHZ MIKEY U6880 READ 0111 0011 0x73
FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT CRITICAL
HP/LINE OUT 0X02 (2) 0X02 (2) 0X09 (9,A) NA 0X09 (Jack Detect A) L6880 MIN_LINE_WIDTH=0.2MM
MIKEY U6880 WRITE 0111 0010 0x72
FERR-1000-OHM MIN_NECK_WIDTH=0.1MM
SATELLITES 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A VOLTAGE=3.3V
SUB 0X03 (3) 0X03 (03) 0X0A (10) GPIO_3 N/A 63 62 57 7 =PP3V3_S0_AUDIO 1 2 PP3V3_S0_HS_RX
0402
CSP MIKEY
SPDIF OUT N/A 0X08 (8) 0X10 (16) N/A 0X0C (Jack detect B)
R6882 1
APN:353S2640
0 R6886
48 IN =I2C_MIKEY_SCL 1 2 10K CRITICAL CRITICAL
CODEC INPUT SIGNAL PATHS 5%
C6880 C6887
A2
1 1
PULLUPS ON MCP PAGE 5% 1/16W CRITICAL
1/16W MF-LF
10UF 0.1UF AVDD
D
FUNCTION CONVERTER PIN COMPLEX VREF DET ASSIGNMENT MF-LF 402
2 20% 10%
D
402
6.3V 25V
LINE IN 0X05 (5) 0X0C (12,C) N/A 0X0C (Jack detect C) OUT 59 X5R 2 2 X5R U6880
603 402 CD3282A1
SPDIF IN 0X07 (7) 0X0F (15) N/A N/A MIN_LINE_WIDTH=0.2MM
WCSP MIN_NECK_WIDTH=0.1MM
BUILT-IN MIC 0X06 (6) 0X0D (13) N/A N/A
R6883 HS_SCL C3 SCL MICBIAS C1 EXT_MIC_BIAS
HEADSET MIC 0X06 (6) 0X0D (13,V22,B,LEFT) MIKEY MIKEY
0
48 BI =I2C_MIKEY_SDA 1 2 HS_SDA B3
SDA DETECT B1 HS_SW_DET CRITICAL
1
SYSTEM INT AND GPIO LINES
5%
1/16W HS_INT_L D3 INT* BYPASS D1 HS_RX_BP C6882
MF-LF 2.2UF
402 BI 59 20%
FUNCTION INT GPIO HS_ENABLE A3 ENABLE 1 2 6.3V
TANT
MIKEY ENABLE SATA4GP/GPIO 16
TIPDET_UNFILT A1
C6881 402
R6884 1
63 HDET 0.01UF
MIKEY INTERRUPT PIRQ H GPIO 5
0 R6887 10% 16V
DGND
AGND
2 CERM 402
PERIPHERAL DETECT PIRQ F GPIO 3 18 OUT AUD_I2C_INT_L 1 2 100K B2 CS GND_AUDIO_CODEC 57 58 63
5%
5%
R6885 1/16W
1/16W
MF-LF
C2
D2
0 MF-LF 402
24 IN AUD_IPHS_SWITCH_EN 1 2 402 2
PORT A DETECT (HEADPHONES) PORT B DETECT(SPDIF DELEGATE) 5%

63 57 OUT AUD_SENSE_A 1/16W
MF-LF
402 R6880 1
1K
PP4V5_AUDIO_ANALOG_FLT
1 1 63 58 57 GND_AUDIO_CODEC 1%
63 R6806 R6805 1/16W
MF-LF
1
39.2K 20.0K 402
2
R6804 1% 1%
Q6803 1/16W 1/16W OUT 59
150K DMC2400UV MF-LF MF-LF
5% SOT563 D 3 2 402 2 402 CRITICAL
1/16W
P-CH AUD_J1_SLEEVEDET_R_INV
C6883
AUD_J1_SLEEVEDET_R
MF-LF
402 AUD_PORTA_DET_L AUD_PORTB_DET_L 0.1UF R6890 MIN_LINE_WIDTH=0.1MM
2 2.2K MIN_NECK_WIDTH=0.05MM
OUT AUD_MIC_INP_L HS_MIC_HI_RC EXT_MIC_P
62 57
1 2 1 2 59
IN IN
1 5%
1
C6802 R6814 10% 1/16W
5 G 220K 25V MF-LF Place this next to Charleston
0.01UF 5%
X5R 402
10% 402 1 1
2
16V 1/16W R6888 1 C6885
C
MF-LF
S
C C6884
GND_AUDIO_CODEC
CERM 4 100K
402
402 2
5%
27PF
63 58 57
D 6
1/16W
0.0082UF 2
5% 50V
10% 25V CERM 402
63 AUD_J1_SLEEVEDET_R_BUF CRITICAL MF-LF 2 X7R 402
C6886 2
402 CRITICAL
CRITICAL
0.1UF
OUT AUD_MIC_INN_L EXT_MIC_REF
1 2
57 IN 59 MIN_NECK_WIDTH=0.05MM
2
AUD_J1_SLEEVEDET_R_INV 2 G
R6803
10%
220K
APN:376S0975 CRITICAL
1/16W
MF-LF
25V
402
5%
CRITICAL
SSM6N37FEAPE X5R
1 S D 3 SSM6N37FEAPE 402
Q6801 D 6
N-CH
1
GND_AUDIO_CODEC Q6801
SOT563
SOT563
PORT B RIGHT(BUILT-IN MIC)
63 58 57
R6850 R6851
5 G S 100 2.4K
4
2 G S 57 IN AUD_CODEC_MICBIAS 1 2 MIC_BIAS_FILT 1 2
1
1% CRITICAL 1%
1/16W 1/16W
1
MF-LF
402
C6852 MF
402-1
2.2UF
20%
63 2 6.3V
TANT
AUD_J1_SLEEVEDET_R_BUF 402
63 58 57 GND_AUDIO_CODEC
CRITICAL
CRITICAL C6850 L6850
L6801 0.1UF FERR-1000-OHM
FERR-1000-OHM
OUT AUD_MIC_INP_R BI_MIC_HI_F BI_MIC_P
1 2 1 2
57 IN 6 62 101
57 IN PP4V5_AUDIO_ANALOG 1 2 0402
10%
0402 25V 1
CRITICAL
X5R R6852 1
402 100K C6853
5%
1/16W 0.001UF
PP4V5_AUDIO_ANALOG_FLT 50V 10%
63 CRITICAL MF-LF 2
C6851 2
402
402 CERM
L6851
B C6804
1
AUD_J1_DET_NMOS_DRN 57 OUT AUD_MIC_INN_R
0.1UF
1 2 BI_MIC_LO_F
FERR-1000-OHM
1 2 BI_MIC_N IN 6 62 101
B
0.1UF VOLTAGE=5V 0402
10V 20% 10%
402 CERM 2
25V R6853
63 58 57 GND_AUDIO_CODEC X5R
402
2.4K XW6851
63 58 57 GND_AUDIO_CODEC 1 2 SM
BI_MIC_SHIELD
1% 1 2 6 62
1/16W
IN
MF HP=80HZ
1 402-1
4 Place this next to the connector
S
S APN:376S1017
SOT-563-HF
SOT-563-HF NTZD3152P
1 2
PORT C DETECT (LINE-IN)
R6801 5 NTZD3152P G Q6804 Q6800 D 3
220K AUD_J1_DET_RC2 G Q6804 SSM3K15AMFVAPE
5%
1/16W R6813
MF-LF D VESM 10K
402
D 6 63 57 AUD_SENSE_A 2 1 AUD_INJACK_INSERT_L
2 OUT
R6802 R6807 3
1% NC
100K AUD_J1_DET_RC 100K 1 G S 1/16W
62 IN AUD_J1_TIPDET_R 1 2 1 2 AUD_J1_DET_R_GATE 2 MF-LF
402
5%
1
5%
1
63 62 57 7 =PP3V3_S0_AUDIO
1/20W
C6801
1/20W
1 1 R6809 AUD_J1_DET_NMOS_GATE
MF
201
MF
201 C6803 R6808 220K
NOSTUFF
0.1UF 220K 5%
Q6802
20% 10V 0.1UF 1
2 CERM 402 20% 10V 5% 1/16W R6811 SSM3K15FV D 3
R6830 2 CERM 402 1/16W
MF-LF
MF-LF
402 270K SOD-VESM-HF
0 TIPDET_UNFILT 402
2
5%
1 2 2
63 1/16W
63 58 57 GND_AUDIO_CODEC MF-LF
5% 402
1/16W 2
MF-LF
402
R6840 1 G S 2
R6812 APN:376S0612
100K 47K
A 1
5%
1/16W
2 AUD_IP_PERIPHERAL_DET OUT 18 62 IN AUD_J2_TIPDET_R 1
5%
1/16W
2 AUD_J2_DET_RC
1
MF-LF EXTRACTION NOTIFICATION MF-LF C6811 PAGE TITLE
402 402
Voltage level shifting from 5V to 3.3V
2
0.1UF
20% 10V AUDIO: JACK TRANSLATORS
CERM 402
DRAWING NUMBER SIZE
63 58 57 GND_AUDIO_CODEC
REVISION
R6841
R
2
3.0.0
200K
1/16W
MF-LF
NOTICE OF PROPRIETARY PROPERTY:

402
5%
BRANCH
1
GND_AUDIO_CODEC THE POSESSOR AGREES TO THE FOLLOWING: PAGE

63 58 57
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 68 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MagSafe DC Power Jack

PP18V5_DCIN_FUSE 6
CRITICAL
CRITICAL
F6905
D
J6900
78048-0573
M-RT-SM
PP18V5_DCIN_FUSE 1
6AMP-24V
2
=PP18V5_DCIN_CONN 7 64
D
MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
PWR
1 VOLTAGE=18.5V 1206-2
2
1
C6905 =PP3V42_G3H_ONEWIREPROT 7
PWR
0.01UF
GND
3 20%
50V
SMC_BC_ACOK_VCC 1 C6908
2 CERM 0.1UF
GND
4
603 20%
5 1 CRITICAL 10V PLACEMENT_NOTE=PLACE NEAR U6900 and U6901
SIG
R6929 2 CERM
1
2.0K VCC U6901 402
5% TC7SZ08FEAPE
1/16W 5
MF-LF U6900 SOT665
A
2 SMC_BC_ACOK IN 45 46
402 MAX9940
2 4
SC70-5 Y
45 BI SYS_ONEWIRE 4 INT EXT 5 B
1
CRITICAL 3
GND NC
3
NC
BIL CONNECTOR
7 =PP3V42_G3H_BIL
516S0523
C6951 1
CRITICAL
1-Wire OverVoltage Protection 0.1UF
10%
J6955
25V
X5R 2 CPB6312-0101F
ADAPTOR_SENSE 402
ADAPTER_SENSE OUT 6 F-ST-SM
14 13
The chassis ground will otherwise float and can

2 1
send transients onto ADAPTER_SENSE when AC is
C connected.
R6961
100 NC
4
6
3
5
NC C
53 46 45 SMC_LID 2 1 SMC_LID_R
6 8 7
OUT 402 1/16W
5% 64 48 BI =SMBUS_BATT_SDA 10 9
TO SMC
MF-LF
64 48 BI =SMBUS_BATT_SCL 12 11 SMC_BIL_BUTTON_L OUT 6 45 46
C6955 1
C6953 1
C6952 1
16 15
C6954 1
0.001UF 47PF 47PF 0.001UF

10% 5% 5% 10%
50V 50V 50V 50V
CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402
CRITICAL
R6905 CRITICAL
3.425V "G3Hot" Supply
=PPBUS_G3H 1
5.1 2
PBUS_G3H_R D6990
65 7
MIN_LINE_WIDTH=0.6 mm BAT30CWFILM Supply needs to guarantee 3.31V delivered to SMC VRef generator
5% MIN_NECK_WIDTH=0.25 mm SOT-323
1/3W
MF VOLTAGE=18.5V 1
0805-1
3 PPVIN_G3H_P3V42G3H
R6990 MIN_LINE_WIDTH=0.6 mm
=PP18V5_DCIN_CONN 47 P18V5_DCIN_CONN_R MIN_NECK_WIDTH=0.3 mm
64 7 1 2 2 VOLTAGE=18.5V P3V42G3H_BOOST
MIN_LINE_WIDTH=0.6 mm DIDT=TRUE
7
1/3W VOLTAGE=18.5V
MF C6990 1
C6994 1
VIN BOOST
B B
0805
4.7UF 0.1UF CRITICAL
10% 10%
35V
X5R-CERM 2
U6990 16V
X5R 2 L6995
0805 LT3970 402 33UH-20%-0.44A-0.455OHM
DFN
=PP3V42_G3H_REG 7
2
EN/UVL0 SW 6 6 P3V42G3H_SW 1 2
MIN_LINE_WIDTH=0.5 mm Vout = 3.414
CRITICAL MIN_NECK_WIDTH=0.25 mm D52LC-SM
9 PG BD 8 0
NC 353S2730
SWITCH_NODE=TRUE DIDT=TRUE
1 2 350mA max output
10 RT FB 1 P3V42_BD_R
R6992 <Ra>
(Switcher limit)
1
GND THRM
1/16W
MF-LF C6995 1 R6995
518-0375 P3V42_RT PAD 402 1M
5% 47PF 1%
11
5% 1/16W
5
50V
CRITICAL 2 MF-LF
J6950
BATTERY CONNECTOR 1
R6991
CERM
402
402 2 1 C6999
BAT-K90-K91-K92 150K 22UF
1% P3V42G3H_FB 20%
M-RT-TH 1/16W 6.3V
MF-LF <Rb> 2 X5R-CERM-1
1 402
P1 2 1 603
P2 2 R6996
549K
3
P3 1%
1/16W
P4 4 =SMBUS_BATT_SCL 48 64 MF-LF
5 6 SYS_DETECT_L 2 402
P5
P6 6 =SMBUS_BATT_SDA 48 64
CRITICAL
7 65 6 PPVBAT_G3H_CONN
P7 D6950
P8 8
R6950 1 Vout = 1.21V * (1 + Ra / Rb)
1
RCLAMP2402B
P9 9 C6950 1 C6960 1 SC-75 10K
0.1UF 1UF 5%
1/16W
10 10% 10%
SHLD_PIN 25V 25V MF-LF
X5R 2 X5R 2 402
11 2
SHLD_PIN 402 603-1
3
12
SHLD_PIN
A SHLD_PIN 13
SYNC_MASTER=J31_JACK SYNC_DATE=09/02/2011 A
PAGE TITLE
DC-In & Battery Connectors

DRAWING NUMBER SIZE

REVISION
R
3.0.0
69 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R7091
CRITICAL 0
Q7080 1 2 PP5V1_CHGR_VDDP 65
IRF9395TRPBF
R7093 5.5V "G3Hot" Supply 5%
0 1/16W
DIRECTFET-MC
65 PPCHGR_DCIN_D 1 2 MF-LF
402
5%
NC NC NC NC 1/16W
MF-LF PPCHGR_DCIN_D_R P5V5G3H_BOOST
402 MIN_LINE_WIDTH=0.2 mm
6
DIDT=TRUE
R7092
10
MIN_NECK_WIDTH=0.2 mm 0
2
1
7
Reverse-Current Protection VOLTAGE=18.5V 1 2 PPCHGR_DCIN 65
Inrush Limiter MIN_LINE_WIDTH=0.2 mm
3
FROM ADAPTER C7094 1 5% MIN_NECK_WIDTH=0.2 mm
VIN BOOST 0.22UF 1/16W VOLTAGE=5.5V
CRITICAL MF-LF
D
7 =PPDCIN_S5_CHGR PPDCIN_G3H_INRUSH 10% 402
MIN_LINE_WIDTH=0.6 mm U7090 10V
CERM 2 L7095 NO STUFF
MIN_NECK_WIDTH=0.4 mm LT3470A 402 33UH-20%-0.39A-0.435OHM PP5V5_CHGR_VDDP
NO STUFF
D 1
C7086 1
C7085
1
R7085
1
R7080
VOLTAGE=18.5V
8 SHDN*
DFN
SW 4 6 P5V5G3H_SW 1 2
MIN_NECK_WIDTH=0.2 mm D
G
1UF 0.1UF 470K 100K MIN_LINE_WIDTH=0.5 mm VOLTAGE=5.5V
1% 5% BIAS 2 MIN_NECK_WIDTH=0.25 mm DP418C-SM
10% 10%
25V 25V 1/16W 1/16W
7
CRITICAL SWITCH_NODE=TRUE Vout = 5.506V
2 2 MF-LF MF-LF NC NC
3
DIDT=TRUE
X5R X5R
603-1 402 2 402 2 402
FB 1 200MA MAX OUTPUT
THRM <Ra>
CHGR_AGATE_DIV CHGR_SGATE_DIV
C7090 1 GND PAD
1
C7095 R7095 1 (Switcher limit)
4.7UF
9
1 10% 22PF 681K
1 R7081 35V 5%
1%
R7086 62K X5R-CERM 2
2
50V 1/20W
MF CRITICAL CRITICAL
332K 0805 CERM
5% 201
1% 1/16W
201 2 1
C7098 1
C7099
1/16W MF-LF
CRITICAL MF-LF 402 P5V5G3H_FB 10UF 10UF
2 20% 20%
402 2 10V 10V
D7005 <Rb> 2 X5R 2 X5R
(CHGR_AGATE) (CHGR_SGATE) 0603 0603
BAT30CWFILM
SOT-323
R7096 1
200K
1
R7005 1%
1/20W
20 R7021 MF
3 65 PPCHGR_DCIN_D 1 2 (CHGR_DCIN) 201
2
MIN_LINE_WIDTH=0.2 mm 10 SIGNAL_MODEL=EMPTY
MIN_NECK_WIDTH=0.2 mm 5% 1 2
2 VOLTAGE=18.5V 1/16W CRITICAL
ACIN pin threshold is 3.2V, +/- 50mV MF-LF 5% 4 2
R7020
402 1/16W 101 CHGR_CSI_R_P
1 C7020 MF-LF
0.020 Vout = 1.25V * (1 + Ra / Rb)
Divider sets ACIN threshold at 13.55V 0.047UF 402 0.5%
10% 1W
10V MF-LF
Input impedance of ~40K meets 2 CERM R7022 101 CHGR_CSI_R_N 0612
30mA max load 402
sparkitecture requirements 10 3 1
1 2
PP5V1_CHGR_VDD R7001 PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.2 mm 4.7 5% MIN_LINE_WIDTH=0.6 mm
74 7 =PP3V42_G3H_CHGR MIN_NECK_WIDTH=0.1 mm 1 2 65 PP5V1_CHGR_VDDP 1/16W MIN_NECK_WIDTH=0.4 mm CRITICAL CRITICAL
VOLTAGE=5.1V MIN_LINE_WIDTH=0.2 mm MF-LF VOLTAGE=18.5V
5%
1/16W
MIN_NECK_WIDTH=0.2 mm 402 1
C7030 1
C7031 1
C7035 1
C7036 1
C7037
VOLTAGE=5.1V 1UF 1UF 0.001UF
MF-LF 22UF 22UF
402 C7001 1 C7022 1 1 C7021 20% 20% 10%
25V
10%
25V
10%
50V
2 25V 2 25V 2 2 2
NO STUFF 1UF 0.1UF 0.1UF POLY-TANT POLY-TANT X5R X5R X7R
C R7012 1
C7002
1UF
10%
1
1
R7002
100K
10%
10V
X5R
402
2
10%
25V
X5R
402
2 2
10%
25V
X5R
402
CASE-D2-SM CASE-D2-SM 603-1
603-1 402
PLACE_NEAR=C7036.1:3mm C
1K 10V
X5R 2 5%
19
20
1% 402 1/16W
1/16W 65 MF-LF
MF-LF 402 5
402 2 GND_CHGR_AGND 2 VDD VDDP OMIT_TABLE
R7000 12 VHST CRITICAL DCIN 2 65 PPCHGR_DCIN CRITICAL
1 SMC_RESET_L
0
CHGR_RST_L
D Max Current = 8A
R7010 IN 1 2 13 SMB_RST_N Q7030
SGATE 26 CHGR_SGATE
30.1K 5% 48 IN =SMBUS_CHGR_SCL 11 SCL U7000 4 G RJK0332DPB-01 (L7030 limit)
1% 1/16W
=SMBUS_CHGR_SDA
AGATE 1 CHGR_AGATE 1
C7025 LFPAK-SM
1/16W MF-LF 48 BI
10 SDA TQFN
0.22UF
402 CSIP 28 99 CHGR_CSI_P f = 400 kHz
ISL6259
MF-LF
2 402
74 IN CHGR_VFRQ 4 VFRQ 10%
10V
CSIN 27 99 CHGR_CSI_N 2 CERM S CRITICAL
CHGR_CELL 6 CELL CRITICAL
BOOT 25 CHGR_BOOT
402
PLACE_NEAR=U7000.25:2mm NC L7030 TO SYSTEM
CHGR_ACIN 3 ACIN
6 DIDT=TRUE 3 F7040
CHGR_UGATE
1 2 3 4.7UH-10.2A
UGATE 24 6 GATE_NODE=TRUE DIDT=TRUE 8AMP-24V
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
CHGR_ICOMP 5 CHGR_PHASE 2 1 2 =PPBUS_G3H
1
ICOMP PHASE 23 6 7 64
R7011 6 CHGR_VCOMP 7 VCOMP
MIN_NECK_WIDTH=0.2 mm FDA1254F-SM
9.31K LGATE 21 6 CHGR_LGATE GATE_NODE=TRUE DIDT=TRUE SWITCH_NODE=TRUE 1206
1% CHGR_VNEG 8 VNEG MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
1/16W NO STUFF 1 CRITICAL
1 CHGR_CSO_P 18 CHGR_BGATE
MF-LF R7015 99 CSOP BGATE 16
2 402 330K 99 CHGR_CSO_N 17 CSON 20V/V AMON 9 CHGR_AMON 50
R7039 1 F7041
OUT
5% 180 8AMP-24V
THRM_PAD
1/16W 36V/V BMON 15 CHGR_BMON OUT 50 5%

MF-LF 1/10W PPVBAT_G3H_CHGR_REG 1 2
1
C7050 =CHGR_ACOK
(AGND)
2 402 (OD) ACOK 14

OUT 46 49 MF-LF MIN_LINE_WIDTH=0.6 mm
CRITICAL
PGND
603 2 MIN_NECK_WIDTH=0.4 mm
1UF VOLTAGE=12.6V 1206
CHGR_VCOMP_R 10%
16V 5
1
C7040 1
C7045
2 OMIT_TABLE
X5R 22UF 0.001UF
402 CHGR_PHASE_RC
29
22
10%
353S2392 CRITICAL 20%
C7015 1
MIN_LINE_WIDTH=0.6 mm 2 25V
POLY-TANT
2
50V
X7R
220PF Q7035 MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE CASE-D2-SM 402
10%
50V
4
RJK0305DPB CRITICAL CRITICAL
2 NO STUFF
X7R-CERM LFPAK-HF
R7050 Q7055
402 1
C7039 0.005 SI7137DP
B 1
R7042
0 2
470PF
10%
50V
CERM
1%
1W
MF
SO-8
SYM-VER-2
TO/FROM BATTERY B
5%
1/16W
R7016 1 XW7000 1 2 3
402 2
0612
1 PPVBAT_G3H_CHGR_R 3 S
MF-LF 3.01K SM MIN_LINE_WIDTH=0.6 mm
4 3 2 D 5 PPVBAT_G3H_CONN
2 402
1% MIN_NECK_WIDTH=0.4 mm 6 64
1/16W 1 2 (GND) VOLTAGE=12.6V MIN_LINE_WIDTH=0.6 mm
MF-LF C7055 1
C7056 1
C7057 1 1 MIN_NECK_WIDTH=0.4 mm
402
2
PLACE_NEAR=U7000.29:1mm 1UF 0.1UF 0.01uF VOLTAGE=12.6V
PLACE_NEAR=U7000.22:1mm 10% 10% 10% G
CHGR_VNEG_R 25V 16V 16V
X5R 2 X5R 2 CERM 2
4
603-1 402-1 402
1
C7016 (CHGR_CSO_P) R7051 2.2 1 2 101 CHGR_CSO_R_P
5% 1/16W MF-LF 402
470PF
10% (CHGR_CSO_N) R7052 0 1 2 101 CHGR_CSO_R_N
50V 5% 1/16W MF-LF 402
2 CERM
402
(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R)
6 CHGR_ICOMP_RC (CHGR_BGATE)
1
C7042 C7011 1 1
C7000 C7005 1
C7026 1
0.068UF 0.01UF 1UF 0.22UF 0.001UF

10% 10% 10% 20% 10%
10V 16V 10V 25V 50V
2 CERM CERM 2 2 X5R X5R 2 CERM 2
402 402 402-1 603 402
65 GND_CHGR_AGND
VOLTAGE=0V
A SYNC_MASTER=J31_JACK SYNC_DATE=11/14/2011 A
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER SIZE

REVISION
R
3.0.0
70 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
7 =PPVIN_S0_VCCSAS0
7 =PP5V_S0_VCCSAS0
VCCSAS0_BOOT_RC
CRITICAL MIN_LINE_WIDTH=0.3 mm CRITICAL CRITICAL
R7101 1 1 C7101 DIDT=TRUE C7119 1 C7120 1 C7121 1 1 C7122
2.2 10UF 10UF 10UF 1UF 1000PF
20% 10% 10% 10% 5%
5%
1/16W 2
10V
X5R 1
1
C7130 16V
X5R-CERM 2
16V
X5R-CERM 2
25V
X5R 2 2
25V
NP0-C0G
MF-LF
402
603 R7130 0.22UF 0805 0805 603-1 402
PLACE_NEAR=C7121.1:3mm
2 0 10%
10V
5% 2 CERM PLACE_NEAR=Q7100.2:1mm
PP5V_S0_VCCSAS0_VCC 1/10W 402
MIN_LINE_WIDTH=0.6 mm MF-LF
MIN_NECK_WIDTH=0.2 mm 603 2
VOLTAGE=5V 376S0944
19
20
CRITICAL
VCC PVCC 6 VCCSAS0_VBST Q7100
U7100 MIN_NECK_WIDTH=0.2 mm 2 RJK0222DNS
DIDT=TRUE
ISL95870AH HWSON CRITICAL
=PVCCSA_EN 15 UTQFN 18
VCCSAS0_DRVH R7140
R7151 74 IN EN BOOT MIN_LINE_WIDTH=0.6 mm CRITICAL 0.001
CRITICAL MIN_NECK_WIDTH=0.2 mm
1.62K 10 17 GATE_NODE=TRUE L7100 1%
93 12 IN CPU_VCCSASENSE 1 2 6 CPU_VCCSASENSE_DIV FB UGATE DIDT=TRUE
1
1.0UH-7.7A 1W =PPVCCSA_S0_REG 7 49
MF-1
1% 0612
VCCSAS0_SREF 7 16 VCCSAS0_LL 7 1 2 PPVCCSA_S0_REG_R
1/16W SREF PHASE 6 1 2
C MF-LF
402
1
VCCSAS0_VO 12
VO LGATE 1
SWITCH_NODE=TRUE
152S0913
FDV0630H-SM
VOLTAGE=1.05V
3 4 6A Max Output C
R7147 DIDT=TRUE
f = 300 kHz
VCCSAS0_OCSET 11 6
41.2K OCSET
1%
1/16W 14
R7153 MF-LF 74 OUT PVCCSA_PGOOD PGOOD
1.62K 2 402
VCCSAS0_RTN 1 2 VCCSAS0_RTN_DIV 4 VCCSAS0_DRVL
RTN 6 3 4 5
VCCSAS0_FSEL 13
1/16W FSEL GATE_NODE=TRUE
MF-LF DIDT=TRUE
402
VCCSAS0_SET0 8
SET0
2 C7103 1
0.022UF VCCSAS0_SET1 9
XW7101 10%
SET1
SM 16V
CERM-X5R 2 6
1
1
402 R7148 VID0
52.3K 5 (ENDIAN SWAP)
1%
1/16W
R7103 1 VID1
101 49 VCCSAS0_CS_P
MF-LF 0
2
402
1
C7102 5% SIGNAL_MODEL=EMPTY
101 49 VCCSAS0_CS_N
1/16W
2.2UF GND PGND 1
10% MF-LF
402
R7141
16V 2 1K
2
2 X5R
R7150 603 1%
1/16W
82.5K MF-LF
C7140
1 2 402 2
1000PF
1%
1/16W 93 12 IN CPU_VCCSA_VID<1> 2 1
MF-LF
1 1
402 93 12 IN CPU_VCCSA_VID<0> SIGNAL_MODEL=EMPTY 5%
SIGNAL_MODEL=EMPTY
1
C7106 R7154 R7152 1
C7105 25V 1
4.64K 4.64K VCCSAS0_SET_R NP0-C0G R7142
10PF 1% 1%
10PF 402 1K
5% 5%
50V 1/16W 1/16W 50V 1
1% OCP = R7141 x 8.5uA / R7140
2 CERM MF-LF MF-LF 2 CERM R7149 1/16W
2 402 2 402
402 402 MF-LF
499K (VCCSAS0_OCSET)
2 402
OCP = 8.5A
1%
B 2
1/16W
MF-LF
402
(VCCSAS0_VO)
B
XW7100
SM
VCCSAS0_AGND 1 2
MIN_NECK_WIDTH=0.2 mm PLACE_NEAR=U7100.3:1mm
VOLTAGE=0V
INTEL TABLE:
VID1 VID0 Voltage
0 0 0.9V
1 0 0.8V
0 1 0.725V
1 1 0.675V
PAGE TITLE
System Agent Supply

DRAWING NUMBER SIZE

REVISION
R
3.0.0
71 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
67 7 =PP5V_S3_REG
7 =PPVIN_S5_P5VP3V3

=PP5V_S5_LDO 7
C7240 1
C7242 1 1
C7241 1
C7270 C7280 1
C7282 1 1
C7281 1
C7283
68UF 68UF 1UF 0.001UF C7200 1
Vout = 5V 68UF 68UF 1UF 0.001UF
20% 20% 10% 10% 20% 20% 10% 10%
16V 2 16V 2 2
25V
2
50V 1UF 100mA MAX OUTPUT 16V 2 16V 2 2
25V
2
50V
POLY-TANT POLY-TANT X5R X7R 10% POLY-TANT POLY-TANT X5R X7R
603-1 402 25V 603-1 402
CASE-D2E-SM CASE-D2E-SM PLACE_NEAR=C7241.1:3MM
X5R 2 CRITICAL CASE-D2E-SM CASE-D2E-SM
PLACE_NEAR=C7281.1:3MM
603-1 1
C7205
PLACE_NEAR=Q7220.1:1MM PLACE_NEAR=Q7260.2:1MM
P5VP3V3_VREG3 10UF
20%
6.3V
SKIP_5V3V3:AUDIBLE 2
SKIP_5V3V3:INAUDIBLE P5VP3V3_VREF2 X5R
603
67 7 =PP5V_S3_REG =PP3V3_S5_REG 7
1 1
R7200 R7201
23
29
22
13
Vout = 5.0V C7201 1 1
C7203 Vout = 3.3V
2
0 0 0.22UF 2.2UF
V5SW
VIN
VREG5
VREG3
VREF2
5% 5%
11.834A MAX OUTPUT 1
MIN_LINE_WIDTH=0.6 mm 1/16W 1/16W
10%
10V
20%
10V MIN_LINE_WIDTH=0.6 mm CRITICAL 2
8.07A MAX OUTPUT
MIN_NECK_WIDTH=0.2 mm MF-LF MF-LF 2 2 MIN_NECK_WIDTH=0.2 mm
CRITICAL 402 402
CERM X5R-CERM
C7264 1
Q7260 CRITICAL
f = 400 Khz CRITICAL
1
C7224 2 2 402 402
0.1UF f = 400 Khz
L7220 0.1UF 10%
RJK0214DPA L7260
2.2UH-14A-7.0M-OHM 10%
6 SKIPSEL1 50V 2 WPAK2
2.2UH-14A
CRITICAL 2
PIMB104E2R2MS-SM Q7220 2
50V
R7244 1 P5VP3V3_SKIPSEL 19 SKIPSEL2 X7R IHLP2525CZ-SM1
1
C7271 CSD58872Q5D
X7R
U7201 R7263
603-1
C7272 1
C 0.001UF
10%
2
1 VIN SON5X6
TG 3 6
603-1
P5VS3_TG
1
5%
1/16W
14 OCSEL
QFN
EN 12 =P5VS5_EN IN 74
1
0
2 6 P3V3S5_TG 1
0.001UF
10% C
TPS51980
50V 50V
2 X7R MIN_LINE_WIDTH=0.6 mm MF-LF MIN_LINE_WIDTH=0.6 mm X7R 2
MIN_NECK_WIDTH=0.2 mm 402 6 P5VS3_VBST 31 VBST1 VBST2 26 6 P3V3S5_VBST 5% MIN_NECK_WIDTH=0.2 mm 1
402 P5VS3_VSW 6 VSW GATE_NODE=TRUE
2
DIDT=TRUE DIDT=TRUE 1/16W DIDT=TRUE
402
CRITICAL CRITICAL MIN_LINE_WIDTH=0.6 mm
7 TGR 4
DIDT=TRUE MF-LF GATE_NODE=TRUE
7
CRITICAL CRITICAL
MIN_NECK_WIDTH=0.2 mm 6 P5VS3_DRVH 1 DRVH1 DRVH2 24 6 P3V3S5_DRVH 402
C7252 1
C7250 1
DIDT=TRUE
8
MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm
1
C7290 1
C7292
10UF MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 10UF
330UF 6 P5VS3_LL 32 SW1 SW2 25 6 P3V3S5_LL 330UF
PLACE_NEAR=L7260.2:3mm
20% 20%
20%
10V NO STUFF MIN_LINE_WIDTH=0.6 mm SWITCH_NODE=TRUE DIDT=TRUE DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm NO STUFF 6.3V
20%
6.3V 2 2 MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 2 2 6.3V

X5R 1 BG 5 P5VS3_DRVL P3V3S5_DRVL 6 X5R
POLY-TANT
CASE-D3L-SM1 805 R7299 MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE
6
DIDT=TRUE
30 DRVL1 DRVL2 27 6
DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm
R7298 1 603
POLY-TANT
CASE-D3L-SM1
1 MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm 10
5% PGND P5VS3_CSP1 7 CSP1 CSP2 18 P3V3S5_CSP2 5%
1/10W 1/10W
P5VS3_CSN1 8 CSN1 CSN2 P3V3S5_CSN2
9
17
MF-LF
603
C7218 C7288 3 4 5
MF-LF
603
2 2
0.1UF 0.1UF
P3V3S5_RF
11 MODE RF 3
P5VS3_SNUBR P3V3S5_SNUBR
PLACE_NEAR=L7220.2:3MM
6 1 2 1 2 6
MIN_LINE_WIDTH=0.6 mm 6 P5VS3_VFB1 9 VFB1 VFB2 16 6 P3V3S5_VFB2 MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
10%
16V
P5VS3_COMP1 10 COMP1 COMP2 15 P3V3S5_COMP2 10%
16V
DIDT=TRUE
SIGNAL_MODEL=EMPTY X5R
R7206 1
X5R
2 NO STUFF NO STUFF 2
402-1
74 IN =P5VS3_EN 4 EN1 EN2 21 =P3V3S5_EN IN 74
402-1
XW7222 C7299 1
P5VS3_PGOOD 5 P3V3S5_PGOOD
249K 1
C7298 XW7262
SM 0.0033UF R7247 74 OUT PGOOD1 PGOOD2 20
OUT 74 1%
R7246 0.001UF SM
1/16W
10% 6.04K 1.21K 10%
50V 1 2 GND THRM_PAD MF-LF
1 2 50V
1 CERM 2 402 2 X7R 1
2
402 402
28
33
1% 1%
P5VS3_VFB1_R 1/16W 1/16W P3V3S5_VFB2_R
2 2 R7256 1 MF-LF
1 R7236 1 1
R7238 R7239 1 MF-LF 1
R7216 2 2
8.25K
402
R7237 12.1K 12.1K 10.5K
402
5.62K
XW7220 XW7221 1% 10.5K 1% 1% 1% 1%
XW7260 XW7261
SM SM SM SM
1/16W 1% 1/16W 1/16W 1/16W 1/16W
R7220 1 1 1
SIGNAL_MODEL=EMPTY MF-LF
402
1/16W
MF-LF
MF-LF
402 2
MF-LF
402
MF-LF
402
MF-LF
402 1 1
R7260 1
41.2K 2 2 2 2 2 23.2K
402
2
1% SIGNAL_MODEL=EMPTY XW7200 1%
1/16W 6 P5VS3_CSP1_R P5VS3_COMP1_R P3V3S5_COMP2_R 6 P3V3S5_CSP2_R 1/16W
SM
MF-LF MF-LF
402 PLACE_NEAR=U7200.28:1MM 402
2 2
1
C7237 1 1
C7236 C7238 1 1
C7239
150PF 4700PF 2200PF 47PF
B 1
R7221
5%
50V
CERM
402
2 2
10%
100V
CERM
402
5%
10V
CERM
0402
2 2
5%
50V
CERM
402 R7261 1
B
10.2K (P5VP3V3_VREF2) (P5VP3V3_VREF2) 10K
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 402
2 2
GND_5V3V3_AGND
VOLTAGE=0V
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER SIZE

REVISION
R
3.0.0
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 72 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
7 =PPVIN_S3_DDRREG
CRITICAL CRITICAL
C7330 1
C7331 1 1 C7332 1 C7333 1
C7334
68UF 68UF 1UF 0.001UF 1UF
20% 20% 10% 10% 10%
16V 2 16V 2 25V 50V 25V
2 X5R 2 X7R 2 X5R
POLY-TANT POLY-TANT
=PPVIN_S0_DDRREG_LDO CASE-D2E-SM CASE-D2E-SM 603-1 402 603-1
7
CRITICAL PLACE_NEAR=Q7330.1:1MM
7 =PP5V_S3_DDRREG
C7301 1
10UF
20%
CRITICAL 10V 5
2
C7300 1 X5R
603
10UF CRITICAL
D
20%
10V
X5R 2 (DDRREG_DRVH) Q7330
603
4 G RJK0225DNS
HVSON-3333
2
C VLDOIN
C7325
0.1UF
S
OMIT_TABLE
C
12 V5IN VBST 15 DDRREG_VBST MIN_LINE_WIDTH=0.6 mm
1 2
DIDT=TRUE 1 2 3
31 6 IN DDRREG_FB DRVH 14 6 DDRREG_DRVH CRITICAL
=DDRVTT_EN
U7300 GATE_NODE=TRUE DIDT=TRUE
10%
50V L7330
26 8 IN (VTT Enable) 17 S3 SW 13 6 DDRREG_LL
X7R
TPS51916 SWITCH_NODE=TRUE DIDT=TRUE
603-1 1.0UH-21A
74 IN =DDRREG_EN (VDDQ/VTTREF Enable) 16 S5 QFN (DDRREG_LL)
1 2
DRVL 11 6 DDRREG_DRVL =PPDDR_S3_REG 7
DDRREG_1V8_VREF 6 VREF GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
FDU1040D-SM
CRITICAL PGOOD 20 DDRREG_PGOOD
OUT 92 MIN_NECK_WIDTH=0.17 mm CRITICAL Vout = 1.5V
5
1
R7315 8 REFIN
VDDQSNS 9 DDRREG_VDDQSNS 1
C7340 15A max output
C7315 1
VTT 3 7 =PPVTT_S0_DDR_LDO XW7360 CRITICAL 330UF (Q7335 limit)
20.0K SM D 20%
0.1UF DDRREG_MODE 19 MODE VTTSNS 1 2 2.0V 1
C7346 f = 400 kHz
10%
16V
1%
1/16W DDRREG_VTTSNS 1 2 Q7335 POLY-TANT
0.001UF
2 MF-LF 6 DDRREG_TRIP 18 TRIP G CASE-B2-SM1
X5R PLACE_NEAR=C7361.1:3mm (DDRREG_DRVL)
4 RJK0226DNS 10%
402 402 50V
2 HVSON-333
VTTREF 5 =PPVTT_S3_DDR_BUF MIN_LINE_WIDTH=0.6 mm CRITICAL CRITICAL 2 X7R
10mA max load
C7341 1
CRITICAL CRITICAL 1
C7345 402
2
NOSTUFF VTT THRM S OMIT_TABLE
330UF 10UF
1 PGND GND GND PAD C7360 1 1
C7361 20% 20% XW7301
R7319 1 10UF 10UF 2.0V 2 6.3V SM
150K R7316 1
C7316 20% 20% POLY-TANT
2 X5R
10
21
6.3V 6.3V 1 2 3 603
1% 100K 2 2 CASE-B2-SM1 1
0.01UF 1 1 X5R X5R
1/16W
MF-LF
1%
1/16W
10% R7317 R7318 603 603
16V
2
402 MF-LF 2 CERM 200K 66.5K PLACE_NEAR=J3100.202:3mm PLACE_NEAR=J3100.202:1mm
402 402 1% 1%
DDRREG_P1V35_L 2
1/16W 1/16W
Q7319 MF-LF MF-LF C7360, C7361 close to memory
402 402
3 D SSM3K15FV
2 2
2 C7350 1
(DDRREG_VDDQSNS)
0.22UF MIN_LINE_WIDTH=0.2 mm
SOD-VESM-HF
NOSTUFF
XW7300 10%
SM 10V
CERM 2
402
1
PLACE_NEAR=U7300.7:1mm
2
S G 1 GND_DDRREG_SGND
B
VOLTAGE=0V
MEM_VDD_SEL:GPIO15
R7351
0
GPIO15_MEM_VDD_SEL_1V5_L 1 2 XDP_FC0_PCH_GPIO15 IN 19 23
5%
1/20W
MF
201
PAGE TITLE
1.5V DDR3 Supply

DRAWING NUMBER SIZE

REVISION
R
3.0.0
73 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP5V_S0_CPUIMVP 7 70
R7401
D PP5V_S0_CPUIMVP_VCC
1
10
2 D
MIN_NECK_WIDTH=0.2 MM 5%
VOLTAGE=5V 1/20W
MF =PPVIN_S0_CPUIMVP 7 70
201
7 =PPVCCIO_S0_CPUIMVP
1
C7402 1
C7403
1 2.2UF 2.2UF
C7401 20% 20%
2.2UF 2
10V
2
10V
20% X5R-CERM X5R-CERM
10V 402 402
2
R7479 1
1 X5R-CERM
R7480 402 NO STUFF
54.9 130 R7409
1% 1%
1/20W 1/20W 300
MF MF PLACE_NEAR=U7400.19:2mm 1 2 CPUIMVP_ISNS1_N 50 70 101
IN
201 201 PLACE_NEAR=U7400.29:2mm
2 2 5%
1/20W
46
29
19
MF
201
VCC
VDDA
VDDB
Note: value needs scrubbing
R7406
R7403 300
180K 1 2 CPUIMVP_ISNS1_P IN 50 70 101
U7400 1 2
5%
MAX15119GTM 1% 1/20W
QFN 1/20W MF
13 1
70 OUT CPUIMVP_AXG_PWM2 DRVPWMB TONB CPUIMVP_TONB MF
R7402 201
201
48
180K R7407
37 TONA 1 2
70 OUT CPUIMVP_PWM3 DRVPWMA CPUIMVP_TONA
300
1% 1 2 CPUIMVP_ISNS2_P 50 70 101
45 25 IN
70 69 IN CPUIMVP_ISUM3_P CSPA3 CRITICAL BSTA1 CPUIMVP_BOOT1 OUT 6 70 1/20W
MF 5%
93 46 45 10 CPU_PROCHOT_L 4 VRHOT* DHA1 27 CPUIMVP_UGATE1 6 70 201 NO STUFF 1/20W
OUT OUT MF
LXA1 26 CPUIMVP_PHASE1 OUT 6 70
C7408 201
150PF
1
C7450 92 OUT CPUIMVP_PGOOD 24
POKA DLA1 28
CPUIMVP_LGATE1 OUT 6 70
1 2 CPUIMVP_ISUM_R R7408
43PF 92 CPUIMVP_AXG_PGOOD 12 POKB CSPA1 42
CPUIMVP_ISUM1_P 70 300
5% OUT OUT 1 2 CPUIMVP_ISNS3_P IN 50 70 101
50V 10%
2 C0G-CERM 41
47 25V
74 CPUIMVP_VR_ON EN CSPAAVE CPUIMVP_ISUM 5%
C
IN
C
0402 X7R-CERM 1/20W
43 0201
21
CSNA CPUIMVP_ISUM_N IN 70 MF
93 12 IN CPU_VIDSOUT VDIO 3
201
23
FBA CPUIMVP_FBA 69
C7409
93 12 IN CPU_VIDSCLK CLK R7410
22 44 470PF
93 12 IN CPU_VIDALERT_L ALERT* CSPA2 CPUIMVP_ISUM2_P
1 2
1
1 2
34
39
BSTA2 CPUIMVP_BOOT2 OUT 6
CPUIMVP_NTC THERMA 32
70
10%
5%
40
DHA2 CPUIMVP_UGATE2 OUT 6
16V
1/20W
CPUIMVP_NTCG THERMB 33
70
X5R-X7R
MF
LXA2 CPUIMVP_PHASE2 OUT 6
70 201
201
38 31
CPUIMVP_SLEW SR DLA2 CPUIMVP_LGATE2 OUT 6
70
35 14
CPUIMVP_IMAXA IMAXA BSTB CPUIMVP_BOOT1G OUT 6
70
36 16
CPUIMVP_IMAXB IMAXB DHB CPUIMVP_UGATE1G OUT 6 CPUIMVP_ISUMG2_P IN 70
70 70
1 1 OMIT 15 OUT
R7468 R7466 1 1 1
LXB CPUIMVP_PHASE1G OUT 6
5.76K 5.76K R7464 R7462 R7460 8 CSPBAVE DLB 18

CPUIMVP_LGATE1G
70
6
NOSTUFF 301K 301K OUT 70
1% 1%
1/20W 1/20W NONE 1% 1% 11
MF MF NONE 1/20W 1/20W CSPB2
201 201 NONE MF MF 9
2 2
2
0201
2
201
2
201 CSPB1 CPUIMVP_ISUMG1_P IN 70
10
CSNB
6
FBB CPUIMVP_FBB 69
GNDSA
GNDSB
PGNDA
PGNDB
CPUIMVP_ISUM3_P IN 69 70
THRM
PAD
1 1 AGND
CRITICAL CRITICAL
1 1 1
20
49
30
17
R7469 R7467 R7465 R7463 R7461 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CPUIMVP_ISUMG_N 70
IN
100KOHM 100KOHM
200K 137K 137K
XW7400
1
C7418 1
C7419 1
C7414 1
C7415 1
C7416 1
C7417
1% 1% 1%
100PF 100PF 100PF 100PF 100PF 100PF
0402 0402
1/20W 1/20W 1/20W SM
5% 5% 5% 5% 5% 5% NO STUFF
MF MF MF
2 2 2
201
2
201
2
201 2 1 2
25V
CERM 2
25V
CERM 2
25V
CERM 2
25V
CERM 2
25V
CERM 2
25V
CERM
1
C7423
201 201 201 201 201 201 100PF
5%
25V
2 CERM
PLACE_NEAR=U7400.46:1mm 201
B PLACE_NEAR=Q7510.1:1mm
GND_CPUIMVP_SGND
C7452 B
100PF
VOLTAGE=0V 1
C7440 1 2
1000PF
10%
16V 5%
1
C7412
2 X7R R7440 25V 1000PF
201 CERM 10%
10 201 16V
CPU_AXG_SENSE_R 1 2 CPU_AXG_SENSE_N 12 93 2
IN X7R
5% R7412 201 R7413
70 IN CPUIMVP_ISUMG_AVE_P C7441 1 1/20W
MF CPUIMVP_FBA 1
12.7K
2 CPUIMVP_FBA_R 1
10
2 CPU_VCCSENSE_P
69 IN 12 93
1000PF 201
10% 1% 5%
16V 1/20W
X7R 2 1/16W
MF
201 R7441 MF-LF
402 201
10
CPU_VCCSENSE_R 1 2 CPU_VCCSENSE_N 12 93
IN
5%
C7422 1
NO STUFF NO STUFF 1/20W 1000PF

MF 10%
1
C7442 1
C7443 201 16V
X7R 2
1000PF 1000PF R7422 201 R7423
10% 10% 17.4K 10
16V 16V 1 2 1 2
2 2 69 CPUIMVP_FBB CPUIMVP_FBB_R CPU_AXG_SENSE_P IN 12 93
X7R X7R
201 201 1% 5%
PLACE HOLDER PLACE HOLDER 1/16W 1/20W
MF-LF MF
402 201
C7462
100PF
1 2
5%
25V
CERM
201
NO STUFF
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator

DRAWING NUMBER SIZE

REVISION
R
3.0.0
74 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
69 7 =PPVIN_S0_CPUIMVP
THESE TWO CAPS ARE FOR EMC THESE TWO CAPS ARE FOR EMC
NOSTUFF NOSTUFF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C7513 C7514 C7515 C7516 C7517 C7518 C7519 C7523 C7524 C7525 C7526 C7527 C7528 C7529
8
CRITICAL CRITICAL
376S1010 68UF 68UF 10UF 10UF 1UF 0.001UF 0.001UF 376S1010 68UF 68UF 10UF 10UF 1UF 0.001UF 0.001UF
Q7510 10% 10% 10% 10% 10%
Q7510 10% 10% 10% 10% 10%
PHASE 1 PHASE 2
20% 20% 20% 20%
D 16V 16V 16V 50V 50V D 16V 16V 16V 50V 50V
000000000000000000000000
2 16V 2 16V 2 2 2 2 2 2 16V 2 16V 2 2 2 2 2
POLY-TANT POLY-TANT X5R-CERM X5R-CERM X5R X7R X7R POLY-TANT POLY-TANT X5R-CERM X5R-CERM X5R X7R X7R
CASE-D2E-SM CASE-D2E-SM
0805 0805 402 402 402 CASE-D2E-SM CASE-D2E-SM
0805 0805 402 402 402
1 G 2 G
CRITICAL IRF6802SDTRPBF CRITICAL
6 CPUIMVP_BOOT1_RC IRF6802SDTRPBF PLACE_NEAR=Q7510.6:1MM 6 CPUIMVP_BOOT2_RC PLACE_NEAR=Q7510.7:1MM
S S DIRECTFET-SA
MIN_LINE_WIDTH=0.25 MM DIRECTFET-SA R7510 PLACE_NEAR=C7517.1:3MM MIN_LINE_WIDTH=0.25 MM R7520 PLACE_NEAR=C7527.1:3MM
MIN_NECK_WIDTH=0.25 MM CRITICAL MIN_NECK_WIDTH=0.25 MM CRITICAL
0.00075 0.00075
3
DIDT=TRUE
L7510 1%
1W
DIDT=TRUE
L7520 1%
1W
0.36UH-20%-40A-0.00075OHM MF 0.36UH-20%-40A-0.00075OHM MF
D
0612 0612
6 PPVCORE_S0_CPU_PH1_L
1 2 PPVCORE_S0_CPU_PH1 =PPVCORE_S0_CPU_REG 6 PPVCORE_S0_CPU_PH2_L
1 2 PPVCORE_S0_CPU_PH2 =PPVCORE_S0_CPU_REG
D
1 1 2 1 1 2
R7511 7 70 R7521 7 70
1 1
C7511 MIN_LINE_WIDTH=0.5 MM
PIMA104E-SM MIN_LINE_WIDTH=0.5 MM
3 4
C7521 MIN_LINE_WIDTH=0.5 MM
3 4
0 MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM 0 MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
5%
0.22UF SWITCH_NODE=TRUE 152S1019 VOLTAGE=1.25V 5%
0.22UF SWITCH_NODE=TRUE 152S1019 VOLTAGE=1.25V
10% CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N 10% CPUIMVP_ISNS2_P CPUIMVP_ISNS2_N
1/16W 10V VOLTAGE=1.25V 101 69 50 OUT OUT 50 69 101 1/16W 10V VOLTAGE=1.25V 101 69 50 OUT OUT 50 101
1 1
MF-LF 2 MF-LF 2
CERM R7512 CERM R7522
402 SIGNAL_MODEL=EMPTY PLACE_NEAR=C7581.1:1mm 402 PLACE_NEAR=C7582.1:1mm
R7513 1
1
R7523 1
2 402 2 402 1
2.2
5%
R7514 5%
2.2
R7524
69 6 IN CPUIMVP_BOOT1 1/10W 46.4 10.2 69 6 IN CPUIMVP_BOOT2 1/10W 46.4 10.2
1
2
8
7
MIN_LINE_WIDTH=0.25 MM DIDT=TRUE
MF-LF 1% 1% SIGNAL_MODEL=EMPTY MIN_LINE_WIDTH=0.25 MM DIDT=TRUE
MF-LF SIGNAL_MODEL=EMPTY 1% 1% SIGNAL_MODEL=EMPTY
MIN_NECK_WIDTH=0.2 MM 603 1/20W 1/20W MIN_NECK_WIDTH=0.2 MM CRITICAL603 1/20W 1/20W
2 2
MF MF MF MF
NOSTUFF D NOSTUFF
69 6 IN CPUIMVP_UGATE1
CPUIMVP_PH1_SNUB
201
2 2
201 69 6 IN CPUIMVP_UGATE2
Q7525 CPUIMVP_PH2_SNUB
201
2 2
201
1
2
8
7
DIDT=TRUE 6 MIN_LINE_WIDTH=0.5 MM
DIDT=TRUE 6
PLACE_NEAR=C7581.2:1mm PLACE_NEAR=C7582.2:1mm CPUIMVP_ISUM_N
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
D
CRITICAL MIN_LINE_WIDTH=0.5 MM
CPUIMVP_ISUM_N
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
649135PBF MIN_LINE_WIDTH=0.5 MM
OUT 69 70
Q7515
CPUIMVP_PHASE1 DIDT=TRUE CPUIMVP_PHASE2 DIDT=TRUE
69 6 IN OUT 69 70 69 6 IN
DIDT=TRUE
1
C7512 DIDT=TRUE
4 G DIRECTFET_S3C 1
C7522
MIN_LINE_WIDTH=1.5 MM MIN_LINE_WIDTH=1.5 MM
SWITCH_NODE=TRUE
649135PBF
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE 0.001UF
10% CPUIMVP_LGATE2
S 0.001UF
10% R7525 1 1
C7582
69 6 IN
4 G DIRECTFET_S3C C7581 2200PF
R7515 1
CPUIMVP_LGATE1 50V 1 50V
300
69 6 IN 2
CERM MIN_LINE_WIDTH=0.5 MM DIDT=TRUE 2
CERM 10%
DIDT=TRUE MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE 1%
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE S 402
200 2200PF 402
1/20W 2
10V
10% X7R-CERM
3
5
6
NOSTUFF 1% 10V NOSTUFF MF 0201
376S1011
1/20W 2 X7R-CERM 201
2 PLACE_NEAR=U7400.43:1mm
MF 0201
201
376S1011
2
SIGNAL_MODEL=EMPTY
3
5
6
NOSTUFF PLACE_NEAR=U7400.43:1mm CPUIMVP_ISUM2_P
OUT 69
CPUIMVP_ISUM1_P
OUT 69
SIGNAL_MODEL=EMPTY Additonal Input Bulk Caps

CRITICAL
THESE TWO CAPS ARE FOR EMC
Q7530 CRITICAL CRITICAL CRITICAL CRITICAL

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
649136PBF 1 1 1
C7535 1
C7536 1
C7537 1
C7538 1
C7539
S1 C7533 C7534 1 1 1 1 1 1
376S1014 1 68UF 68UF 10UF 10UF 1UF 0.001UF 0.001UF C7570 C7571 C7572 C7573 C7574 C7575
PHASE 3 D
2 2
20%
16V
POLY-TANT
2
20%
16V
POLY-TANT
2
10%
16V
X5R-CERM
2
10%
16V
X5R-CERM
2
10%
16V
X5R
2
10%
50V
X7R
2
10%
50V
X7R
2
68UF
20%
16V 2
68UF
20%
16V 2
68UF
20%
16V 2
68UF
20%
16V 2
68UF
20%
16V 2
68UF
20%
16V
5 CASE-D2E-SM CASE-D2E-SM 0805 0805 402 402 402 POLY-TANT POLY-TANT POLY-TANT POLY-TANT POLY-TANT POLY-TANT
CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM
70 69 7 =PP5V_S0_CPUIMVP 4 G 6 CRITICAL
6 CPUIMVP_BOOT3_RC S R7530 PLACE_NEAR=C7537.1:3MM
3 CRITICAL
0.00075
L7530 1%
C 1
1
C7541
1UF
10%
DIDT=TRUE
SWITCH_NODE=TRUE 6
0.36UH-20%-40A-0.00075OHM
PPVCORE_S0_CPU_PH3_L
1 2 PPVCORE_S0_CPU_PH3 2
0612
1W
MF
1 =PPVCORE_S0_CPU_REG 7 70
C
R7547 16V
R75311
5
2
X5R 1 MIN_LINE_WIDTH=0.5 MM
4 3
10K C7531 MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
5% VDD
402
3.3 0.22UF
SWITCH_NODE=TRUE 152S1019 VOLTAGE=1.25V CPUIMVP_ISNS3_P CPUIMVP_ISNS3_N
1/16W 5% 10%
VOLTAGE=1.25V
1
101 69 50 OUT OUT 50 101
MF-LF 1/16W 10V R7532
2
402 U7541 MF-LF 2
CERM 1 1
MAX17491
402 2 402
2.2
5%
R7533 R7534
1/10W 46.4 10.2 SIGNAL_MODEL=EMPTY
69 CPUIMVP_PWM3 2
PWN TQFN
BST 1 6 CPUIMVP_BOOT3 MF-LF SIGNAL_MODEL=EMPTY 1% 1%
IN
MIN_LINE_WIDTH=0.25 MM 603 1/20W 1/20W
CRITICAL DIDT=TRUE 2
MIN_NECK_WIDTH=0.2 MM MF MF
CPUIMVP_SKIP3 6
1
2
8
7
NOSTUFF
SKIP* DH 8 6 CPUIMVP_UGATE3
CPUIMVP_PH3_SNUB
201
2 2
201
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE CRITICAL 6
CPUIMVP_ISUM_N
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE OUT 69 70
LX D MIN_LINE_WIDTH=0.5 MM
7
6 CPUIMVP_PHASE3 Q7535 1
C7532
DIDT=TRUE
DL 4
DIDT=TRUE
SWITCH_NODE=TRUE 649135PBF 0.001UF
C7583
R7536 1
1
THRM 6 CPUIMVP_LGATE3 4 G DIRECTFET_S3C 10%
GND PAD 50V 2200PF
DIDT=TRUE 2
CERM
300 10%
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE S 1% 10V
3
402
1/20W 2 X7R-CERM
376S1011 NOSTUFF MF 0201
201
2 PLACE_NEAR=U7400.43:1mm
AXG PHASE 1
5
6
3
SIGNAL_MODEL=EMPTY CPUIMVP_ISUM3_P
OUT 69
=PPVIN_S0_CPUAXG THESE TWO CAPS ARE FOR EMC

7 NOSTUFF NOSTUFF
R7556
AXG PHASE 2 1
CRITICAL
C7560
1
CRITICAL
C7561
1
CRITICAL
C7562 1
CRITICAL
C7563 1
C7564 1
C7565 1
C7566
0 68UF 68UF 10UF 10UF 1UF 0.001UF 0.001UF
1 2 6 CPUIMVP_BOOT1G_R 20% 20%
10% 10% 10% 10% 10%
16V 16V 16V 50V 50V
MIN_LINE_WIDTH=0.25 MM 2 16V 2 16V 2 2 2 2 2
5% THESE TWO CAPS ARE FOR EMC POLY-TANT POLY-TANT X5R-CERM X5R-CERM X5R X7R X7R
CASE-D2E-SM CASE-D2E-SM 0805 0805 402 402 402
1/16W DIDT=TRUE CRITICAL CRITICAL CRITICAL CRITICAL
5
1
MF-LF C7551 CRITICAL
1 1 1 1 1 1 1
CPUIMVP_BOOT1G C7555 C7556 C7557 C7558 C7559
69 6 IN 402
0.22UF C7553 C7554
MIN_LINE_WIDTH=0.25 MM 10% D Q7550 68UF 68UF 10UF 10UF 1UF 0.001UF 0.001UF
B B
10V 10% 10% 10% 10% 10%
8
DIDT=TRUE
CERM
2 IRF6802SDTRPBF 20% 20%
16V 16V 16V 50V 50V
CRITICAL CRITICAL CRITICAL PLACE_NEAR=C7564.1:3MM
16V 16V 2 2
402 1 G DIRECTFET-SA
2
POLY-TANT
2
POLY-TANT
2
X5R-CERM X5R-CERM X5R
2
X7R
2
X7R
Q7550 L7560 R7560
MIN_LINE_WIDTH=0.5 MM CASE-D2E-SM CASE-D2E-SM
0805 0805 402 402 402 D 0.36UH-20%-40A-0.00075OHM
CPUIMVP_UGATE1G IRF6802SDTRPBF
69 6 IN MIN_NECK_WIDTH=0.2 MM
S 376S1010 CRITICAL
0.00075
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE DIDT=TRUE
PLACE_NEAR=C7557.1:3MM 2 G DIRECTFET-SA 1 2 PPVCORE_S0_AXG2_L
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE GATE_NODE=TRUE
PLACE_NEAR=Q7550.5:1MM 6 CPUIMVP_VSWG2 1%
4
152S1019 R7550 MIN_LINE_WIDTH=0.5 MM

1W
MF
CRITICAL
S MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
VOLTAGE=1.05V
0612
69 6 IN CPUIMVP_PHASE1G 0.00075
376S1010 152S1019 1 2 =PPVCORE_S0_AXG_REG 7 49 70
L7550
3
1%
MIN_LINE_WIDTH=1.5 MM DIDT=TRUE
1W NOSTUFF 3 4
MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE 0.36UH-20%-40A-0.00075OHM MF 1

Schem, MLB - Kepler - 2phase, J31: Schematic / PCB #'S

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Schem, MLB - Kepler - 2phase, J31: Schematic / PCB #'S

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8 7 6 5 4 3 2 1

D (.csa) Date (.csa) Date (.csa) Date

8 Signal Aliases K18_MLB 53 WELLSPRING 1 J30_MLB 98 Thunderbolt Constraints T29_REF

9 CPU DMI/PEG/FDI/RSVD J5_MLB 54 WELLSPRING 2 J31_LINDA 99 SMC Constraints J31_YONAS

16 PCH SATA/PCIe/CLK/LPC/SPI J31_ANNE 61 AUDIO: SPEAKER AMP J31_AUDIO

20 PCH POWER J5_MLB 65 PBus Supply & Battery Charger J31_JACK

21 PCH GROUNDS J5_MLB 66 System Agent Supply J31_JACK

22 PCH DECOUPLING J5_MLB 67 5V / 3.3V Power Supply J31_JACK

23 CPU & PCH XDP J31_ANNE 68 1.5V DDR3 Supply J31_JACK

27 DDR3 SO-DIMM Connector A K92_SUMA 72 Misc Power Supplies J31_JACK

28 DDR3 Byte/Bit Swaps K92_SUMA 73 Power FETs J31_MARY

29 DDR3 SO-DIMM Connector B K92_SUMA 74 Power Control 1/ENABLE J31_MARY

30 SD Card Connector J31_YONAS 75 KEPLER PCI-E J31_SREE

31 DDR3/FRAMEBUF VREF MARGINING J31_ANNE 76 KEPLER CORE/FB POWER D2_MLB_2P

32 X19/ALS/CAMERA CONNECTOR J30_MLB 77 KEPLER FRAME BUFFER I/F J31_SREE

33 Thunderbolt Host (1 of 2) T29_REF 78 1V05 GPU / 1V35 FB POWER SUPPLY J31_JACK

36 ETHERNET PHY (CAESAR IV) K91_ERIC 81 KEPLER LVDS/DP/GPIO J31_SREE

38 FireWire LLC/PHY (FW643) K18_MLB 83 KEPLER PEX PWR/GNDS J31_SREE

40 FireWire Connector T27_REF 85 LVDS Display Connector K18_MLB

42 External A USB3 Connector J31_LINDA 87 Thunderbolt MUXing A J31_WILL

U8000 INTEL CPU

GPIO FDI DMI RTC

SPI FAN CONN AND CONTROL

LVDS CONN PG 27,29

Apple Inc. 051-9585 D

PPVBAT_G3H_CHGR_R PGOOD (PAGE 39)

Apple Inc. 051-9585 D

- Bar Code Labels / EEEE #’s

639-3861 PCBA,MLB_2P,FSB,2.3,MOL,512_SAM,FAIR,J31,F32C J31_CMNPTS,SODIMM:MOLEX,CPU:2_3GHZ,FB_512_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F32C 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F327] CRITICAL EEEE:F327

639-3862 PCBA,MLB_2P,FSB,2.6,MOL,1G_HY,FAIR,J31,F325 J31_CMNPTS,SODIMM:MOLEX,CPU:2_6GHZ,FB_1G_HYNIX_A_DIE,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F325 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F32C] CRITICAL EEEE:F32C

639-3863 PCBA,MLB_2P,FSB,2.6,FOX,1G_SAM,REN,J31,F324 J31_CMNPTS,SODIMM:FOXCONN,CPU:2_6GHZ,FB_1G_SAMSUNG,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F324 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F325] CRITICAL EEEE:F325

639-3864 PCBA,MLB_2P,FSB,2.7,FOX,1G_HY,REN,J31,F328 J31_CMNPTS,SODIMM:FOXCONN,CPU:2_7GHZ,FB_1G_HYNIX_A_DIE,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F328 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F324] CRITICAL EEEE:F324

639-3865 PCBA,MLB_2P,FSB,2.7,MOL,1G_SAM,FAIR,J31,F329 J31_CMNPTS,SODIMM:MOLEX,CPU:2_7GHZ,FB_1G_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F329 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_F328] CRITICAL EEEE:F328

D 607-9557 CMN PTS,PCBA,MLB_KEPLER,J31 J31_COMMON

607-9557 1 CMN PTS,PCBA,MLB_KEP_2P,J31 CMNPTS CRITICAL J31_CMNPTS

BOM GROUP BOM OPTIONS

J31_PVT VREF:PROD,XDP,XDP_CPU:BPM,BKLT:PROD,LOADISNS:NO,XWLOADISNS:NO TABLE_ALT_ITEM

J31_DEVEL:ENG DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,GMUX_JTAG_CONN,LPCPLUS_CONN:YES,BKLT:ENG,S0PGOOD_ISL,CPURIPPLE_ENG,LOADISNS:YES,XWLOADISNS:YES,DEBUG_ADC TABLE_ALT_ITEM

J31_DEVEL:FSB DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,LPCPLUS_CONN:YES,BKLT:PROD,S0PGOOD_ISL,LOADISNS:YES,XWLOADISNS:NO TABLE_ALT_ITEM

341S3099 1 IC,TP PSOC,K9x,DVT,PVT,J31 U5701 CRITICAL TPAD_PROG:PROTO0

341S3489 1 IC,TP PSOC,PIB,J31 U5701 CRITICAL TPAD_PROG:PIB

341S3522 1 U5701 CRITICAL TPAD_PROG:FSB

376S0855 376S0613 ALL Diodes alt to Toshiba dual N-FET

138S0676 138S0691 ALL Murata alt to Samsung cap

BOM GROUP BOM OPTIONS TABLE_ALT_ITEM

VREF:PROD VREFDQ:M1_M3,VREFCA:LDO TABLE_ALT_ITEM

VREF:ENG_M3 VREFDQ:M1_M3,VREFCA:LDO_DAC TABLE_ALT_ITEM

VREF:ENG_LDO VREFDQ:M1_DAC,VREFCA:LDO_DAC TABLE_ALT_ITEM

335S0852 1 IC,GPUROM,J31,BLANK U8701 CRITICAL GPUROM:BLANK

514-0788 514-0671 ALL Acon (with liteon) alt to Acon

337S4266 1 IC,CPU,IVB,S,R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA U1000 CRITICAL CPU:2_3GHZ

337S4267 1 IC,CPU,IVB,S,R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA U1000 CRITICAL CPU:2_6GHZ

335S0663 1 IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC U3990 CRITICAL ENETROM_BLANK

337S4268 1 IC,CPU,IVB,S,R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA U1000 CRITICAL CPU:2_7GHZ

341S3096 1 IC,ENET ROM,1MBIT,DVT,PVT,K90i/K91x,J31 U3990 CRITICAL ENETROM_PROG:PROTO3

B 337S4269 1 IC,PCH,PPT,C1,SLJ8C,PRQ,BD82HM77 U1800 CRITICAL

Murata alt to TDK cm mode filter

341S3492 1 IC,PRGRMD,ENET,SPI ROM,FSB,J30/J31 U3990 CRITICAL ENETROM_PROG:FSB B

338S1072 1 IC,ASSP,LIGHTRIDGE,PRQ,S LJJY,FCBGA,15X15MM,C1 U3600 CRITICAL T29:YES

338S0895 1 IC,SMC,HS8/2117,9MMX9MM,TLP U4900 CRITICAL SMC_BLANK

338S0753 1 U4100 CRITICAL 341S3258 1 U4900 CRITICAL SMC_PROG:PROTO0

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12 IC,SMC,DEVELOPMENT-PROTO0,J31