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2.3 BUILD Sequential Logic Circuit
2.3 BUILD Sequential Logic Circuit
3 BUILD
SEQUENTIAL
LOGIC CIRCUIT
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1
Learning Outcome
1. Define sequential logic circuit
2. List the types of flip flop
• SR flip flop
• Clocked SR Flip-Flop,
• JK Flip-Flop.
• T Flip-Flop
• D flip-flop
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LEARNING OUTCOME
3. Draw the block symbol and logic circuit of SR,
Clocked SR JK, T and D flip flop
4. Develop truth table of SR, Clocked SR JK, T
and D flip flop
5. Draw timing diagram of SR, Clocked SR JK, T
and D flip flop
6. Describe registers
7. Describe memory organisation
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SEQUENTIAL LOGIC CIRCUIT
• Define Sequential Circuits ?
• Sequential logic circuits is circuits is the type of a
digital system that does not only depend on current
input, but also the previous history of the system.
• For that reason sequential logic circuit require
memory to function.
• Sequential circuits have loops - these enable
circuits to receive feedback.
• The building block used to construct device that
store data is called Flip flop.
2.3 SEQUENTIAL CIRCUITS
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• The output of circuit depends on
the previous output and the present
inputs.
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COMBINATIONAL VS SEQUENTIAL LOGIC
CIRCUIT
Combinational logic circuit Sequential logic circuit
refers to circuits whose output is Circuits whose outputs depends not
strictly depended on the present value only on the present input value but
of the inputs also the past input value are known
as sequential logic circuits.
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INTRODUCTION – FLIP FLOP
Figure 4.0.1 : General Flip flop
symbol • They are 1 (HIGH) or 0
(LOW).
Q
Inputs Normal
output
• Whenever we refer to
the state of flip flop, we
Q refer to the state of its
Inverted
normal output (Q).
Output
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THE USED OF FLIP FLOP
• For Memory circuits
• For Logic Control Devices
• For Counter Devices
• For Register Devices
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SR FLIP FLOP
• The most basic Flip Flop is called SR Flip Flop.
• The basic SR flip flop is an asynchronous device.
• In asynchronous device, the outputs is immediately
changed anytime one or more of the inputs change
just as in combinational logic circuits.
• It does not operate in step with a clock or timing.
• These basic Flip Flop circuit can be constructed
using two NAND gates latch or two NOR gates
latch.
• SR Flip Flop Active Low = NAND gates 12
• Two outputs,
Q Q as normal
11 output and ¯ as inverted
output and feedback
mechanism.
2 1 0
1
16
16
SR FLIP FLOP - NAND GATE
2 0 1
0
17
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SR FLIP FLOP - NAND GATE
• Normal Resting • Input S=1 , R=1 ,
State Figure 4.1.4.d • This is the normal
resting state of the
1
1 0
circuit and it has no
0
0 effect of the output
states.
• Output Q and ¯ will
Q
remain in whatever
1
2 1 1
1 state they were in
prior to the
occurrence of this
input condition.
• It works in HOLD 18
mode of operation. 18
SR FLIP FLOP - NAND GATE
• From the description of the NAND gate
latch operation, it shows that the SET
and RESET inputs are active LOW. • Figure 4.1.5 : SR NAND gate
• The SET input will set Q = 1 when SET latch Truth Table
is 0 (LOW). RESET input will reset Q =
0 when RESET is 0 (LOW)
S R Q Q
¯ STATUS
• In the prohibited/INVALID state both
outputs are 1.
0 0 1 1 INVALID
• This condition is not used on the RS
flip-flop.
0 1 1 0 SET
• The set condition means setting the
output Q to 1. RESET
1 0 0 1
• The reset condition means resetting
(clearing) the output Q to 0. The last 1 1 Q Q
¯ HOLD
row shows the disabled, or hold, (NoChange)
condition of the RS flip-flop. The
outputs remain as they were before the
hold condition existed. There is no
change in the outputs from the 19
previous states.
R S
Q R
Q
¯Q
Q ¯
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SR FLIP FLOP
SR Flip Flop logic Symbol
SR NAND gate latch Truth Table
input output S R Q ¯
Q
STATUS
0 0 1 1 INVALID
0 1 1 0 SET
1
1 0 0 1 RESET
1 1 Q ¯
Q
HOLD
2 (NoChange)
• The construction is
similar to the NAND
latch except that the
Q
normal output Q and
inverted output ¯
• Figure 4.1.6: SR NOR have reversed
(Active HIGH) Logic circuit positions.
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SR FLIP FLOP - NOR GATE
The analysis of a SR FLIP FLOP
SR FLIP FLOP NOR NOR :
(Active HIGH) Logic circuit
* S = 0, R = 0; This is the normal
mode operation.
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SR FLIP FLOP - NOR GATE
• S = 1, R = 0; This will set Q to 1, it works in SET mode operation.
• S = 1, R = 1; This condition tries to set and reset the NOR gate
latch at the same time, and itQproduces Q = ¯ = 0. This is an
unexpected condition and are not used.
Since the two outputs should be inverse of each other. If the inputs
are returned to 1 simultaneously, the output states are
unpredictable.
This input condition should not be used and when circuits are
constructed, the design should make this condition
SET=RESET = 1 never arises.
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SR FLIP FLOP - NOR GATE
• From the description of • Figure 4.1.7 : SR NOR gate
the NOR gate latch latch Truth Table
operation, it shows that
S R Q ¯ STATUS
the SET and RESET Q
_ HOLD
inputs are Active HIGH. 0 0 Q Q (NoChange)
0 1 0 1 RESET
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SR NOR FLIP FLOP -
WAVEFORMS
• Example 4.1.2: Determine the • Exercise 4.1.2 : Determine the
output of NOR gate latch which output of NOR gate latch which
Q initially 0 for the given input Q initially 1 for the given input
waveforms. waveforms.
S S
R R
Q Q
Q
¯ Q
¯
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SR NOR FLIP FLOP
S R Q ¯ STATUS
Q
_ HOLD
0 0 Q Q (NoChange)
0 1 0 1 RESET
1 0 1 0 SET
SR NOR 1 1 0 0 INVALID
(Active HIGH) Logic circuit
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THE CLOCK
• In synchronous device, the exact
times at which any output can change
states are controlled by a signal
commonly called the clock.
• The clock signal is generally a
rectangular pulse train or a square
wave as shown in figure 4.9.
• The clock is distributed to all parts of
the system, and most of the system
outputs can change state only when
the clock makes a transition.
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THE CLOCK
• When the clock changes from a LOW state to a HIGH
state, this is called the positive-going transition (PGT)
or positive edge triggered.
• When the clock changes from a HIGH state to a LOW
state, it is called negative going transition (NGT) or
negative edge triggered.
Figure 4.2.1: Clock Pulse-Train Enable
Disable
(a) Positive going transition
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CLOCKED SR FLIP FLOP
• Additional clock input is
added to change the SR
flip-flop from an element • Figure 4.2.2 : PGT Clocked
used in asynchronous SR Flip flop symbol
sequential circuits to one,
which can be used in
synchronous circuits.
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Clocked SR Flip Flop
• Example 4.2.1: Determine the • Exercise 4.2.1: Determine the
output of PGT clocked SR flip flop output of PGT clocked SR flip flop
which Q initially 0 for the given which Q initially 1 for the given
input waveforms input waveforms.
Cp Cp
S
S
R R
Q
Q
¯ ¯
Q
Q
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CLOCKED SR FLIP FLOP
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CLOCKED SR FLIP FLOP
• Example 4.2.2: Determine the • Exercise 4.2.2: Determine the
output of NGT clocked SR flip flop output of NGT clocked SR flip flop
which Q initially 0 for the given which Q initially 1 for the given
input waveforms input waveforms.
Cp Cp
S S
R R
Q Q
¯
Q
¯
Q
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JK FLIP FLOP - SYMBOL
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JK FLIP FLOP – TRUTH TABLE AND
LOGIC CIRCUIT
Figure 4.3.3: Truth Table • Figure 4.3.4: JK FLIP FLOP
for JK Flip Flop LOGIC CIRCUIT
clock
J K Q Q
¯ STATUS
_
0 0 Q Q HOLD
(No Change)
0 1 0 1 RESET
1 0 1 0 SET
_ Toggle
1 1 Q Q
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JK FLIP FLOP - WAVEFORMS
Example 4.3.1 : Determine the output of PGT clocked JK flip flop for
the given input waveforms which the Q initially 0.
Clk
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JK FLIP FLOP - WAVEFORMS
Exercise 4.3.1:Determine the Exercise 4.3.2:Determine the
output output
of NGT clocked JK flip flop for the of PGT clocked JK flip flop for the
given input waveforms which the given input waveforms which the
Q initially 0. Q initially 0.
Cp Cp
J J
K K
Q Q
Q̄ ¯Q
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T FLIP FLOP - SYMBOL
• The T flip flop has only • Figure 4.5.1: Symbol for T
Flip Flop
the Toggle and Hold T
Operation. CP
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T FLIP FLOP – LOGIC CIRCUIT
T
T
Cp
Figure 4.5.3: Logic circuit for T Flip Flop
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T FLIP FLOP – WAVEFORMS
Example 4.5.1 : Determine the output of PGT T flip flop for
the given input waveforms which the Q initially 0.
Clk
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T FLIP FLOP – WAVE FORMS
Exercise 4.5.1 : Determine the Exercise 4.5.2 : Determine the
output of output of
PGT T flip flop for the given NGT T flip flop for the given
input input
waveforms which the Q initially waveforms which the Q initially
0. 0.
Cp Cp
T T
Q Q
Q Q
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D FLIP FLOP
• Also Known as Data Flip flop • Figure 4.6.1 :
• Can be constructed from RS • D Flip flop symbol
Flip Flop or JK Flip flop by
addition of an inverter.
• Inverter is connected so that
the R input is always the
inverse of S (or J input is
always complementary of K).
• The D flip flop will act as a
storage element for a single
binary digit (Bit).
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D FLIP FLOP - SYMBOL
• PGT • NGT
Positive Edge Negative Edge
Q Q
D D
D D
Flip Flop Flip Flop
Clk Clk Q
Q
Figure 4.6.2 : D Flip flop symbol using JK Flip Flop / SR Flip Flop
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D FLIP FLOP- LOGIC CIRCUIT-TRUTH
TABLE
• Figure 4.6.3: Logic • Figure 4.6.4: Truth
circuit for D Flip Flop Table for D Flip Flop
clock status
D Q Q
¯
RESET
0 0 1
1 1 0 SET
Cp
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46
D FLIP FLOP – WAVEFORMS
Example 4.6.1 : Determine the output • Exercise 4.6.1 Determine the
of output of NGT D flip flop for the
PGT D flip flop for the given input given input waveforms, which
waveforms which the Q initially 0. output Q initially 0.
Cp Cp
D D
Q Q
Q Q
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T FLIP FLOPS AND D FLIP FLOPS CAN BE
BUILT USING JK FLIP FLOP
• The JK flip flop is • Figure 4.7.1 : D Flip flop
considered as a universal symbol using JK Flip Flop /
flip flop. SR Flip Flop
• A combination of Jk flip
flop and an inverter can
construct a D Flip Flop as
shown in Figure 4.18 • Figure 4.7.2 : T Flip flop
symbol using JK Flip Flop /
• It also can construct T T
SR Flip Flop
Flip Flop by combine
both J and K inputs with
HIGH level input as 48
• control signal, labelled load, controls writing into the register from signal
lines, D11 through D18.
• These lines might be the output of multiplexers.
• so that data from a variety of sources can be loaded into
the register.
SHIFT REGISTER
• A shift register accepts and/or transfers
information serially.
• Figure below shows a 5-bit shift register
constructed from clocked D flip-flops.
• Data are input only to the leftmost flip-flop.
SHIFT REGISTER
With each clock pulse, data are shifted to the right
one position, and the rightmost bit is transferred
out.
CONT…
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PRIMARY STORAGE
• is the top level and is made up of CPU registers, CPU cache
and memory which are the only components that are directly
accessible to the systems CPU.
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TERTIARY STORAGE
• is mainly used as backup and archival of data and
although based on the slowest devices can be
classed as the most important in terms of data
protection against a variety of disasters that can
affect an IT infrastructure.