Embedded Systems - Spring 2019 - HW2

Bishoy Boshra Labib

900132990
March 13, 2019

1
Consider an embedded system made of a microcontroller that has 12-bit ADC and an SPI
master controller. An external SPI SRAM (23K256) is connected to the microcontroller.
The function of the embedded system is to acquire an analog signal at a rate of 100ksps and
store the samples into the external serial SRAM. The SPI clock could be one of the following
options: 500KHz, 1MHz, 2MHz, 5MHz, 10MHz, 25MHz and 50MHz.

a) If you use single byte write with the 23K256, what is the minimum SPI clock?

b) If you use sequential writes with the 23K256, what is the minimum SPI clock?

Justify your answers.1

i. Byte mode. Number of cycles per sample = 2 × (8 + 16 + 8) = 64 cycles. Minimum

frequency = 64 × 100K = 6.4M Hz. Out of the given options, we would have to go for
10M Hz.

Byte write.
1
The datasheet was obtained at http://www.alldatasheet.com/ on 2019.03.12.

1
 ii. Sequential mode. Number of cycles per sample = 8+16+2×8 = 40 cycles. Minimum
frequency = 40 × 100KHz = 4M Hz. Out of the available options, we would have to
go for 5M Hz.

Sequential write.

2
We want to sample the output from a microphone using a 12-bit ADC. The ADC Vref+ is
connected to 3.3V and Vrefis connected to GND. The microphone produces an output in the
range of 0-30mV.

a) What is the effective sample size?

b) To increase the effective sample size, we need to amplify the signal before applying it
to the input of the ADC.

Design an amplifier using an OPAMP to increase the effective sample size.

a) The maximum Vref is 3.3V corresponding to 212 − 1 = 4095. A maximum Vin of 0.03V
would correspond to 0.03/3.3 × 4095 ≈ 37, which would use 6 bits. Thus, the effective
sample size is 6, rather than 12, bits.

b) We would use a simple non-inverting amplifier, which would magnify the input voltage
by a factor of 3.3/0.03 = 110. The design is shown in the figure below.

2
 Non-inverting amplifier with a gain factor of 110

3
An ADC input is connected to 4 × 1 analog multiplexor. A timer is used to generate a peri-
odic interrupt to start the conversion. The timer ISR selects one of the multiplexor 4 inputs
the start the conversion. The ADC end of conversion causes another interrupt. The ADC
ISR reads the converted sample then writes it to the SRAM. If the 4 signals connected to the
multiplexor inputs are sampled at different rates (10ksps, 20ksps, 40ksps and 80ksps). What
is the timer ISR frequency? Justify your answer.

Solution 1
One possible design is to trigger the timer ISR at a frequency of (80ksps), which is the
highest signal sampling rate.
Each call to the timer ISR would sample one or more signals, depending on the index of
the interrupt, which can be kept track of using a global variable. The first signal (frequency of
10KHz) would be sampled once every 8 calls to the timer ISR, the second signal (frequency
of 20KHz) once every 4 calls, the third (frequency of 40KHz) once every 2 calls, and the
fourth (frequency of 80KHz) would be sampled at each call.
Execution flow:
i. Main thread halts (e.g. in an empty loop) till the next timer interrupt.
ii. The timer ISR would start conversion on one of the signals, and will halt (e.g. in an
empty loop) until conversion is done.
iii. Once conversion is done, execution switches from the timer ISR to the ADC ISR, which
saves the converted value.

3
 iv. Execution returns from the ADC ISR to the timer ISR, which will break out of the
empty loop, and start sampling the following signal (if any).

v. After the timer ISR ends, execution returns to the main thread, which halts until the
next timer interrupt.
Requirements for this solution:
i. Nested interrupts have to be allowed, since the timer ISR must be interrupted by the
ADC ISR, which then must have a higher priority than the timer ISR.

ii. It is assumed that the longest possible execution time of the timer ISR, which occurs
when all 4 signals need to be sampled, must not exceed 1/80K = 12.5µs. Thus,
sampling and converting one signal must be doable in no more than ≈ 3µs.
A pseudo-code for this solution is shown below.
int timer_isr_idx = 0;

void initialize () {
/* Configure system timer to trigger timer_ISR
* at a frequency of 80 Ksps .
* Perform other required initializations .
*/
}

void main () {
initialize ();
while (1) {
// Do nothing , waiting for periodic timer interrupts .
}
}

void timer_ISR () {
if (( timer_isr_idx & 0 b111 ) == 0) {
// Signal 0 is sampled at a frequency of 10 K Hz .
sample_signal (0);
}
if (( timer_isr_idx & 0 b11 ) == 0) {
// Signal 1 is sampled at a frequency of 20 K Hz .
sample_signal (1);
}
if (( timer_isr_idx & 0 b1 ) == 0) {
// Signal 2 is sampled at a frequency of 40 K Hz .
sample_signal (2);

4
 }
// Signal 3 is sampled at a frequency of 80 K Hz .
sample_signal (3);

++ timer_isr_idx ;
}

void sample_signal ( const int sample_idx ) {

sampling_done = false ;
signal_mux_select ( sample_idx );
start_sampling ();
while (! sampling_done ) {
// Do nothing , waiting for the end - of - conversion interrupt .
}
}

void ADC_ISR () {
// This should be called at the end of conversion .
r ep or t_converted_signal_sample ();
sampling_done = true ;
}

Solution 2
One possible design is to trigger the timer ISR at a frequency of (320ksps), which is 4 times
the highest signal sampling rate.
Each call to the timer ISR would sample zero or one signals, depending on the index
of the interrupt, which can be kept track of using a global variable. Four consecutive calls
of the timer ISR would be associated with each of the four signals respectively, with each
call deciding whether or not to sample its associated signal based on the desired sampling
frequency for that signal.
The first signal (frequency of 10KHz) would be sampled once every 32 calls to the timer
ISR, the second signal (frequency of 20KHz) once every 16 calls, the third (frequency of
40KHz) once every 8 calls, and the fourth (frequency of 80KHz) would be sampled once
every 4 calls.
Requirements for this solution:
i. Nested interrupts have to be allowed, since the timer ISR must be interrupted by the
ADC ISR, which then must have a higher priority than the timer ISR.

ii. It is assumed that the longest possible execution time of the timer ISR, which occurs
when a signal is sampled, must not exceed 1/320K = 3.125µs. Thus, sampling and
converting one signal must be doable in no more than ≈ 3µs.

5
 Advantages:
i. This solution ensures the uniformity of the sampling intervals for each individual signal.

ii. This solution requires the same bound of 3µs on the sampling and conversion time, as
the previous solution.
Disadvantages:
i. In 32 consecutive calls, only 1 + 2 + 4 + 8 = 15 calls actually sample signals. The other
17 calls incur unused overhead.
A pseudo-code for the methods differing from solution 1 is shown below.
int timer_isr_idx = 0;

void initialize () {
/* Configure system timer to trigger timer_ISR
* at a frequency of 320 Ksps .
* Perform other required initializations .
*/
}

void timer_ISR () {
if (( timer_isr_idx & 0 b11 ) == 0) {
// This call is associated with signal 0.
// To have a frequency of 10 K Hz , we will only
// take a sample once every 8 associated calls .
if (( timer_isr_idx & 0 b11100 ) == 0) {
sample_signal (0);
}
} else if (( timer_isr_idx & 0 b11 ) == 1) {
// This call is associated with signal 1.
// To achieve a frequency of 20 K Hz , we will only
// take a sample once every 4 associated calls .
if (( timer_isr_idx & 0 b1100 ) == 0) {
sample_signal (1);
}
} else if (( timer_isr_idx & 0 b11 ) == 2) {
// This call is associated with signal 2.
// To achieve a frequency of 40 K Hz , we will only
// take a sample once every 2 associated calls .
if (( timer_isr_idx & 0 b100 ) == 0) {
sample_signal (2);
}

6
 } else {
// This call is associated with signal 3.
// To achieve a frequency of 80 K Hz , we will take
// a sample with each associated call .
sample_signal (3);
}

++ timer_isr_idx ;
}