AUDIO

S/PDIF Output
For OSCAR and other digital audio-equipment
Design by T. Giesberts

The standard MP3 CD player is not provided with an S/PDIF-output that

would have enabled the transmission of digital audio signals to other
equipment. With the aid of this circuit, designed around an IC from
Crystal, an optical and coaxial S/PDIF signal is generated from a kind of
I2S signal in the OSCAR MP3-player.

Althoiugh the OSCAR MP3 player is

fitted with analogue audio outputs
that may be connected to other hi-fi
equipment or the line input of a
sound card, it would be easier and
less lossy to transfer the signal in
digital form to another piece of
equipment with digital input, espe-
cially when recording tracks using,
for instance, a DAT- or MD-recorder.
As standard, OSCAR does not
possess an output that provides a
digital audio signal in usable form.
However, on the main circuit board
is a connection that provides digital
audio data in a ‘raw’ format. This
signal must first be correctly
encoded with additional information
bits and then transmitted with the
correct bi-phase modulation and
amplitude.
The CS8402A from Crystal is an
IC that can do all these tasks by
itself, hence the name ‘digital audio
interface transmitter’. Around this IC
is some circuitry that translates the
‘raw’ signal from OSCAR to S/PDIF.
In the first instance, this circuit
was designed for use with OSCAR,
however it is universally applicable
because almost all the hardware
modes of the CS8402A are available
to be selected. Two DIP switches
and two jumpers enable the circuit
to support various formats.

28 Elektor Electronics 10/2000

 AUDIO

The CS8402 has already appeared M2 M1 M0

in various projects (such as the Sam- 23 22 21
8
pling Rate Converter from October SDATA
Serial Audio
6
’96, 20-bit A/D Converter from SCK Port
Logic
7 Aux
December ’96 and the S/PDIF Test FSYNC
20
Generator from July/August ’99), so 10
Biphase
Mark Line TXP
C C Bits Mux
we will limit ourselves to the most 11
Encoder Driver
TXN
U Registers 17
important aspects. In any case, to V
9 CRC
*
enable a better insight into the over-
U Bits
all functionality of the IC, Figure 1
16
shows once again the block diagram Validity Timing RST
of the CS8402A. Additional informa- Preamble *
tion can be found on the Cirrus Logic
web site. Parity

2 3 24 4 1 13 14 12 15 5

The circuit (H)PRO FC0 FC1 C2

(L)PRO C1 TRNPT C6
C3 C8 C9 C15
C7 EM1 EM0 C9 * professional mode only
CBL MCK
000131-12

In Figure 2 you can see the entire

schematic for the converter circuit. Figure 1. Internal architecture of the CS8402A.
As previously mentioned, the
CS8402A takes care of the complete
conversion from raw audio data to on the PCB pin of the same name). It not selected) the master clock MCK amounts
S/PDIF. Besides the TOSLINK module is then routed via header JP1 to pin 5 to 128?Fs. Because of the presence of the
for the optical output, the only other of IC1. To make the circuit as univer- divide-by-twos MCK may also take the values
active elements are two HCT logic sally applicable as possible, two of 256?Fs or 512?Fs. This is selectable with
ICs (dual D flip-flops). divide-by-two circuits (IC2a and Jumper 1 (JP1). The divisors /4, /2 and /1 can
The master clock signal MCK for IC2b) are connected to pin 3 of K1. be seen next to JP1 on the PCB overlay. The
the CS8402A arrives at pin 3 of K1 (or Normally (when transparent mode is latter connects the MCK input of the CS8402A

5V 5V IC4
R8
TOTX173
4Ω7
3
R7
2
10 3 4 1 S2 4 3 2 1 S1 12 10 9 11 13 14 15 16 8k2
L1 R2 4
S R S R
C4
10k

12 9 2 5
D D
IC2b IC2a 1 OPTO
100n
11 8 3 6 47µH
C C 5 6 7 8 5 7 8 6 4 3 2 1

C6 C5
R4 K2
100n 47µ 75Ω
25V TR1
3
JP1 COAX
270Ω

MCK R3
1 2 ÷4
IC1 19
MCK ÷2 4
3 4 1
5 6 ÷1 5 20 C2
MCK TXP
8 17
SDATA TXN
7 47n
K1 FSYNC
5V 6 2 K3
9 10 SCK PRO R6
FSYNC 3
7 8 21 C1/FC0 2 75Ω
M0 24 5
5 6 22 TRNPT/FC1 COAX
270Ω

M1 4 R5
3 4 23 C6/C2
M2 1
1 2 2 5 C7/C3
D 15 13 20 : 2 : 2 6
IC3a CBL/SBC EM1/C8
14 C3
3 6 EM0/C9
C 9 12
V C9/C15
S R 10 47n
C/SBF
4 1 11 16
U RST 5V
5V
SDATA 10 13 JP2 5 4 3 2 2 3 4 5 6 7 8 9
18
S R 14 14
SCK
12 9 CS8402A C1 C7 C8
D IC2 IC3
IC3b SCK
22µ 7 7
11 8 SCK 100n 100n
C R9 1 4x 10k R1 1 8x 10k 40V

IC2, IC3 = 74HCT74

000131 - 11

Figure 2. Complete circuit diagram of the S/PDIF-converter.

10/2000 Elektor Electronics 29

AUDIO

000131-1 R9 S2
COMPONENTS LIST 4

OUT1
K1 S1 8 R1

H2
H1

R8

R7
Resistors:

L1

IC4
R1 = 8 x 10kΩ resistor array
1
R2 = 10kΩ C6 C4

IC1
R3,R5 = 270Ω C3
R4,R6 = 75Ω

SDATA
C5 TR1
1

SCK MCK
R7 = 8kΩ2 T JP2
R8 = 4Ω7

OUT2
K3

SCK
FSYNC

R2
R9 = 4 x 10kΩ resistor array +5V C1 R6
SCK R5
JP1
IC3 R3
Capacitors: /4
R4
/2
C1 = 22µF 40V radial 0 IC2 /1 C2 K2
C8
C2,C3 = 47nF MCK

H4
H3

OUT3
C4,C6,C7,C8 = 100nF ceramic C7 ROTKELE )C( 1-131000

C5 = 47µF 25V radial

Inductors:
L1 = 47 µH choke
000131-1 (C) ELEKTOR
Semiconductors:
IC1 = CS8402A-CP (Crystal)
IC2,IC3 = 74HCT74
IC4 = TOTX173 (Toshiba)

Miscellaneous:
JP1 = 3-way pinheader + jumper
JP2 = 2 x 3-way pinheader + jumper
K1 = 10-way boxheader
K2,K3 = cinch socket, PCB mount (e.g., T-
709G from Monacor/Monarch)
S1 = 8-way DIP switch
S2 = 4-way DIP switch
TR1 = ferrite ring core, Philips type
TN13/7,5/5-3E25, primary 20 turns,
secondary 2 x 2 turns, lacquered wire 0.5
mm dia.
PCB, order code 000131-1 (see Readers Figure 3. The single-sided PCB designed for the converter. Be sure to fit the three
Services pages)
wire links!

directly to K1 and associated PCB pin.
Depending on the mode, data may be
clocked on the rising or the falling edge of
serial clock SCK. Consequently, an additional
D flip-flop (IC3b) is provided to allow the pos-
sibility of inverting SCK. Jumper J2 selects
the polarity of SCK. To ensure the correct rela-
tionship between data and SCK, the data is
also clocked through a D flip-flop (IC3a). The
divide-by-two MCK clock signal (output Q of
IC2b) is used for this.
The decision to use HCT logic was a con-
scious one because it is possible that the
input signals originate from 3-V logic (such as
the MP3 CD-Player). The CS8402A interprets
signals greater than 2 V as a logic high level.
This arrangement avoids the need for a level
shifter. The L/R clock signal FSYNC (frame
sync) is connected directly, without level
shifting, from K1 to pin 7 of IC1.
SDATA, SCK and FSYNC together form the
audio serial port. Mode select pins M0, M1
and M2 define the format for this port. Seven
different formats may be selected mits a relatively large primary/sec-
this way and the addition of Jumper ondary turns ratio (10:1). A coaxial
2 allows several more (refer to the cable (transmission line) is normally
sidebar for details). A quad DIP terminated at both ends into its
switch S2 and a quad resistor array characteristic impedance. Reflec-
R9 are used to select the mode of tions are avoided this way. An out-
these 3 pins. Although the fourth put signal of 1 Vpp is required on the
switch and resistor remain unused, secondary side in order to deliver
a quad package is used simply 0.5 Vpp into 75 Ω. The large trans-
because it is easier to obtain. former ratio provides a lower output
The CS8402A is provided with impedance and greater bandwidth
eight pins that define the operation (better coupling because the primary
of the transmitter. These are selected winding covers a large part of the
with the aid of S1/R1. Every pin has toroidal core).
two functions depending on whether The application of a transformer
professional- or consumer mode is for the coaxial outputs is motivated
selected (pin 2, S1-8). Table 1 lists as follows: full electrical isolation
the preferred values for use with between various devices will, to a
OSCAR. The functions shown for S1 large extend, avoid ground loops and
apply to consumer mode. other possible sources of trouble.
The output of the CS8402A is A second advantage of the sym-
symmetrical. The 10 Vpp drive signal metrical drive signal for the trans-
for Tr1 for the coaxial outputs per- former is that by using a toroidal

30 Elektor Electronics 10/2000

 AUDIO

core, the primary winding can be winding consists of 20 turns and

split easily into two equal halves. the two secondary windings of two Main settings
The terminals for the primary and
secondary windings are now on
turns each (refer to the drawing of
Figure 4). A 0.5-metre length of
on S1 & S2.
opposite sides of the core and the wire should be adequate. Audio Port modes
connection between the two halves The connection between the cir- S2-3 S2-2 S2-1
M2 M1 M0 Format
of the primary winding acts as a vir- cuit and the audio data source is
0 0 0 FSYNC & SCK output
tual ground point. This suppresses made with a ribbon cable plugged 0 0 1 Left/right, 16-24 bits
crosstalk (and improves electrical into K1 (for connection to OSCAR) or 0 1 0 Word sync, 16-24 bits
isolation at RF). by using the PCB pins next to K1 and 0 1 1 Reserved
Resistors R3 and R5 damp the individual wires for other applica- 1 0 0 Left/right, I2S compatible
outputs of the secondary windings tions. With OSCAR, the ribbon cable 1 0 1 LSB justified, 16 bits
and ensure that the transformers connects via a 10-way insulation dis- 1 1 0 LSB justified, 18 bits
present an resistive load to the placement connector (IDC) to pin- 1 1 1 MSB last, 16-24 bits
CS8402A at all times. R4 and R5 header JP6 (AUX) on the main circuit
mainly define the output impedance board. Pay careful attention to the Sample rates in professional mode
S1-8 S1-4 S1-5
(75 Ω). Capacitors C2 and C3 provide correct orientation.
PRO C6 C7
RF grounding for the screen of the In the case of the MP3 player, the 0 0 0 not defined
coax cables. supply voltage arrives via the ribbon 0 0 1 48 kHz
The circuitry around the cable connected to K1. In the event 0 1 0 44.1 kHz
TOSLINK module IC4 is of a con- that the connections are made using 0 1 1 32 kHz
ventional nature and consists individual wires connected to the
mainly of power supply decoupling. PCB pins next to K1, a separate 5 V Sample rates in consumer-mode
R7 is required for the internal power supply may be connected to S1-8 S1-7 S1-6
adjustment of the module. the power supply pins next to IC3. PRO FC1 FC0
A few remarks before finishing. 1 0 0 44.1 kHz
1 0 1 48 kHz
Practical matters Unfortunately there was no space on
1 1 0 32 kHz
the PCB next to S2 to provide a quick
1 1 1 44.1 kHz, CD-mode
A small circuit board was developed reference to the function of the indi-
for the S/PDIF converter. It is shown vidual DIP switches. S2-1 is the LSB Category code
in Figure 3. The construction will M0, S2-2 is M1 and S2-3 is M2. S1-8 S1-2 S1-3
require little effort. Winding trans- Between R1 and C1 you may find PRO C8 C9
former Tr1 is probably the most diffi- enough room on the board to stick a 1 0 0 general format
cult part. small label with the default settings 1 0 1 PCM encoder/decoder
The output transformer is wound for the functions of S1. 1 1 0 CD
with 0.5 mm diameter enamelled (000131) 1 1 1 DAT
copper wire on a 13?5.5 mm Internet address:
(‘1’= switch closed, ‘0’=switch open)
toroidal core from Philips Cirrus Logic: http://www.cirrus.com
(TN13/7.5/5-3E25). The primary

Table 1. Default
settings for OSCAR.
S1 Pos. Signal description
-1 off C15\ generation status
-2 off C8\ category code
-3 off C9\ category code
-4 off C2\ copy prohibit/permit
-5 on C3\ pre-emphasis
-6 off FC0 sample frequency
-7 off FC1 sample frequency
-8 on PRO\ professional/consumer
mode

S2-1 on
S2-2 off
S2-3 off
S2-4 n.c.

JP1: /4

Figure 4. Showing how the transformer is wound. JP2: SCK

10/2000 Elektor Electronics 31