Uday Intern Project Original 2

Name:Pendem Udaykiran
Affiliation (Institution/Company):RGUKT,Basar
Email:iiit.pendem@gmail.com Phone:8106113419
Title of Internship Program Undertaken:Design and Verification using Verilog Internship Program
Assignment No and Title ………………………………………………………………………………………………………….
Important Instructions:
1) All assignment results should be computer screenshot or computer typed. Handwritten and
scanned copies shall not be considered for evaluation
2) Due date for all assignment submission is 1 Week from the last date of internship
3) All assignment questions should be captured along with solutions/answers.
4) Code snippets, simulation results should be captured properly
5) Use only the JPEG image format for capturing the simulation results and name/label the results
appropriately.
6) The description of answers should be short and crisp. Provide only the required information,
answered copied or cut and pasted from google shall not be considered.
Session 03 : HDL Modelling and Digital Fundamentals
Q: 1). Convert 2DB7 to decimal and binary number system?
Solution : 2DB7 (In Hex) = (7*16^0)+(B*16^1)+(D*16^2)+(2* 16^3) //(converting to decimal)
=(7)+(11*16)+(13*256)+(2*4096)
= 11703 (In Decimal)
2DB7 (In Hex) = 0010 1101 1011 0111 (In Binary).
2. Perform the following operations using 2’c complement method?

i. -39+92
ii. -19-7
iii. 44+45
iv. -1+1
Solution:
i. 92 = (01011100)2 and 39 = (00100111)2
2’s complement of (39): -39 = + (11011001)2
…………………………
discard end carry -> 1 00110101
………………………….
PRIVATE & CONFIDENTIAL
Entuple Technologies and/or Excel VLSI Technologies
-39+92 = ( 00110101)2 = 53
ii. 19 = 00010011 , 2’s complement of (19) : -19 = (11101101)2

7 = 00000111 , 2’s complement of (7): -7 = + (11111001) 2
………………………..
1 11100110
…………………………
Discard end carry and the result is in 2’s complement form since MSB bit is 1 and it is
negative,
Therefore -19-7 = -(00011010)2 = -26
iii. 44 =( 00101100)2
45 = (00101101)2
…………………………..
(01011001)2
…………………………..
44+45 = (01011001) = 89
iv. 1 = (00000001)2
-1 = 2’s complement of (1) = (11111111)2
1 = +(00000001)2
………………………
Discard end carry -> 1 00000000
……………………..
Therefore -1+1 = (00000000)2 = 0
Q: 3). Represent the Boolean expression f (A,B,C) = A’BC’+A’BC+A’B’C’+ABC in SOP and POS forms?
Solution : SOP form: f ( A,B,C) =A’B’C’+A’BC’+A’BC +ABC = m0+m2+m3+m7
POS form : f (A,B,C) = M1*M4*M5*M6=(A+B+C’)(A’+B+C)(A’+B+C’)(A’+B’+C)
The above SOP and POS forms can be written in simplified form by using K-map simplification as :

4. Explain how many bits to be added for detecting error in any 3 bits in the data stream of
10 bits?
Solution: : For error detection of 3 bits minimum Hamming distance required is must be
greater than 3.
If k is the number of extra bits required for error detection and n is the number of total
bits(10)
Since 2^k>=n+k+1
Therefore k=4 satisfies the above equation.
Answer is “4”.
5. Convert Binary code 0101 to gray code and convert gray code 1010 to binary?
Solution:
Session 04 : Verilog Constructs – Part I

1. Compile, remove the syntax errors and determine the output for the following Verilog
code?

//casex example
module casex_example();
reg [3:0] opcode;
reg [1:0] a,b c;
reg [1:0] out;
always @ (opcode a or b or c)
casex(opcode)
4'b1zzx : begin // Don't care 2:0 bits
out = a;$display("@%0dns 4'b1zzx is selected, opcode
%b",$time,opcode); end
4'b01?? : begin // bit 1:0 is don't care
out = b; $display("@%0dns 4'b01?? is selected, opcode
4'b001? : begin // bit 0 is don't care
out = c; $display("@%0dns 4'b001? is selected, opcode
default : begin
$display("@%0dns default is selected, opcode %b,$time,opcode); end
endcase
// Testbench code goes here
always #2 a = $random;
always #2 b = $random;
always #2 c = $random;
initial begin
opcode = 0;
#2 opcode = 3'b101x;
#2 opcode = 4'b0101;
#2 opcode = 0010;
#2 opcode = 4'b0000;
#2 $finish;
end
endmodule
Solution:
module casex_example(out,a,b,c,opcode);
input [30] opcode;
input [10] a,b,c;
output reg [10]out;
always@(opcode)
begin
casex(opcode)
4'b1zzx begin
Don't care 20 bits
out = a;
$display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode); end
4'b01 begin
bit 10 is don't care
out = b;
$display("@%0dns 4'b01 is selected, opcode %b",$time,opcode); end
4'b001 begin
bit 0 is don't care
out = c;
$display("@%0dns 4'b001 is selected, opcode %b",$time,opcode); end
default begin
$display("@%0dns default is selected, opcode %b,$time,opcode); end
endcase
end
endmodule
//Testbench code goes here
module casex_tb;
reg [30]opcode;
reg [10]a,b,c;
wire [10]out;
casex_example c1(.out(out),.a(a),.b(b),.c(c),.opcode(opcode));
always #2 a = $random;
always #2 b = $random;
always #2 c = $random;
initial begin
opcode = 0;
#2 opcode = 3'b101x;
#2 opcode = 4'b0101;
#2 opcode = 0010;
#2 opcode = 4'b0000;
#2 $finish; end
endmodule
//result
@0ns default is selected, opcode 0000

@2ns 4'b001? is selected, opcode 001x
@4ns 4'b01?? is selected, opcode 0101
@6ns 4'b1zzx is selected, opcode 1010
@8ns default is selected, opcode 0000
Session 05 : Verilog Constructs – Part II
1. Write a Verilog program to demonstrate the behaviour of blocking and non-blocking ?

Solution:
module blockingndnon();
reg [2:0]a,b;

initial begin
a=3;b=5;
a=b;
b=a;
$display("@%0dns a=%d b=%d in blocking",$time,a,b);
end
initial begin
a=3;b=5;
a<=b;
b<=a;
$display("@%0dns a=%d b=%d in non blocking",$time,a,b);
#1;
$display("@%0dns a=%d b=%d after end of timeunit",$time,a,b);
end
endmodule
//result
@0ns a=5 b=5 in blocking

@0ns a=3 b=5 in non blocking
@1ns a=5 b=3 after end of timeunit

USER SPACE
2. Write a function to compute temperature conversion from centigrade to Fahrenheit and

call this function in a Verilog task? Compile and Simulate the results.
Solution:
module temp_conv(c,f);
input [7:0]c;
output reg [7:0]f;
function [7:0]c_to_f;
reg [7:0]temp;
input [7:0]c;
begin
temp=c*(1.8); //(c)*9/5;
c_to_f = temp+32;
end
endfunction
task conversion;
input [7:0]c;
output reg [7:0]f;
begin
f={c_to_f(c)};
end
endtask
always @ (c)
begin
conversion(c,f);
$display("@%0dns centigrade c=%0d to fahrenheit f=%0d",$time,c,f);
end
endmodule
//tb
module temp_conv_tb;
// Inputs
reg [7:0] c;
// Outputs
wire [7:0] f;
// Instantiate the Unit Under Test (UUT)

temp_conv uut (
.c(c),
.f(f)
);
initial begin
// Initialize Inputs
c = 0;
#10;
c = 10;

#10; USER SPACE
c = 20;
#20;
$finish;
end
endmodule
//Result
@0ns centigrade c=0 to fahrenheit f=32
3. Generate a 200 MHz clock and simulate and attach the output waveform?
Solution:
module clock_gen();
reg clk;
endmodule
module test;
reg clk;
realtime delay=2.5;
// Outputs

clock_gen uut (
);
initial clk=1'b1;
always #(delay) clk=~clk;
// Wait 100 ns for global reset to finish
initial begin
#100;
$finish;
end
// Add stimulus here
endmodule

4. Write a program to demonstrate the differences between casex and casez?
Solution:
module casexz(next,present);
input [3:0]present;
output reg [3:0]next;
always@(present)
begin
casex(present)
4'bzzx1:begin next=1;
$display("next value is %d",next);
end
4'bxz1x:
begin
next=2;
end
endcase
casez(present)
4'bx1zz:begin
next=3;
end
4'b1xzz:begin
next=4;
end
endcase
end
endmodule
//tb
module tb;
reg [3:0]present;
wire [3:0]next;
casexz x1(next,present);
initial begin
present=4'b01z1;
#10
present=4'bxx10;
#10
present=4'bx100;
#10;
present=4'b1x00;
end
endmodule
//result
next value is 1
next value is 2
next value is 3
next value is 4
5. Write a simple program to demonstrate differences between $display, $strobe, $write,

$monior?
module blockingndnon();

reg [2:0]a,b;
initial begin
a=3;b=5;
a=b;
b=a;
$display("@%0dns a=%d b=%d in blocking with $display",$time,a,b);
end
initial begin
a=3;b=5;
a<=b;
b<=a;
$monitor("@%0dns a=%d b=%d in non blocking with $monitor",$time,a,b);
$write("@%0dns a=%d b=%d in non blocking with $write\n",$time,a,b);
//#1;
$strobe("@%0dns a=%d b=%d after end of timeunit with $strobe",$time,a,b);
end
endmodule
//result
@0ns a=5 b=5 in blocking with $display

@0ns a=3 b=5 in non blocking with $write
@0ns a=5 b=3 in non blocking with $monitor
@0ns a=5 b=3 after end of timeunit with $strobe
6. Write a program for the usage of `include, `define and parameter?
Solution:
`include "mux2_1.v"
`define S $stop;
module tick(y,s1,s0,a,b,c,d); //module mux4_1
parameter delay=10;
input a,b,c,d,s1,s0;
output y;
wire w1,w2;
mux2_1 m0(w1,s1,a,b);
mux2_1 m1(w2,s1,c,d);
mux2_1 m2(y,s0,w1,w2);
endmodule
//test_bench
`define S $stop;
module tick_mux4_1_tb;
// Inputs
reg s1;
reg s0;
reg a;
reg b;
reg c;
reg d;
parameter delay=10;
// Outputs
wire y;

tick uut (
.y(y),

.s1(s1),
.s0(s0),
.a(a),
.b(b),
.c(c),
.d(d)
);
initial begin
s0 = 0;
s1 = 0;
a = 1;
b = 0;
c = 0;
d = 0;
#(delay);
s0=0;s1=1;a=0;b=1;c=0;d=0;
#(delay);
s0=1;s1=0;a=0;b=0;c=1;d=0;
#(delay);
s0=1;s1=1;a=0;b=0;c=0;d=1;
#(delay);
`S
end
// Wait 100 ns for global reset to finish
initial begin
#100;
$finish;
// Add stimulus here
end
initial
$monitor($time,"a=%b,b=%b,c=%b,d=%b,s0=%b,s1=%b,y=%b",a,b,c,d,s0,s1,y);
endmodule
//output
Finished circuit initialization process.
0a=1,b=0,c=0,d=0,s0=0,s1=0,y=1
10a=0,b=1,c=0,d=0,s0=0,s1=1,y=1
20a=0,b=0,c=1,d=0,s0=1,s1=0,y=1
30a=0,b=0,c=0,d=1,s0=1,s1=1,y=1
Stopped at time : 40 ns
//"mux2_1.v"
module mux2_1(y,s,a,b);
input a,b,s;
output y;
assign y=s?b:a;
endmodule

7. Declare a simple 2 dimensional array for implementing 64 locations memory, write a
program to load the memory using $readmemh and write the contents of the memory
back to a file using $writememh?
Solution:
module read_test;
reg [7:0]memory[0:63];
integer i;
initial begin
$readmemh("mem.txt",memory);
//displaying contents before writing
for(i=0;i<64;i=i+1)
$display("memory[%d]=%b",i,memory[i]);
#3;
//writing contents into memory
for(i=0;i<64;i=i+1)
memory[i]=i;
//displaying after writing
for(i=0;i<64;i=i+1)
$display("memory[%d]=%b",i,memory[i]);
end
endmodule
//result
memory[ 62]=xxxxxxxx
memory[ 63]=xxxxxxxx
memory[ 0]=00000000
memory[ 1]=00000001
memory[ 2]=00000010
memory[ 3]=00000011
memory[ 4]=00000100
memory[ 5]=00000101
memory[ 6]=00000110
memory[ 7]=00000111
memory[ 8]=00001000
memory[ 9]=00001001
memory[ 10]=00001010
memory[ 11]=00001011
memory[ 12]=00001100
memory[ 13]=00001101
memory[ 14]=00001110
memory[ 15]=00001111
memory[ 16]=00010000
memory[ 17]=00010001
memory[ 18]=00010010
memory[ 19]=00010011
memory[ 20]=00010100
memory[ 21]=00010101
memory[ 22]=00010110
memory[ 23]=00010111
memory[ 24]=00011000
memory[ 25]=00011001
memory[ 26]=00011010
memory[ 27]=00011011
memory[ 28]=00011100
memory[ 29]=00011101
memory[ 30]=00011110
memory[ 31]=00011111
memory[ 32]=00100000
memory[ 33]=00100001
memory[ 34]=00100010
memory[ 35]=00100011
memory[ 36]=00100100
memory[ 37]=00100101
memory[ 38]=00100110
memory[ 39]=00100111
memory[ 40]=00101000
memory[ 41]=00101001
memory[ 42]=00101010
memory[ 43]=00101011
memory[ 44]=00101100
memory[ 45]=00101101
memory[ 46]=00101110
memory[ 47]=00101111
memory[ 48]=00110000
memory[ 49]=00110001
memory[ 50]=00110010
memory[ 51]=00110011
memory[ 52]=00110100
memory[ 53]=00110101
memory[ 54]=00110110
memory[ 55]=00110111
memory[ 56]=00111000
memory[ 57]=00111001
memory[ 58]=00111010
memory[ 59]=00111011
memory[ 60]=00111100
memory[ 61]=00111101
memory[ 62]=00111110
memory[ 63]=00111111
8. Debug, compile and simulate the following Verilog code?
//Passing more than one parameter
module ram_sp_sr_sw (
input clk , // Clock Input
input address , // Address Input
inout data , // Data bi-directional
input cs , // Chip Select
input we , // Write Enable/Read Enable
input oe // Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// Actual code for RAM Read/Write here
initial begin
$display ("ADDR_WIDTH=%0d, DATA_WIDTH=0d, RAM_DEPTH=%0d",
ADDR_WIDTH, DATA_WIDTH, RAM_DEPTH);
end
endmodule
// Memory Config 2
module ram_controller2 ();//Some ports
ram_sp_sr_sw #(
.DATA_WIDTH(8),
.ADDR_WIDTH(16),
.RAM_DEPTH(1024)) ram(address,data,cs,we,oe);
initial begin
#1; end
endmodule
Solution:
//Passing more than one parameter
module ram_sp_sr_sw (
input clk , // Clock Input
input address , // Address Input
inout data , // Data bi-directional
input cs , // Chip Select
input we , // Write Enable/Read Enable
input oe // Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// Actual code for RAM Read/Write here
initial begin
$display ("ADDR_WIDTH=%0d, DATA_WIDTH=%0d, RAM_DEPTH=%0d",
ADDR_WIDTH, DATA_WIDTH, RAM_DEPTH);a
end
endmodule
// Memory Config 2
module ram_controller2 ();//Some ports
ram_sp_sr_sw #(
.DATA_WIDTH(8),
.ADDR_WIDTH(16),
.RAM_DEPTH(1024)) ram(clk,address,data,cs,we,oe);
initial begin
#1; end
endmodule
//result
ADDR_WIDTH=16, DATA_WIDTH=8, RAM_DEPTH=1024

Session 06: Design and verification of Combinational circuits
1.Design and Verify using Verilog test bench -- 1 to 4 Demultiplexer ?

Solution:
module demux(y1,y2,y3,y4,i,s);
input [3:0]i;
input [1:0]s;
output reg [3:0]y1,y2,y3,y4;
always@(s)
begin
case(s)
2'b00:begin
y1=i;y2=0;y3=0;y4=0;end
2'b01:begin
y1=0;y2=i;y3=0;y4=0;end
2'b10:begin
y1=0;y2=0;y3=i;y4=0;end
2'b11:begin
y1=0;y2=0;y3=0;y4=i;end
endcase
end
endmodule
//tb
module tb;
reg [3:0]i;
reg [1:0]s;
wire [3:0]y1,y2,y3,y4;
demux d1(y1,y2,y3,y4,i,s);
initial
begin
i=15;
s=2'b01;
$strobe("value of y2=%d when selection line is %b",y2,s);
#10
s=2'b11;
#10
s=2'b00;
end
endmodule
//result
value of y2=15
value of y4=15
value of y1=15
2. Design and Verify 8 to 3 Priority Encoder?
Solution:
module encoder(y,i,en);
input [0:7]i;
input en;
output reg [2:0]y;
always@(*)
begin

if(en)
begin
casex(i)
8'b00000001: y=3'b000;
8'b0000001x: y=3'b001;
8'b000001xx: y=3'b010;
8'b00001xxx: y=3'b011;
8'b0001xxxx: y=3'b100;
8'b001xxxxx: y=3'b101;
8'b01xxxxxx: y=3'b110;
8'b1xxxxxxx: y=3'b111;
endcase
end
else
$display($time," make enable as HIGH");
end
endmodule
//testbench
module tb;
reg [0:7]i;reg en;
wire [2:0]y;
encoder e1(y,i,en);
initial
begin
en=1;
i=8'b00000001;
#10
i=8'b00000101;
#10
i=8'b10100000;
#10
i=8'b00100001;
#10 en=0;
i=8'b00000011;
end
initial
$monitor($time," output values are y=%d when input is %b",y,i);
endmodule
//result
0 output values are y=0 when input is 00000001
40 make enable as HIGH
3. Develop a decoder to decode given 16-bit address, equally to 4 memory devices.

generate chip selects for all the four devices? Indicate size of each memory?
Solution:
module memory_64kbx8(
input [15:0]addr, //address bus
inout [7:0]data // data bus
);
reg [7:0]mem1[0:13];
reg [7:0]mem2[0:13];
reg [7:0]mem3[0:13];
reg [7:0]mem4[0:13];

always@(addr)
begin
case({addr[15],addr[14]})
2'b00:begin
$display("@%0dns address is given to memory1",$time);
end
2'b01:begin
end
2'b10:begin
end
2'b11:begin
end
default:begin
$display("@%0dns address is not initialized yet",$time);
end
endcase
end
endmodule
//testbench
module memory_64kbx8_tb;
reg [15:0]addr;
wire [7:0]data;
memory_64kbx8 dut(addr,data);
initial begin
addr=16'h0000;
#2 addr=16'hB001;
#2 addr=16'hA010;
#1 addr=16'h5836;
#2 $finish;
end
endmodule
//result
@0ns address is given to memory1
4. Design 4 bit adder circuit and verify?

Solution:
module rca(cout,sout,a,b,cin);
input [3:0]a,b;
input cin;
output [3:0]sout;
output cout;
//instanciation
fulladder f1(c0,sout[0],a[0],b[0],cin);
fulladder f2(c1,sout[1],a[1],b[1],c0);
fulladder f3(c2,sout[2],a[2],b[2],c1);
fulladder f4(cout,sout[3],a[3],b[3],c2);
endmodule
//fulladder definition
module fulladder(cout,sout,a,b,cin);
input a,b,cin;
output cout,sout;
assign sout=a^b^cin;
assign cout=(a&b)|(cin&(a^b));
endmodule
//testbench
module tb;
reg [3:0]a,b;
reg cin;
wire [3:0]sout;
wire cout;
rca r1(cout,sout,a,b,cin);
initial begin
cin=0;a=4'b0000;b=4'b0011;
#10 a=4'b0011; b=4'b0010;
#10 a=4'b0001; b=4'b0011;
#10 a=4'b1001; b=4'b1011;end
initial
$monitor($time," when inputs are a=%b b=%b ,output cout=%b sum=%b ",a,b,cout,sout);
endmodule
//result
0 when inputs are a=0000 b=0011 ,output cout=0 sum=0011
5. Design BCD to 7 segment display and verify?
Solution:
module bcdconversion(a,b,c,d,e,f,g,in);
input [3:0]in;
output reg a,b,c,d,e,f,g;
always@(*)
begin
if(in>=0 && in<10)
begin
case(in)
4'b0000:begin
a=1;b=1;c=1;d=1;e=1;f=1;g=0;
$display($time," Displaying 0 when input is %b",in);end
4'b0001:begin
a=1;b=1;c=0;d=0;e=0;f=0;g=0;
4'b0010:begin
a=1;b=1;c=0;d=1;e=1;f=0;g=1;
4'b0011:begin
a=1;b=1;c=1;d=1;e=0;f=0;g=1;
4'b0100:begin
a=0;b=1;c=1;d=0;e=0;f=1;g=1;
4'b0101:begin
a=1;b=0;c=1;d=1;e=0;f=1;g=0;
4'b0110:begin
a=1;b=0;c=1;d=1;e=1;f=1;g=1;
4'b0111:begin
a=1;b=1;c=1;d=1;e=0;f=0;g=0;
endcase
end
else

$display("\t \t \t \tenter the correct input between 0 and 9");
end
endmodule
//testbench
module tb;
reg [3:0]in;
wire a,b,c,d,e,f,g;
bcdconversion b2(a,b,c,d,e,f,g,in);
initial
begin
in=4'b0010;
#10 in=4'b0001;
#10 in=4'b0011;
#10 in=4'b0111;
#10 in=4'b0000;
#10 in=4'b0100;
#10 in=4'b0110;
#10 in=4'b0101;
#10 in=4'b1111;
end
endmodule
//result
0 Displaying 2 when input is 0010
enter the correct input between 0 and 9
Session 07: Design and Verification of Sequential circuits
1.Write Verilog codes for latch and a D flip flop and verify?
Solution:
//SR Latch
module srlatch(s,r,en,out);
input s,r,en;
output reg out;
reg temp=0;
always@(*)
begin
if(en==1)begin
casex({s,r})
2'b00:out<=temp;
2'b01:begin
out<=0;
temp<=out;end
2'b10:begin
out<=1;
temp<=out;end
2'b11:
$display("\t it is not valid");
endcase
end
end
endmodule
//tb for sr latch
module tb;
reg s,r,en;
wire out;
srlatch s1(s,r,en,out);
initial
begin
en=1;
s=0;r=0;
#10 s=0;r=1;
#10 s=1;r=0;
//#10 s=1;r=1;
#10 s=1;r=0;
#10 s=0;r=0;
end
initial
$monitor($time, " when s=%b r=%b then output values are %b",s,r,out);
endmodule
//result
0 when s=0 r=0 then output values are 0

//D Latch
module dlatch(d,en,out);
input d,en;
output reg out;
always@(*)
begin
if(en==1)begin
casex(d)
1'b0:
out<=0;
1'b1:
out<=1;
endcase
end
end
endmodule
//tb
module tb;
reg d,en;
wire out;
dlatch d1(d,en,out);
initial
begin
$dumpfile("dump.vcd");
$dumpvars;
en=1;
d=0;
#10 d=1;
#10 d=0;
#10 d=1;
#10 d=0;
end
initial
$monitor($time, " when d=%b then output values are %b",d,out);
endmodule
//result
0 when d=0 then output values are 0
2. Write Verilog code for T flip flop, JK flip flop?

Solution:
JK Flipflop
module jkff(j,k,clk,out);
input j,k,clk;
output reg out;
reg temp=0;
always@(posedge clk or j or k)
begin
case({j,k})
2'b00:out<=temp;
2'b01:begin
out<=0;
temp<=out;end
2'b10:begin
out<=1;
temp<=out;end
2'b11:out<=~temp;
endcase
end
endmodule
//tb
module tb;
reg j,k,clk;
wire out;
jkff j1(j,k,clk,out);
initial
begin
$dumpvars;
clk=0;
j=0;k=0;
#10 j=0;k=1;
#10 j=1;k=0;
#20 j=1;k=1;
#10 j=1;k=0;
#10 j=0;k=0;
#10 j=0;k=1;
#10 j=0;k=0;
end
always
#10 clk=~clk;
initial
$monitor($time, " when j=%b k=%b then output values are %b",j,k,out);
initial
#500 $finish;
endmodule
//result
0 when j=0 k=0 then output values are 0
// T Flipflop
module tff(t,clk,out);
input t,clk;
output reg out;
reg temp=0;
always@(posedge clk or t)
begin
case(t)
1'b0:out<=temp;
1'b1:out<=~temp;
endcase
end
endmodule
//tb
module tb;
reg t,clk;
wire out;
tff t1(t,clk,out);
initial
begin
$dumpvars;
clk=0;
t=0;
#20 t=1;
#10 t=0;
#20 t=1;
#10 t=0;
end
always
#10 clk=~clk;
initial
$monitor($time, " when t=%b then output values are %b",t,out);
initial
#100 $finish;
endmodule
//result
0 when t=0 then output values are 0
3. Develop Verilog code for 4 bit synchronous shift register? use clock frequency of 100 Mhz
in test bench?
Solution:module syn_4bit_shiftreg(clk,reset,d,q,ctrl);
input clk,reset,d;
input [1:0]ctrl;
output reg[3:0]q;
always @(posedge clk, posedge reset)
begin
if(reset)
q<=4'b0000;
else
begin
if(ctrl==2'b00)
begin
q[3]<=d;
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
else if(ctrl==2'b01)
begin
q[0]<=d;
q[1]<=q[0];
q[2]<=q[1];
q[3]<=q[2];
end
else if(ctrl==2'b10)
begin
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
q[3]<=q[0];
end
else
begin
q[0]<=q[3];
q[1]<=q[0];
q[2]<=q[1];
q[3]<=q[2];
end
end
end
endmodule
//tb
module syn_4bitshiftreg_tb;
// Inputs
reg clk;
reg reset;
reg d;
reg [1:0] ctrl;
// Outputs
wire [3:0] q;

syn_4bit_shiftreg uut (
.clk(clk),
.reset(reset),
.d(d),
.q(q),
.ctrl(ctrl)
);
initial
clk = 0;
always #5 clk=~clk; //clock_period=10ns =>clock_frequency=100MHz.
initial begin
reset = 1;
d = 0;
ctrl = 0;
#10;
ctrl=2'b00;
reset=0;
d=1;#10 d=0;#10 d=1;#10 d=0;
#10;
ctrl=2'b01;

d=0;#10 d=1;
#10;
ctrl=2'b10;
#10;
ctrl=2'b11;
end
initial $monitor("@%0dns reset=%b ctrl=%b d=%b output=%b",$time,reset,ctrl,d,q);
initial begin
#100;
$finish;end
endmodule
//output
@0ns reset=1 ctrl=00 d=0 output=0000
Stopped at time : 100 ns
4. Design mod 24 counter and Verify?

Solution:
// mod n counter design
module count_n(clk, rst, out);
input clk,rst;
output reg[4:0] out;
parameter n = 24;
always @(posedge clk or rst)
begin
if(rst)
out <= 'd0;
else if(out < (n-1))
out <= out + 1;
else
out <= 'd0;
end
endmodule
//testbench
module count_n_tb;
reg clk,rst;
wire[4:0] out;
count_n coun_n_inst(clk,rst,out);
initial
begin
$dumpvars;
clk = 1'b0;
rst = 1'b1;
#6 rst = 1'b0;
end
always #5 clk <= ~ clk;
initial
$monitor("output values are %d",out);
initial
#1000 $finish;
endmodule
//result
VCD info: dumpfile dump.vcd opened for output.
output values are 0
output values are 1
output values are 2
output values are 3
output values are 4
output values are 5
output values are 6
output values are 7
output values are 8
output values are 9
output values are 10
output values are 0
output values are 1
output values are 2
output values are 3
output values are 4
output values are 5
output values are 6
output values are 7
output values are 8
output values are 9

output values are 0
output values are 1
output values are 2
Finding VCD file...
5. Develop Verilog code for divide by 4 clock output?

Solution:
module modN_ctr
# (parameter N = 4)
( input clk,
input rstn,
output reg out1,out2);
always @ (posedge clk) begin

if (!rstn) begin
{out1,out2} <= 0;
end else begin
if ({out1,out2} == N-1)
{out1,out2}<= 0;
else
{out1,out2} <= {out1,out2}+ 1;
end
end
endmodule
//tb
module tb;
parameter N = 4;
reg clk;
reg rstn;
wire out1,out2;
modN_ctr u0 ( .clk(clk),
.rstn(rstn),
.out1(out1),.out2(out2));
always #10 clk = ~clk;
initial begin
$dumpvars;
end
initial begin
{clk, rstn} <= 0;
$monitor ("T=%0t rstn=%0b out1=%b out2=%b", $time, rstn, out1,out2);

repeat(2) @ (posedge clk);
rstn <= 1;
repeat(20) @ (posedge clk);

$finish;
end
endmodule
//result
T=0 rstn=0 out1=x out2=x
T=10 rstn=0 out1=0 out2=0

Session 09 : Microprocessors, Timing
1. Calculate the max frequency of the circuit with 2 flip flops connected back to back with a
combinational circuit between flip flops with following timings given.
a. flip flop 1 - delay - 2 ns,
b. combinational circuit delay - 4 ns
c. setup time of flip flop 1 - 2 ns
d. setup time of flip flop 2 - 2 ns
e. flip flop 2 delay - 2 ns
Solution:
2. Write a Verilog code for double synchronizer? and simulate?

Solution:
module double_sync (input clock,
input resetn,
input D1,
output reg Q2);
reg Q1;
always @ (posedge clock or negedge resetn)

begin
if (resetn == 1'b0) begin
Q1 <= 0;

Q2 <= 0; // when reset
end else begin
Q1 <= D1;
Q2 <= Q1; // when clk
end
end
endmodule
//testbench
`timescale 1ns/1ps
module double_sync_tb;
integer count = 0;
reg clk, D1, resetn;
wire q2;
double_sync ds_inst (.clock(clk), .resetn(resetn), .D1(D1), .Q2(Q2));
always #10 clk = ~clk ;
initial begin
$dumpvars;
clk=0;
resetn = 0;
#1;
resetn = 1;
D1 = 0;
for (count = 0 ; count < 10; count = count+1) begin
D1 = count;
#15;
end
$finish;
end
endmodule
Projects :
1. State machine design- Mandatory
2. Dual Port Memory design- Mandatory
3. Serial Adder design- Mandatory
4. FIFO Design and Verification - Mandatory
5. APB Memory design - Optional

1. Design a mealy machine and develop Verilog code for checking the sequence “1011”
overlapping sequence?
Solution:

module fsm(op,ip,clk,rst);
input ip,clk,rst;
output reg op;
reg [1:0]s;
always @(posedge clk)
begin
if(rst)
begin
s<=2'b00;
op<=0;
end
else
begin
case(s)
2'b00:begin
if(ip)
begin s<=2'b01;op<=0;end
else
end
2'b01:begin
if(ip)
else
end
2'b10:begin
if(ip)
begin s<=2'b11;op<=0;$display("\t \t \t \t sequence is detected");end
else
end
2'b11:begin
if(ip)
else
end
default:
begin
s<=2'b00;op<=0; end
endcase
end
end
endmodule
//tb
module tb;
reg ip,clk,rst;
wire op;
reg [0:15]seq;
integer i;
fsm f1(op,ip,clk,rst);
initial begin
rst=1;clk=0;
seq=16'b1011011011011011;
#5 rst=0;
#10 for(i=0;i<16;i=i+1)
begin
#10 ip=seq[i];
end
end
always #5 clk=~clk;
initial
$monitor($time," out is %b when state is %b for input is %b ",op,f1.s,ip);
initial begin

$dumpvars; end
initial
#200 $finish;
endmodule
//result
0 out is x when state is xx for input is x
5 out is 0 when state is 00 for input is x
25 out is 0 when state is 01 for input is 1
sequence is detected

2. Design and Verify 256x8 synchronous Memory as shown below?
Solution:
module dualport(q_a,q_b,data_a,data_b,addr_a,addr_b,we_a,we_b,re_a,re_b,clk_a,clk_b);
input [7:0]data_a,data_b;
input [7:0]addr_a,addr_b;
input we_a,we_b,re_a,re_b,clk_a,clk_b;
output reg [7:0]q_a,q_b;
//memory
reg [7:0]ram[255:0];
always@(posedge clk_a)
begin
if(we_a)//writing into memory
ram[addr_a]<=data_a;
else if(re_a)//reading from memory
q_a<=ram[addr_a];
else
q_a<=0;
end
always@(posedge clk_b)
begin
if(we_b)//writing into memory
ram[addr_b]<=data_b;
else if(re_b)//reading from memory
q_b<=ram[addr_b];
else
q_b<=0;
end
endmodule
//tb
module tb;
reg [7:0]data_a,data_b;
reg [7:0]addr_a,addr_b;
reg we_a,we_b,re_a,re_b,clk_a,clk_b;
wire [7:0]q_a,q_b;
dualport df(q_a,q_b,data_a,data_b,addr_a,addr_b,we_a,we_b,re_a,re_b,clk_a,clk_b);
initial
begin
data_a=15;
data_b=11;
clk_a=0;clk_b=0;
addr_a=8'b11010101; addr_b=8'b00101011;
#10 we_a=1;we_b=1;
#10 we_a=0;we_b=0;
#10 re_a=1;re_b=1;
#60 re_a=0;re_b=0;end
always #10 clk_a=~clk_a;
always #10 clk_b=~clk_b;
initial
$monitor($time," output qa=%b qb=%b",q_a,q_b);
initial
#150 $finish;
initial begin
$dumpvars; end
endmodule
//result
0 output qa=xxxxxxxx qb=xxxxxxxx
30 output qa=00001111 qb=00001011
90 output qa=00000000 qb=00000000

3. Design and Verify a 4 bit serial adder as shown below?
Solution:
module serial_adder_4b(ser_in,shft_cntrl,clk,rst,s);
input ser_in,shft_cntrl,clk,rst;
output wire s;
wire clk_ff,j,k;
reg [3:0]x,y;
reg c;
assign clk_ff=(clk)&(shft_cntrl);
assign s=(x[0])^(y[0])^c;
always@(posedge(clk) or rst)
begin
if(rst)
x<=4'b0000;
else begin
x[3]<=s;
x[2]<=x[3];
x[1]<=x[2];
x[0]<=x[1];
$display("x=%b",x[0]);
end
end
always@(posedge(clk) or rst)
begin
if(rst)
y<=4'b0000;
else begin
y[3]<=ser_in;
y[2]<=y[3];
y[1]<=y[2];
y[0]<=y[1];
$display("y=%b",y[0]);
end
end
always @(posedge(clk_ff) or rst)
begin
if(rst)begin
c<=1'b0;
end
else
begin
case({x[0]&&y[0],(~(x[0]||y[0]))})
2'b00:c<=c;
2'b01:c<=0;
2'b10:c<=1;
2'b11:c<=~c;
default:$display("invalid jk_flipflop input");
endcase
end
end
endmodule
`timescale 1ns/1ps
module serial_adder_4b_tb;
reg ser_in,shft_cntrl,clk,rst;
wire s;
integer i;
serial_adder_4b dut(ser_in,shft_cntrl,clk,rst,s);
always #5 clk=~clk;
initial begin
clk=0;rst=1;shft_cntrl=0;
#15;
shft_cntrl=1;
rst=0;
for(i=0;i<10;i=i+1)
begin
ser_in=$random;
#10;
$display("ser_in=%b,ser_out=%b",ser_in,s);
end
#20 $finish;
end
endmodule
//Result
y=0
x=0
ser_in=0,ser_out=0
x=0
y=0
ser_in=1,ser_out=0
y=0
x=0
ser_in=1,ser_out=0
x=0
y=0
ser_in=1,ser_out=0
y=0
x=0
ser_in=1,ser_out=1
x=0
y=1
ser_in=1,ser_out=1
y=1
x=0
ser_in=1,ser_out=1
x=0
y=1
ser_in=0,ser_out=1
y=1

x=0
ser_in=1,ser_out=0
x=1
y=1
ser_in=1,ser_out=1
y=1
x=1
x=1
y=0
y=1
x=1
4. Design and Verify 16x8 asynchronous FIFO as below?
Solution:
module aFIFO(
input wclk,rclk,reset,
input w_enable,r_enable,
input [7:0]wdata,
output reg [7:0]rdata,
output full_flag,empty_flag);
parameter FIFO_DEPTH=16,POINTER=4;
reg [7:0]fifo[0:FIFO_DEPTH-1];
reg [POINTER:0]wpointer,rpointer,wpointer_sync,rpointer_sync,Qr,Qw;
assign full_flag=(({~wpointer[POINTER],wpointer[POINTER-
1:0]}==rpointer_sync[POINTER:0]))?1:0;
assign empty_flag=(wpointer_sync==rpointer)?1:0;
//write
always@(posedge wclk,posedge reset) begin
if(reset==1)
begin
wpointer<=0;
end
else begin
if(w_enable==1 && full_flag!=1)begin
fifo[wpointer[POINTER-1:0]]<=wdata;
wpointer<=wpointer+1;
end
end
end
//read
always@(posedge rclk,posedge reset) begin
if(reset==1)
begin
rpointer<=0;
end
else begin
if(r_enable==1 && empty_flag!=1)begin
rdata<=fifo[rpointer[POINTER-1:0]];
rpointer<=rpointer+1;
end
end
end
//w_ptr sync for read side
always@(posedge rclk,posedge reset)
begin
if(reset==1) begin
Qw<=0;
wpointer_sync<=0;
end
else begin
Qw<=wpointer; wpointer_sync<=Qw;
end
end
//r_ptr sync for write side
always@(posedge wclk,posedge reset)
begin
if(reset==1) begin
Qr<=0;
rpointer_sync<=0;
end
else begin
Qr<=rpointer; rpointer_sync<=Qr;
end
end
endmodule
//testbench
module aFIFO_tb;
parameter FIFO_DEPTH=16,POINTER=4;
// Inputs
reg wclk;
reg rclk;
reg reset;
reg w_enable;
reg r_enable;
reg [7:0] wdata,data_in;
// Outputs
wire [7:0]rdata;
wire full_flag;
wire empty_flag;
integer count;
aFIFO #(FIFO_DEPTH,POINTER) uut(
.wclk(wclk),
.rclk(rclk),
.reset(reset),
.w_enable(w_enable),
.r_enable(r_enable),
.wdata(wdata),
.rdata(rdata),
.full_flag(full_flag),
.empty_flag(empty_flag)
);
task write_task;

input [7:0]data_in;
begin
@(posedge wclk);
if(!full_flag) begin
w_enable=1;
wdata=data_in;
@(posedge wclk);
w_enable=0;
end
end
endtask
//read task
task read_task;
begin
@(posedge rclk);
if(!empty_flag) begin
r_enable=1;
@(posedge rclk);
r_enable=0;
end
end
endtask
//single_wr_rd_test();
task single_wr_rd_test();begin
//input [7:0]data_in;
data_in=$random;
write_task(data_in);
read_task();
end
endtask
//all_wr_rd_test();
task all_wr_rd_test();
for(count=0;count<FIFO_DEPTH;count=count+1)begin
//input [7:0]data_in;
data_in=$random;
read_task();
end
endtask
//fifo_full_empty_test
task fifo_full_empty_test();begin
// input [7:0]data_in;
for(count=0;count<FIFO_DEPTH+1;count=count+1)begin
data_in=$random;
end
for(count=0;count<FIFO_DEPTH+1;count=count+1)begin
read_task();
end
end
endtask
//wclk clock generation
always
begin
#5;
wclk=~wclk;
end
always
begin

#10;
rclk=~rclk;
end
//reset and calling the tasks
initial
begin
wclk=0;
rclk=0;
reset=1;
#15;
reset=0;
@(posedge wclk);
//single write and read
single_wr_rd_test();
//all write and read
all_wr_rd_test();
//fifo full and empty test
fifo_full_empty_test();
#100;
$finish;
end
endmodule


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Name:Pendem Udaykiran

Assignment No and Title ………………………………………………………………………………………………………….

Session 03 : HDL Modelling and Digital Fundamentals

Q: 1). Convert 2DB7 to decimal and binary number system?

Solution : 2DB7 (In Hex) = (7*16^0)+(B*16^1)+(D*16^2)+(2* 16^3) //(converting to decimal)

= 11703 (In Decimal)

2DB7 (In Hex) = 0010 1101 1011 0111 (In Binary).

2. Perform the following operations using 2’c complement method?

i. 92 = (01011100)2 and 39 = (00100111)2

2’s complement of (39): -39 = + (11011001)2

discard end carry -> 1 00110101

ii. 19 = 00010011 , 2’s complement of (19) : -19 = (11101101)2

Therefore -1+1 = (00000000)2 = 0

Solution : SOP form: f ( A,B,C) =A’B’C’+A’BC’+A’BC +ABC = m0+m2+m3+m7

POS form : f (A,B,C) = M1*M4*M5*M6=(A+B+C’)(A’+B+C)(A’+B+C’)(A’+B’+C)

PRIVATE & CONFIDENTIAL

Session 04 : Verilog Constructs – Part I

PRIVATE & CONFIDENTIAL

reg [3:0] opcode;

reg [1:0] a,b c;

reg [1:0] out;

4'b1zzx : begin // Don't care 2:0 bits

out = a;$display("@%0dns 4'b1zzx is selected, opcode

4'b01?? : begin // bit 1:0 is don't care

out = b; $display("@%0dns 4'b01?? is selected, opcode

4'b001? : begin // bit 0 is don't care

out = c; $display("@%0dns 4'b001? is selected, opcode

$display("@%0dns default is selected, opcode %b,$time,opcode); end

// Testbench code goes here

@0ns default is selected, opcode 0000

Session 05 : Verilog Constructs – Part II

1. Write a Verilog program to demonstrate the behaviour of blocking and non-blocking ?

PRIVATE & CONFIDENTIAL

@0ns a=5 b=5 in blocking

PRIVATE & CONFIDENTIAL

2. Write a function to compute temperature conversion from centigrade to Fahrenheit and

// Instantiate the Unit Under Test (UUT)

PRIVATE & CONFIDENTIAL

// Instantiate the Unit Under Test (UUT)

PRIVATE & CONFIDENTIAL

5. Write a simple program to demonstrate differences between $display, $strobe, $write,

PRIVATE & CONFIDENTIAL

@0ns a=5 b=5 in blocking with $display

// Instantiate the Unit Under Test (UUT)

PRIVATE & CONFIDENTIAL

// Add stimulus here

PRIVATE & CONFIDENTIAL

ADDR_WIDTH=16, DATA_WIDTH=8, RAM_DEPTH=1024

PRIVATE & CONFIDENTIAL

1.Design and Verify using Verilog test bench -- 1 to 4 Demultiplexer ?

PRIVATE & CONFIDENTIAL

3. Develop a decoder to decode given 16-bit address, equally to 4 memory devices.

PRIVATE & CONFIDENTIAL

4. Design 4 bit adder circuit and verify?

PRIVATE & CONFIDENTIAL

0 when s=0 r=0 then output values are 0

2. Write Verilog code for T flip flop, JK flip flop?

// Instantiate the Unit Under Test (UUT)

PRIVATE & CONFIDENTIAL

4. Design mod 24 counter and Verify?

PRIVATE & CONFIDENTIAL

5. Develop Verilog code for divide by 4 clock output?

always @ (posedge clk) begin

Solution : 2DB7 (In Hex) = (716^0)+(B16^1)+(D16^2)+(2 16^3) //(converting to decimal)

POS form : f (A,B,C) = M1M4M5*M6=(A+B+C’)(A’+B+C)(A’+B+C’)(A’+B’+C)