Module 3b - DC BJT (Compatibility Mode) - 4

Chapter 3 – BJT | Module 3b – DC Analysis of BJT
Learning Outcome
Chapter 3 :
At the end of this chapter, students able to:
BIPOLAR JUNCTION TRANSISTORS (BJTs)  Analyze the dc biasing of single stage BJT amplifier circuit.
Module 3b : DC Analysis of BJT  Calculates operating point of DC voltages and DC currents.
 Calculates maximum output voltage, VO(max).
 Plots the DC and AC load line.

Norsabrina Sihab
Faculty of Electrical Engineering,
Universiti Teknologi MARA
Pulau Pinang
Tel : 04-3823355
Email : norsabrina@ppinang.uitm.edu.my
ELE232 - Electronics 1 Updated Nov 2013

Norsabrina Sihab
Chapter 3 – BJT | Module 3b – DC Analysis of BJT Chapter 3 – BJT | Module 3b – DC Analysis of BJT
3 4
Definitions DC biasing circuits (contd)

Proper biasing circuit which it operate in linear region and circuit
Biasing refers to the DC voltages applied to a transistor in order to have centered Q-point or midpoint biased
turn it on so that it can amplify the AC signal. Improper biasing cause
The DC input establishes an operating or quiescent point called the  Distortion in the output signal
Q-point.  Produce limited or clipped at output signal

Vi Vo
In DC analysis all capacitor act as open circuit.
DC Biasing circuits
Linear operation for an inverting amplifier
1. Fixed-bias circuit
2. Emitter-stabilized bias circuit
3. Voltage divider bias circuit
4. Emitter Follower circuit
5. Voltage feedback
Non-linear operation for an inverting amplifier
Norsabrina Sihab Norsabrina Sihab
5 6
1) Fixed-bias circuit - DC analysis

1) Fixed-bias circuit
Input Loop Output Loop
1
2
KVL at loop 1: The collector current is given by:

+VCC – IBRB – VBE = 0 I C  I B  (2)
Solving for the base current: KVL at loop 2 :

V  V BE VCC  I C RC  VCE  0
I B  CC   (1)
RB VCE  VCC  I C RC  (3)
7 8
Load Line for Fixed-bias circuit Circuit Values Affect the Q-Point
From equation (3) :
VCE  VCC  I C RC  (3)

The end points of the load line
are:
VCC
I C sat 
RC VCE  0V
VCE sat  VCC I C 0 A Increasing level of IB

Increasing level of RC
The Q-point is the particular operating point:
where the value of RB sets the value of IB Decreasing
where IB and the load line intersect value of VCC
that sets the values of VCE and IC
9 10
Determine Q-point Example

Determine a) IBQ and ICQ, b) VCEQ, c) VB and VC, d) VBC
Example : Q point at midway between cut-off and saturation
ICsat
ICQ Q-point
VCEQ VCE(Cut-off)

11 12
2) Emitter-Stabilized Bias Circuit – DC Analysis
2) Emitter-Stabilized Bias Circuit
Input Loop Output Loop
Adding a resistor (RE) to improve the stability that is DC bias
current and voltage remain closer to where they set even
temperature change.
1 2
KVL at loop 1 :
KVL at loop 2 :
VCC - I B R B - VBE - I E R E  0
 VCC  I C R C  VCE  I E R E  0
Since IE = (β+1)IB: Since IE  IC:
VCC - I B R B - (   1)I B R E  VBE  0 VCE  VCC – I C (R C  R E ) - -(2)
Solving for IB: Also: VE  I E R E

VCC - VBE VC  VCE  VE  VCC - I C R C
IB   (1)
R B  (   1)R E VB  VCC – I B R B  VBE  VE
13 14
Load Line for Emitter-bias circuit Example

From equation (2) : Determine a) IB, b) IC, c) VCE, d) VC, e) VE, f) VB, g) VBC
VCE  VCC – I C (R C  R E ) - -(2)
The end points of the load line

are:
VCC
I Csat 
RC  RE VCE  0V
VCE  VCC I C 0 A

15 16
3) Voltage Divider Bias 3a) Exact Analysis

Step 1 : Redraw circuit Step 3 : Replace thevenin equiv.
circuit
 This is a very stable
bias circuit.
 The currents and

voltages are almost
independent of
variations in .
Step 2 : Find thevenin equiv. circuit Step 4 : Apply KVL to determine IB
 There are two ways
and VCE
of analyzing the
VTh  VBE
voltage divider bias IB 
circuit :- RTh    1RE
1. Exact analysis VCE  VCC  I C RC  RE 
2. Approximate
analysis R2VCC
RTh  R1 R2 VTh  VR2 
R1  R2
17 18
Example – Exact Analysis 3b) Approximate analysis

Determine VCE and IC Used for circuit that have a very small
IB due to large resistance between
base and ground.
If Ri ≥ R2, IB < I2. So approx. I1  I2
Testing RE ≥ 10R2. If satisfied:

R 2 VCC VE  VB  VBE
VB 
R1  R 2
VE
IE 
RE
Apply KVL at output loop:

VCE  VCC - I C R C - I E R E
IE  IC
VCE  V CC -I C (R C  R E )

19 20
Example – Approx. Analysis 4) DC Bias with Voltage Feedback

Determine VCE and IC
Another way to
improve the stability
of a bias circuit is to
add a feedback path
from collector to
base.
In this bias circuit

the Q-point is only
slightly dependent
on the transistor
beta, .

21 22
4) DC Bias with Voltage Feedback (contd) 4) DC Bias with Voltage Feedback (contd)
KVL at input loop:
VCC – I C RC –I B RB –VBE –I E RE  0
KVL at output loop:
IERE + VCE + ICRC – VCC = 0
Where IB ≤ IC, so approx.:
I C  I C  I B  I C IC  I E Since IC  IC as IB=0 and IC = IB:

IC(RC + RE) + VCE – VCC =0
Knowing IC = IB and IE  IC, the
loop equation becomes:
1 Solving for VCE:
VCC – β–B RC  I B RB  VBE  βI B RE  0
VCE = VCC – IC(RC + RE)
Solving for IB:
VCC  VBE
IB 
RB  β(RC  RE )
23 24
Example MISCELLANEOUS BIAS CONFIGURATION

Determine IB and VC 1) COLLECTOR FEEDBACK
Determine ICQ, VCEQ, VB, VC, VE and VBC
Vcc = +20V
680k CB2
Vo
CB
Vi

25 26
MISCELLANEOUS BIAS CONFIGURATION MISCELLANEOUS BIAS CONFIGURATION

2) Common Collector
Determine VCEQ and IE 3) Common Base
Determine VCB, IB and VCE
CB Co
Vi Vo
E C
EE CC

27 28
Load Line & Maximum Output Voltage, Vo(max) Exercise
DC load line
ICQ, VCEQ --> find in circuit during DC analysis
From KVL at output find:-
 IC(sat) --> when VCE=0V
 VCE(cutoff) --> when IC=0A
Vo(max)DC = 2VCEQ
AC load line
Vce’=VCE(cutoff) – (loss)
Loss = ICQrc --> where rc is bypassed resistor at output during ac analysis.
Vo(max)ac = 2(VCE(cutoff) – loss – VCEQ) = 2(VCE(cutoff) – VCE’)
Maximum peak to peak output voltage, Vo(max)

Vo(max) = Vo(max)DC OR Vo(max)ac  whichever is smaller

Chapter 3 – BJT | Module 3b – DC Analysis of BJT
29
Exercise

Norsabrina Sihab

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Chapter 3 – BJT | Module 3b – DC Analysis of BJT

 Calculates maximum output voltage, VO(max).

 Plots the DC and AC load line.

ELE232 - Electronics 1 Updated Nov 2013

Definitions DC biasing circuits (contd)

Q-point.  Produce limited or clipped at output signal

1) Fixed-bias circuit - DC analysis

KVL at loop 1: The collector current is given by:

Solving for the base current: KVL at loop 2 :

VCE  VCC  I C RC  (3)

VCE sat  VCC I C 0 A Increasing level of IB

Determine Q-point Example

ELE232 - Electronics 1 Updated Nov 2013

VCC - I B R B - (   1)I B R E  VBE  0 VCE  VCC – I C (R C  R E ) - -(2)

Solving for IB: Also: VE  I E R E

Load Line for Emitter-bias circuit Example

The end points of the load line

ELE232 - Electronics 1 Updated Nov 2013

3) Voltage Divider Bias 3a) Exact Analysis

 The currents and

Example – Exact Analysis 3b) Approximate analysis

Testing RE ≥ 10R2. If satisfied:

Apply KVL at output loop:

ELE232 - Electronics 1 Updated Nov 2013

Example – Approx. Analysis 4) DC Bias with Voltage Feedback

In this bias circuit

ELE232 - Electronics 1 Updated Nov 2013

I C  I C  I B  I C IC  I E Since IC  IC as IB=0 and IC = IB:

Example MISCELLANEOUS BIAS CONFIGURATION

ELE232 - Electronics 1 Updated Nov 2013

MISCELLANEOUS BIAS CONFIGURATION MISCELLANEOUS BIAS CONFIGURATION

ELE232 - Electronics 1 Updated Nov 2013

Load Line & Maximum Output Voltage, Vo(max) Exercise

 VCE(cutoff) --> when IC=0A

Maximum peak to peak output voltage, Vo(max)

ELE232 - Electronics 1 Updated Nov 2013

ELE232 - Electronics 1 Updated Nov 2013

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