2014 Annual IEEE India Conference (INDICON)
Harmonic Mitigation in Voltage Source Converters
based HVDC system Using 12-Pulse AC-DC
Converters
Ruchi Agarwal, Student Member, IEEE
Electrical & Instrumentation Engineering Department
Sant Longowal Institute of Engineering & Technology
Longowal, Punjab, India
agarwalruchi01@gmail.com
Abstract—This paper investigates a 12-pulse voltage source
converter (VSC) for harmonics mitigation in high voltage DC
(HVDC) system. The most promising features of the VSC based
system are compact and light weight design, short installation
and commissioning periods, low operation and maintenance cost
and flexibility in control. A current multiplier approach is
proposed in this paper inside the voltage control loop for power
quality (PQ) improvement at AC mains. The proposed system is
designed, modeled and its performance is simulated in
MATLAB-SIMULINK environment. The simulated results are
presented to demonstrate an improved power quality at the AC
mains in term of total harmonic distortion and power factor of
the VSC based HVDC system under various transient conditions
such as variation of load, load unbalancing and voltage sag in
power supply.
Keywords— HVDC; VSC; AC-DC converter; Multipulse;
Power quality;
I. INTRODUCTION
High-voltage direct current (HVDC) transmission is a safe
and efficient technology designed to deliver large amounts of
electricity over long distances. The first commercial projects
launched in this field were the Moscow-Kashira project of
30MW over a distance of 100km in 1951, and the Sweden-
Gotland island project of 20MW, spread over a distance of 98
km
With the increasing expansion of HVDC transmission, A
VSC-HVDC transmission system is a preferred option due to
its operational flexibility, such as provision of voltage support
to AC networks, its ability to operate independent of AC
network strength. This makes it suitable for connection to
weak AC networks such as offshore wind farms, and multi-
terminal HVDC network. Moreover, active power reversal is
achieved without DC link voltage polarity change, and
resiliency to AC side faults (no risk of commutation failure as
with line-commutating HVDC systems) [2-4]
The core component of VSC based system is the power
converter, which serves as the interface between the AC
system and HVDC system. The conversion from AC to DC,
and vice versa, is achieved by controllable electronic switches
978-1-4799-5364-6/14/$31.00 ©2014 IEEE
Sanjeev Singh, Senior Member, IEEE
Electrical & Instrumentation Engineering Department
Sant Longowal Institute of Engineering & Technology
Longowal, Punjab, India
sschauhan.sdl@gmail.com
(such as IGBT) [5].The power quality problems cause in
terms of voltage distortions, poor power factor, high crest
factor etc [6]. Moreover, due to strict requirement of the
power quality at the input AC mains several standards [7, 8]
have been developed and are enforced on the customers. One
of very popular method is use of passive filters but it increases
cost, size, weight, and losses in the system. Moreover, they are
designed for specific harmonic frequencies and become less
effective for a number of harmonics [9, 10]
There are some passive waves shaping solutions which are
based on magnetics. One such passive solution is multipulse
converters which can be used in number of configurations
starting for 12 pulses to large number of pulses e.g. 18, 24, 36,
etc.
The multipulse converter use multi winding transformers,
which result high pulses in DC output, thereby reduction in the
ripple. This AC-DC converter draws a current from AC mains
having a number of steps with its waveform close to a
sinusoidal. The higher number of pulse eliminates need of
separate passive filters.
The operation of the conventional 12-pulse converter
results in the absence of the fifth and seventh harmonics in the
input utility line current. However, the total harmonic
distortions (THD) of input line currents are still high and do
not qualify the standard IEEE 519 [11]. The HVDC system
consist of VSC powered through 12, 24, and 48 pulse, only 36
pulse and above qualify the clean power in two level converter
with this passive wave shaping technique [12]. Moreover,
higher number of pulse result its high cost and complexity of
the system.
Active wave shaping also known as pulse width
modulation is another concept for efficient control of DC
power and PQ improvement at AC mains [13, 14]. This
technique reduces harmonics and consequently improves the
power factor. However, use of hybrid combination of active
and passive wave shaping techniques provides a more
efficient, effective and economic solution for PQ in many
applications [15, 16].
 Amongst many attempts for PQ improvement in HVDC
system, most of the applications are current source converter
(CSC) based HVDC using twelve-pulse controlled converter
topology. However, CSC based topology has high risk of
commutation failure. This paper proposes combination of a
12-pulse converter along with the active wave shaping scheme
for harmonic mitigation in HVDC systems. The 12-pulse
converter configuration is selected amongst a number of
configurations AC-DC converter due to its benefits of lowest
switch count.
II. DESIGN OF 12-PULSE AC-DC CONVERTER FOR PROPOSED
VSC-HVDC SYSTEM
The schematic diagram of 12-pulse converter based HVDC
link is shown in Fig. 1. The design of a 12-pulse converter
consists of the generation of the desired phase shift of 30 (i.e.
360º/number of pulses) between the two sets of three-phase
voltages through multi-winding transformers. It can be
achieved by two configurations namely 0 and 30 phase shift
using star-delta transformer or -15 and +15 phase shift
using star-zigzag transformer as shown in Fig. 1. The star-
zigzag transformer combination is selected in this paper being
a symmetrical system as compared to the star-delta
transformer combination [17].The detailed 12-pulse topology
with star-zigzag configuration is shown in Appendix-2.
Fig. 1. Schematic diagram of HVDC Link
III. PROPOSED CONTROL SCHEME FOR VSC BASED HVDC
SYSTEM
Closed-loop control of output DC voltage of AC-DC
converters is the essential requirement while maintaining high
level of power quality at input AC mains during steady state as
well as transient operation. The proposed control scheme is
shown in Fig. 2.
The close-loop control starts with processing of voltage
error (Ve) obtained after comparison of sensed DC link voltage
(Vdc) with the reference voltage (V*dc), through a proportional-
integral (PI) controller to give modulating control signal (IC).
The signal (IC) is multiplied with a unit template of three-
phase input AC voltage to get AC current reference i*a, i*b, i*C
and compared with AC current (ia, ib, iC) sensed from the
supply to generate current error (Ie). The resultant current error
(Ie) is passed to another PI controller and compared with
triangular carrier signals of fixed frequency (fs) to generate the
PWM pulse for VSC converter. Its duty cycle (D) controls the
DC link voltage at the desired value.
The close-loop control starts with processing of voltage
error (Ve) obtained after comparison of sensed DC link voltage
(Vdc) with the reference voltage (V*dc), through a proportional-
integral (PI) controller to give modulating control signal (IC).
The signal (IC) is multiplied with a unit template of three-
phase input AC voltage to get AC current reference i*a, i*b, i*C
and compared with AC current (ia, ib, iC) sensed from the
supply to generate current error (Ie). The resultant current error
(Ie) is passed to another PI controller and compared with
triangular carrier signals of fixed frequency (fs) to generate the
PWM pulse for VSC converter. Its duty cycle (D) controls the
DC link voltage at the desired value.
Fig. 2. Proposed control scheme for VSC
IV. MODELING OF THE PROPOSED CONTROLLER FOR VSC-
HVDC SYSTEM
The proposed system has VSCs at both side as main
components, which are modeled by mathematical equations
and complete system is represented by a combination of these
model.
A. PI Voltage Controller
The PI voltage controller closely tracks the reference DC
link voltage and gives a control signal (Ic) to minimize the
voltage error Ve(k), which is calculated from the reference DC
link voltage V*e(k) and a sensed DC link voltage Vdc(k) at kth
instant of time as,
* (k) − V (k)
Ve (k) = Vdc (1)
dc
The output of the controller Ic (k) at k th instant is given as,
Ic (k) = Ic (k − 1) + k pv {Ve (k) − Ve (k − 1)} + k iv Ve (k) (2)
where k pv and kiv are the proportional and integral gain of
the voltage controller
B. Reference Current Generator
Three voltage template are derived from the AC terminal
voltages of 3-phase supply,
vsa = Va VL , vsb = Vb VL , vsc = Vc VL (3)
where VL is amplitude of supply voltage and it is computed as,
VL = 2 3(Va2 + Vb2 + Vc2 ) (4)
i*a = Ic × vsa , i*b = Ic × vsb , i*c = Ic × vsc (5)
C. PWM Current Controller
The reference input current are compared with the sensed
phase current (ia,ib,ic) to generate current error (Ie) as given
below ,
ΔΙa = (i*a − ia ) , ΔΙ b = (i*b − i b ) , ΔΙc = (i*c − ic )
The current errors are passed to Proportional-Integral (PI)
controller and compared with triangular carrier signal m (t) of
a fixed frequency (fs) to generate the switching sequence for
the voltage source converter. The switching sequence for
phase “a” is generated based on the logic given as,
if k i ΔΙa ≥ m(t) then S1 = 1 else 0
if k i ΔΙa < m(t) then S4 = 1 else 0
The values “1” and “0” represent “on” and “off”
conditions, respectively. The switching sequences for other
two phases of the system are generated using similar logic.
D. Voltage Source Converter
An equivalent circuit VSC fed HVDC system is shown in
Fig. 1 .The output of VSC to be fed to phase ‘a’ of the HVDC
system is given as ,
Vao = + Vdc 2 for S1 = 1 and S4 = 0
Vao = − Vdc 2 for S4 = 1 and S1 = 0
Vao = 0 for ia = 0 (i.e. S1 = S4 = 0 )
Where Vao, Vbo, Vco are voltage of three phases with
respect to virtual mid-point of the DC link (o). Since the two
switches are never off simultaneously, the output voltage Vao
fluctuates between two values (1/2Vdc and -1/2Vdc).
V. DESIGN OF PROPOSED VSC BASED HVDC SYSTEM
The design of proposed VSC based HVDC system is
carried out for 100MW load with 0.9 lagging power factor
with main consideration on PQ constraints at AC mains and
allowable ripple in DC-link voltage.
The rating of switch used in VSC is calculated as,
Ι L = VA 3VL = P 3(PF)VL , Ipeak = (CF) I L
Crest factor (CF) of the load current is order 2 to 3
Vpeak = 2VL
So, the voltage and current rating of IGBTs is calculated
using equations (12, 13) are 700kV, 1kA respectively.
The voltage (Vdc) of VSC-HVDC system is given as,
Vdc = 2 2Vcon 3m
Where m is modulation index considered as 0.9, Vcon is
converter voltage as line voltage (VL) is step down to 100kV
with transformer. The calculated value of Vdc is estimated
190kV using equation (14).
A capacitor (Cd) is used to minimize the ripples introduced
due to switching frequency of the converter. Its value is
calculated for specified ripple in output voltage (Vdc) given as,
Cd = Id 2ωΔVdc
where Id, ω, ΔVdc are DC link current (P/Vdc), angular
frequency and ripple voltage respectively. From equation (15),
the calculated value of Cd is 200µF
(6)
The interfacing inductor (L) is considered to limit the 5th
harmonic current in each VSC bridge [18] of the order of 20%
of the fundamental current as in conventional line commutated
thyristor based HVDC system
Base impedance, Z base = (kV) 2 MVA
X L = 0.2* Zbase , L = X L 2πf (16)
(7)
(8) The calculated value for L is 0.336H using equation (16)
VI. PERFORMANCE EVALUTION OF PROPOSED SYSTEM
The proposed VSC based HVDC system is modeled in the
MATLAB/Simulink environment, and its performance is
evaluated for 100MW load with lagging power factor. The
detailed data is given in Appendix-1
The performance is evaluated on the basis of various
parameters such as THD in voltage & current, crest factor of
AC mains (CF) and displacement power factor (DPF) and
(9) power factor (PF) at different loading. Fig. 5 and Table-I show
(10) the obtained results of the proposed system.
(11) A. Performance of proposed system during steady state
conditions
Fig. 3 shows the performance of the HVDC system
depicting voltage (Va) and current ia, DC link voltage (Vdc),
load current (IL), active power (P) and reactive power (Q)
drawn from the supply. The performance of controller under
steady-state condition is obtained at rated load, and it is
observed that the reference DC link voltage remains constant
along with sinusoidal voltage and current at input
mains.
(12)
(13)
(14)
Fig. 3. Performance of proposed system under steady state condition
B. Performance of proposed system under transient
conditions
The performance of the proposed system is evaluated
under various transient conditions. It is observed from the
(15) results shown in Figs. 4, 5, 6, 7 and Table-I that DC link
voltage remains constant while restricting power factor near
unity value.
The active load is decremented in PCC1 from 100MW to
60MW at time t=1sec as shown in Fig. 4a. As the results
showed, the supply and load currents drawn from the source
has decreased after load decrement while keeping DC link
voltage constant.
Next transient condition is applied with load increment
shown in Fig. 4b. The system is working at 60MW load
suddenly additional 40MW load at t = 1 sec is added at PCC1,
consequently source and load currents has increased. As the
results showed, the recovery time is less than 5 cycles and
steady state reached again. After the load change, reactive
power required is compensated by the voltage source
converter used in the HVDC system.
(a) Load decrement at PCC1
(b) Load increment at PCC1
The load is varied from 100MW to 60MW at t = 1 sec and
these load is applied again at t = 1.2 sec at PCC2 as shown in
Fig. 4c. It is observed that the PI controller tracks the
reference DC voltage quickly within 5 cycles. The results
reveals that voltage control is fast and smooth in either
condition, i.e., increment or decrement of load, with PF
maintain at near unity value. The AC mains current are
balanced and sinusoidal due to compensation provided by
VSC.
A small 3-phase tapped load of 40MW is connected with
PCC1, suddenly one phase is opened and whole load is shifted
to remaining two phases as shown in Fig. 5. During the
unbalancing conditions, the transmitted DC power is almost
halted since the DC side capacitance is being excessively
charged.
(c) Load variation at PCC2
Fig. 4. Performance of proposed system under load perturbation
Fig. 5. Performance of proposed system under phase open of tapped load at
PCC1
Next, the AC source of PCC2 side is programmed for a
step change of -0.1 p.u on voltage magnitude at t = 1s, for a
duration of 10 cycles. It is observed that the system recovers
within 0.05sec after the AC voltage sag as shown in Fig. 6.
C. PQ performance of HVDC system
The proposed system performance is evaluated under
abovementioned transient conditions. The harmonic spectra of
corresponding voltage and current are shown in Figs. 8, 9, &
10. The THD at AC mains demonstrating less than 5% in
current distortion shows the conformity of International
Standard IEEE-519.
 The system performances is also tested under varying load
conditions at PCC and number of power quality indices are
obtained in term of THDi, THDv, CF, DPF, PF as shown in
Table-I. Fig. 7 depicts reduced distortion of current at rated
load with near unity PF at the AC mains.

(c) Load variation at PCC2

Fig. 8. Voltage and current waveform of AC mains and its harmonic spectra

Fig. 9. Voltage and current waveform of AC mains and its harmonic spectra
at PCC1 disturbance
Fig. 6. Performance of proposed system under voltage sag condition at PCC2

TABLE I. VARIOUS POWER QUALITY INDICES

Load(%) PF DPF CF THDv(%) THDi(%) ia
60 0.9992 0.998 1.41 3.55 3.56 263.4
70 0.9991 0.9997 1.41 3.64 3.42 286.8
80 0.9928 0.9931 1.41 2.9 2.62 309.8
90 0.9933 0.9996 1.41 2.82 2.57 333.9
100 0.994 0.9943 1.41 2.71 2.52 355.8
Fig. 10. Voltage and current waveform of AC mains and its harmonic spectra
due to voltage sag at PCC2 side

VII. CONCLUSION
The performance simulation of 12-pulse converter
topology based VSC system has been presented for power
quality improvement in HVDC system. The presented results
demonstrate near unity PF under various transient. Moreover,
(a) Variation of PF (b) Variation of ia and THDi
PQ indices of the proposed system are in conformity to
Fig. 7. PQ indices of proposed system under load variation International Standard IEEE-519. Based on the performance
evaluation of the proposed system, it is concluded that, the 12-
pulse based VSC–HVDC system is a cost effective solution as
well as a good option for power quality improvement.

(a) Load decrement at PCC1
(b) Load increment at PCC1
APPENDIX-1
Rated active power: 100MW with 0.9 lagging PF, line
voltage (VL): 230kV with 50 Hz supply frequency, interfacing
AC inductor (L): 0.336H, DC link voltage (Vdc): 190kV, DC
link capacitor (Cd): 200µF, transformer: 230/100kV with 20%
leakage reactance, switching frequency (fs): 1950Hz, DC
voltage controller proportional gain: 6, integral gain: 160,
current controller proportional gain: 9, integral gain: 80.
APPENDIX-2
The turn’s ratio for Y/Z1 and Y/Z2 transformers to provide
+15◦ and -15◦ phase shift is given by N3/(N2+N3) and
N1/(N2+N3) and, where N1 is number of turns per phase in star
winding and N2, N3are number of turns of zigzag windings
shown in Figs. 11, 12.
 From the triangle ijk in phasor diagram shown in Fig. 11, N3 ( N 2 + N3 ) = sin(30° − δ ) sin(30° + δ ) (24)
the voltage relation for Y/Z1 transformer is written as
Similarly, the second relation can be derived as
Vq s in(30° − δ) = Vby sin(30° + δ) , where δ = 15° (17) N1 ( N 2 + N3 ) = VAB {2Vab sin(30° + δ )} (25)
Vq Vax = N3 ( N 2 + N3 ) (18) Therefore, the system turn ratio N1/(N2+N3) and N3/(N2
For balanced system, Vax = Vby, then the relation between +N3) for Y/Z1 and Y/Z2 transformer are calculated as 1.626
secondary windings and 0.336 for given line voltage across three-phase star
connected primary winding and three-phase zigzag connected
N3 ( N 2 + N3 ) = sin(30° − δ) sin(30° + δ) (19) secondary winding terminals.
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