ESD Merged RL All 803pg

M1 – Introduction to Embedded Systems
§ Dedicated computer/processor based system built for

application/product
§ System within a system
Embedded System Design - RL1.1.1 © K.R.Anupama & Meetha.V.Shenoy 2

§ An embedded system is a special-purpose system -
the computer is completely encapsulated by the
device it controls
§ Unlike a general-purpose computer- an embedded
system performs one or a few pre-defined tasks-
usually with very specific requirements
§ Since the system is dedicated to specific tasks-
design engineers can optimize it, reducing the size
and cost of the product

§ What are we designing ?
§ What is the behavior ?
§ What are the inputs?
§ What are the outputs?
§ What are the constraints ?

§ Single functioned
§ Complex Algorithms
§ User Interface
§ Tightly Constrained –Power, Cost, Memory
§ Reactive and Real-Time
§ Multi-rate

§ Response
§ Throughput
§ Reliability – MTBF,MTTR
§ Maintainability
§ ISP & IAP
§ Testability & Debug-ability

§ Evolvability
§ Portability
§ Time-to-prototype and Market

M1 – Introduction to Embedded Systems
Requirement Analysis
Specifications
System Architecture
Hardware Design Software Design
Hardware Implementation Software Implementation
Hardware Testing Software Testing
System Integration
System Validation
Operation & Maintenance

§ Ensuring Sound Specifications
§ Formulating arch for system
§ Partitioning H/W & S/W
§ Iterative approach in H/W - S/W design

§ Based on Complexity

§ Small-Scale Embedded System
§ Single 8/16 bit Microcontroller
§ Less complex hardware and software
§ Board level design
§ Battery-operated

§ Medium-Scale Embedded System
§ 16/32 bit Microcontroller/RISC,DSP/ASSP/IP
§ May involve use of RTOS
§ Distributed System – bus/networks
§ Encryption/ Decryption/DCT
§ Real-Time Scheduling Algorithms

§ Sophisticated Embedded System
§ Multi-processor system
§ Safety Critical applications
§ H/w S/w Co-design
§ RTOS

FPGA/ASIC Memory
Sensors ADC CPU DAC Actuators
Diagnostic Human I/f

Port
Software
M1: Introduction to Embedded Systems
FPGA/ASIC Memory

Port
Software
§ Processors
§ Timers
§ SCI
§ Interrupt Controller
§ Parallel Ports
§ Memory
§ Data
§ Program
§ Power supply
§ Reset- Oscillator circuits
§ Application Specific Circuits

§ Software
§ Application Specific Software – series of tasks
§ Constraints- available memory, available processing power, power
dissipation limit
§ RTOS
§ Supervise application s/w
§ Allocate resources
§ Context switching
§ Latencies – meet the deadlines
§ Scalable

GPP
Performance
/ Power DSP, ASIPs Flexibility
Efficiency
FPGA
ASIC

§ General Purpose Processor- µp
§ Stream 1 – 68HCxx – Motorola
§ Stream 2 – 80x86 – Intel
§ Stream 3 – SPARC – Sun
§ Stream 4 – Power PC – IBM
§ Stream 5 - ARM

Goal: Multiply data in mem A with B- put it
back in A A
CISC: Mem
B
MUL A,B
C
RISC:
LDA R0,A
R0 R1
LDA R1,B
R2 R3
MUL R0,R1
STR A,R0
x,÷,+,-

Time = Time x cycles x Instructions
Program cycle Inst Program
RISC CISC

§ Instruction:
§ Fetch
§ Decode
§ Execute
1. ADD R2,R1,R3
2. SBR R2,R3,R2
3. STR R2,b

IF1 ID1 IE1 IF2 ID2 IE2 IF3 ID3 IE3
9 cycles
IF1 ID1 IE1
IF2 ID2 IE2
IF3 ID3 IE3
5 cycles
Pipeline Hazards
§ µc
§ Processor has limited capability
§ Enhanced i/o Functions
§ Appln Specific units [DTMF/MODEM]
§ Stream 1 – 68HC11xx, HC12xx, HC16xx
§ Stream 2 - 8051
§ Stream 3 – PIC16F84 – Microchip
§ Stream 4 – ARM based Microcontrollers

§ CISC or RISC ?
§ µp or µc ?
§ µc
§ used when program is small/ less complex instructions
§ located in internal memory
§ µp
§ used when program is large/ large no. of computations have to be
carried out
§ RISC – used when intensive computations have to be done

§ For a GPP to Qualify as an Embedded Processor
§ Architecture must be optimized for RT op
§ Support atomic operations
§ Used for complex real –time functions

§ RISC CPU + CISC special unit
§ I960 – CPU+ Interrupt +DMA

Read value
Inc value
Write value

Read value
Suspend
Task1
Inc value
Read value
Inc value
Restore
Task1
Write value
Write value

§ An operation during which a processor can simultaneously read a
location & write it in the same bus operation
§ This prevents any other processor or I/O device from writing or
reading memory until the operation is complete
§ Atomic implies indivisibility & irreducibility
§ An atomic operation must be performed entirely or not performed

at all

§ µp core + MAC
§ Provides fast discrete –time signal processing streams
§ Stream 1 - TMS 64xx – Texas
§ Stream 2 – SHARC – AD
§ Stream 3 – 5600xx – Motorola

§ Specific tasks such as MPEG coding
§ I2 chip – TCP/UDP – IP, ARP, Ethernet,10/100
§ Faster than s/w solution using GPP

§ RTOS-less solution
§ IIM 700 - serial –to – Ethernet converter
§ ASSP is used as an additional processing unit – instead of

embedded s/w - AES

§ Speech signal compressing & coding
§ Communication unit
§ Keyboard display i/f
§ Image Processing
§ Multiple processors are used when a single processor cannot

meet the needs of different tasks

§ Instruction Set
§ Max- bits in operand (Size of the processor) – 8/16/32
§ Clock frequency in MHz
§ Processing speed in MIPS

§ Dhrystone – uses a bench mark program
§ 1 MIPS = 1757 Dhrystones – VAX 11/780

FPGA/ASIC Memory

Port
Software
§ RAM
§ Internal/External
§ Flash Memory/EEPROM
§ External/Internal
§ System Ports
§ ROM/PROM
§ Cache

Address
Memory
CPU Data
Inst/Data
Control

IADDR
IDATA Inst
Memory
ICONTROL
CPU
DADDR
DDATA Data
Memory
DCONTROL

Memory
RAM Hybrid ROM
EEPROM NVRAM Flash
SRAM DRAM EPROM PROM

§ ROM
§ EEPROM
DRAM with
§ SRAM Address
clock
Page
§ DRAM – FPM
Location
§ SDRAM 64 k
64 pages
§ SIMMs 1K
§ DIMMs 0 002
§ SODIMMs
§ PCMIA

§ Programs larger than memory
§ Multiple processes in memory
§ Multiple programs in memory
§ Swapping
§ Overlays
§ Program – segment – main & overlay

Memory mapped I/O
Instructions
RAM
NVRAM
Stack
System

§ Stuck at ‘0’
§ Stuck at ‘1’
§ Bridge
§ Signature Analysis - ROM

Extreme Fast Memory
Internal/External to CPU
CPU uses cache memory to store instructions that are repeatedly required to run
programs- working set
Sequential locality of reference – spatial & temporal
Cache
Cntlr
Cache hit/miss
L2 Cache
L1 Cache
CPU

tmain 0.1µs
tL1 10 ns
§ tmain – access time for main memory tL2 25 ns
§ tL1 – access time for primary cache h1 90%
h2 7%
§ h1 – hit ratio of primary cache
tav =
§ tL2 – access time for primary cache 0.9x 10ns
§ h2 – hit ratio of secondary cache but not primary +0.07x25ns
+(1-0.9-0.07) x 0.1µs
§ If system has only L1 cache
tav = 13.75 ns
§ tav ?
§ If system has L1 and L2 cache
§ tav?
§ tav = h1tL1 + (1-h1)tmain
§ tav = h1tL1 + h2tL2 + (1-h1 -h2)tmain

Extreme Fast Memory
Internal/External to CPU
CPU uses cache memory to store instructions that are repeatedly required to run
programs- working set
Sequential locality of reference – spatial & temporal
Cache
Cntlr
Cache hit/miss
L2 Cache
L1 Cache
CPU

§ Compulsory Miss/Cold Miss
§ Capacity Miss
§ Conflict Miss

§ Direct Mapped
§ Set Associative

MDR
Cache
MAR

MAIN
Page 0 Block 0 4 bytes
4k
Block1
4k
Block N Block 0 TAG
Block1
Block 0
Block1 Block N
Page 1
Block N
CACHE
Block 0
Page 2 No. of Blocks = 1K
Block1
Block N

Valid Tag Data
cache block 1
cache block 2
cache block 3
cache block 4
cache block 5
Address
Tag Index Offset
Dirty Bit Value

Hit
Write Through
Write Back

001 Address Data
100 000 0101
010 001 1111
101 010 0110
011 0000
100 1000
101 0001
110 1010
111 0100
00 -
1 1000
-
01 -
0
1 0001
1111
-
10 -
0 0110
-
11 - -
Block Tag Data

Address Data
001
000 0101
100
001 1111
010
010 0000
101
011 0110
100 1000
101 0001
110 1010
111 0100
0 -
10 -
1000 -01 -0000
1 -
00 -
0101 -10 -0001
Block S0 Tag S0 Data S1Tag S1Data
Set Associative Cache

§ Cache
§ 64K x 32
§ 128 - 0.5 K blocks
§ Two sets
§ Main Memory
§ 256 K x 32
§ 512 Blocks - m
§ 64 Groups –n
§ Group No m mod n

Block Group
0 64 128 384 448 0
1 65 129 385 449 1
2 66 130 386 450 2
63 127 192 447 511 63
0 1 2 3 4 5 6 7

Block
Tag
bank 1 bank 2 bank n
bank select
data

§ Unified Cache
§ Instruction/Data Cache
§ Strong ARM – 16 KB, 32 way cache – each block is 32 bytes
§ C5510 – 16KB instruction cache – 2 way

§ Specific operation range
§ Range of voltages
§ 5.0 ± 0.25 V
§ 3.3 ± 0.3
§ 2.0 ± 0.2
§ 1.5 ± 0.2 V
§ Additionally EEPROM/ RS232 C – 12 V
§ Usual pattern of Power Distribution

§ 2 pins of VDD + VSS
§ Distributes power to all sections and reduces interference

§ Ext I/O
§ Timers
§ Clock + Reset
§ ADC
§ VDD VSS AGnd, AREF, AIP
§ Some Devices use charge pumps – no external power supply

§ Propagation delay in gates α 1/V
§ Power consumed in a CMOS circuit α V2
§ An ES has to perform tasks continuously
§ Power saving important
§ Wait State/ Stop state
§ 2.5 mW /100 KHz

§ Offers three low power modes of operation
§ Run
§ Normal Consumes Max Power
§ Idle
§ Saves power by stopping the CPU clock
§ Sleep
§ Turns off all units except – Power -0
§ Keeps Power unit thro’ I/O power supply line
§ Low speed clock available for power manager

400 mW
Run
10 µs 90 µs
10 µs
160ms
Idle Sleep
90 µs
50 mW 0.16 mW

§ Clock source
§ Crystal – highest stability – inspite of temp drifts
§ Internal Ceramic Resonator – reasonable stability
§ External IC based Oscillator – more driving power required

§ Activated only for a few clock cycles
§ System reset – CPU in synch with the reset of rest of the devices
§ Sources of reset
§ Power on reset
§ Reset
§ RC
§ IC
§ S/w Instruction /COP/CM

temp
40
Sense
10ms
t
Control

§ RTC/Timers/Counters
§ At least one counter in every ES

§ Most Embedded Systems are Real-Time
§ No. of Interrupts
§ h/w
§ event driven
§ Priority
§ Latency
§ Default Priorities
§ COP Watchdog
§ External Interrupts
§ Timer
§ Serial I/f
§ ADC

§ ADC – multi-channel
§ Vref + , Vref-
§ DAC- PWM

§ Parallel
§ Serial
§ Synchronous
§ Asynchronous

§ Synchronous
§ SPI,USB
§ Clock sent explicitly by Master – Slave
§ Clock Signal
§ Data modulated with Clock
§ Synch Pulse
§ Asynchronous
§ Peer- to- Peer
§ Clock Implicit

§ Encoders
§ Decoders
§ Multiplexers
§ PAL
§ GAL
§ PLDs, CPLD,
§ FPGA
§ Drivers

FPGA/ASIC Memory

Port
Software
FPGA/ASIC Memory

Port
Software
Appln Layer
RTOS
Hardware

§ S/w particular to an application
§ Processor of ES- handles inst/data
§ Final stage ROM Image

§ Boot-up program
§ Stack/addr pointers
§ Appln tasks
§ ISR
§ RTOS
§ i/p data
§ Vector address

§ Configuring devices
§ Device drivers for specific processors
§ Small –Scale ES

Assembler
Machine code
ALP [any loc]
.obj
Bytes for Machine code
Library [MC] linked program [any loc]
Re-locating .exe
Linker
Addr [loader] Locater
Data Bytes Programmer
µc
.s19/hex

§ Device Types
§ Physical e.g. Keyboard/Display
§ Virtual e.g. File/ Pipe
§ Each device has three components

§ Control Registers
§ Status Register H/w of
§ Device Mechanism Device
§ (I/p Buffer, O/p Buffer)

§ s/w for controlling/ receiving/ sending data
§ Made up of 3 functions
§ Initializing Device
§ Calling the ISR
§ Resetting status bits after ISR
§ If Underlying h/w as hidden as possible OS Functions

§ API- then defines the h/w
§ Device usable – when h/w in the system is changed

§ Codes for detecting the presence of devices initializing and
testing
§ Allocates address and checks for collision
§ Address Allocation can be – pre-defined, relocatable

§ Each Task has a distinct memory location
§ Tasks – made up of one or more procedure
§ Scheduling by OS - takes care of constraints

§ RTOS kernel important func - schedule transitions of task
§ Ready state - Running State
§ Block state - Running State

§ Tasks can enter into ready state at any time
§ At a time only one task will be in running state
§ Scheduling Algo
§ RMS
§ EDF
§ LLF
§ RTOS also controls inter-process communication

§ How much h/w is required?
§ How do we meet deadlines?
§ How do we minimize power consumption?

§ How do we design for upgradeability ?
§ Does it work?
§ Complex Testing
§ Limited observability and controllability
§ Restricted Development Environment

§ Design method - Optimize performance
§ Tools for ESD
§ Split-up design work

§ Process has to optimise
§ Manufacturing cost
§ Performance
§ Power Consumption
§ User I/f

Requirements Every step
Analyze
Top Down Refine

Specifications
Approach Verify
Architecture
Components
Sys Integration

§ Generally final step in Embedded System Design
Embedded System Design - RL1.3.1 © K.R.Anupama &

5
Meetha.V.Shenoy
§ Embedding an GPP
§ ARM7,ARM9 + Special Circuits

§ Large no. of programmable gates
§ Set of gates - Macro Cell
§ Each cell - several i/p / several o/p

§ All cells inter connect - Arrays
§ Algo FT, IFT, LT, ILT, encryption/ decryption, DCT

RAM ROM EEPROM
ASIP
Timer/Int I/o I/f
FSK Mod
Charge Pump Antenna

M2: Small Scale Embedded System Design Example
DESIGN PROCESS
Analyze
Top Down Refine

Specifications
Approach Verify
Architecture
Components
Sys Integration
EMBEDDED SYSTEM DESIGN – RL2.1.1 © K.R.ANUPAMA & MEETHA.V.SHENOY

2
MICROWAVE OVEN
8051RE2
EMBEDDED SYSTEM DESIGN – RL2.1.1 © K.R.ANUPAMA & MEETHA.V.SHENOY 3

MICROWAVE OVEN – USER REQUIREMENTS
Simple Microwave Oven

No Grill

USER REQUIREMENTS – OVEN OPERATION
Start/ Quick Start

Stop
Power Control
Time
Weight
Auto Cook Features

USER REQUIREMENTS – FRONT PANEL
Display Time / User Options
Oven Lock
Buttons
Weight
Power Level
Time
10 Min
1 Min
10 Sec
Auto Cook
Chilled
Beverage
Frozen
Start/Quick Start
Stop
USER REQUIREMENTS – INSIDE OVEN
Rotating Plate
Microwave Vents
Weight Sensor

SPECIFICATIONS – HOW DOES COOKING
IN MICROWAVE HAPPEN ??
Heats food - bombarding it with electromagnetic radiation in the
microwave spectrum
Causes polarized molecules in the food to rotate and build up thermal
energy in a process known as dielectric heating

SPECIFICATIONS – ORDER OF USER
INPUT
Any Auto Cook
Weight
Power Level
Time

SPECIFICATIONS –SETTING AUTO COOK
User can press any auto cook option
Beverage – Auto Cook Time 1.07 - 20 % Power Level
Frozen – Auto Cook Time 11.50 – 40 % Power Level
Chilled – Auto Cook Time 5.15 – 40% Power Level
Weight will always be auto weight

SPECIFICATIONS – SETTING WEIGHT
• Each press of button 100g button adds 100g in weight – maximum
weight cannot exceed 1.2 Kg
• Or Auto Weight button can be used – This option detects weight to
accuracy of 100g
• Default - Auto weight

SPECIFICATIONS – SETTING POWER LEVEL
User can cook at 5 different Power levels: 100%, 80%, 60%, 40 %
20%
Every press of the Power Button decrements the power level by 20 %
1 Press - 100%; 2 Presses – 80% ; 3 Presses – 60%; 4 Presses – 40
% ; 5 Presses – 20%
6 Presses – Brings the power level back to 100 %
The Default power level is 100%

SPECIFICATIONS – SETTING TIME
Time is set as multiples of 10 Mins, 1Min, 10 Secs. For e.g. if the
cooking time is 12 Minutes and 40 secs- the 10 Minutes button has to
be pressed once, 1 Minute Button has to be pressed Twice and 10
seconds button has to be pressed four times

SPECIFICATIONS - DISPLAY
When user is setting power level or Time, the value being pressed
should be displayed, and when user presses the Start button, the
cooking process begins and the time left for cooking to complete is
displayed.

SPECIFICATIONS- LOCK & STOP
Once the cooking begins the door gets locked and
should open only when cooking process is terminated.
Internal Illumination is provided as long as door is closed
User can terminate cooking anytime by pressing the
STOP button
When Stop button is pressed once cooking is aborted,
timer is stopped, not cleared; cooking can be resumed
by pressing Start
When stop is pressed twice, cooking is aborted and
timer is also cleared
When cooking time elapses, a buzzer is sounded;
pressing the Stop Button stops the buzzer

SPECIFICATIONS – QUICK START
A Quick Start mode is available where timer or power need not be
set - just Start button needs to be pressed, the default power value
and auto weight is taken and time is set as 30 secs, for ever press of
the start button time is incremented by 30 seconds

SPECIFICATIONS- COOKING
Microwave Cooking Apparatus Consists of:
A high voltage power source- commonly a simple transformer - which
passes energy to the magnetron
A cavity magnetron- which converts high-voltage electric energy to
microwave radiation
A waveguide (to control the direction of the microwaves)

SPECIFICATIONS COOKING POWER
LEVELS
Transformer – Linear – Complete ON/OFF Switching
Power Level is varied by controlling the amount of time for which the
Magnetron is turned on.
Time of cooking is broken up into 10 sec slots, if power is 60% then
for 6 secs the microwave is on and rest of the 4 secs the microwave is
off

SPECIFICATIONS – MICROWAVE TURN
TABLE
The turntable in a microwave oven is driven by an AC single phase
synchronous motor which may start in either direction at random and
continues to travel in that direction until stopping.
The reason for using a turntable in a microwave oven is that the
microwave energy is not evenly distributed across the oven. The
turntable allows the food to receive an equal amount of energy by
turning across the uneven microwave field. The microwave energy is
turned to heat within the food.
It actually does not matter in which direction the turntable rotates in
order to evenly cook the food.
Standard Driver available to which a PWM of 16 KHz and 50 %
duty cycle is to be provided

DESIGN PROCESS
Analyze
Top Down Refine

Specifications
Approach Verify
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2

MICROWAVE OVEN

No Grill

MODULAR DEVELOPMENT
Module 1: User Interface – Key & Display
Module 2: Timer – Start, Stop, Restart, Halt
Module 3: Oven Functions – Magnetron, Turn Table , with Weight
Sensor
Module4: Door Lock Control

MODULE 1
Keys
Auto cook -3 keys
Weight/ Auto Weight
Power Level
Timer
10 Min
1 Min
10 sec
Display – 6 ; 7 –segment displays – Numeric Characters

MODULE 3
Magnetron Control – ON & OFF according to power level
Turn Table Control
Weight Sensor ON/OFF

MODULE 4
Relay Mechanism – Lock & Unlock Door – Electromagnetic Relay

ARCHITECTURE
User Key Magnetron –
Timer ON & OFF
& Display
Turn Table
Open/Close
Door

Timer CPU
Magnetron Control
Memory
Turn Table Control

Panel I/O
Door Control
Hardware Architecture

DESIGN PROCESS
Requirements
Specifications Top Down

Approach
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2 – Module1

MICROWAVE OVEN

No Grill

MODULAR DEVELOPMENT
Module 1: User Interface – Key & Display
Module 2: Timer – Start, Stop, Restart, Halt
Module 3: Oven Functions – Magnetron, Turn Table , with Weight
Sensor
Module4: Door Lock Control

MODULE 1
Keys Ports
Start/Stop INT0/INT1
Auto cook -3 keys P1.0- P1.2
Weight -2 P1.3 – P1.4
Power Level P1.5
Timer P1.6
10 Min
P2.0- 2.2
1 Min
10 sec

KEYBOARD INTERFACE
P1.0
P1.1
P1.2
P1.3
P1.4
KBD
P1.5
IE1
P1.6
P1.7

KEYBOARD INTERFACE
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KLS7 KLS6 KLS5 KLS4 KLS3 KLS2 KLS1 KLS0

VCC
R
10
S1 A
MODULE 1 - DISPLAY
LT a
RBO
RBI
5V h
A
B
C Vcc Port4, Port 5, Port 2.4-2.7, Port 3.4,3.5
D
GND
7447

MICROWAVE OVEN
8051RE2 – Module 4

MODULE 4 - RELAY
Solid state relay – RS 275-310

Turning ON/OFF Lock
P3.6

DESIGN PROCESS
Requirements

Approach
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2 – Module3

MICROWAVE OVEN -INTERNALS
Rotating Plate
Microwave Vents
Weight Sensor

MODULE 3
Turn Table
!6 KHz – 50 % duty cycle

255-125+1
24MHz
THX
4 MHz
CCLK
6
32 KHz
TLX
3.125x10-5
TX
Enable TFX
(TCON)
TMOD
INTX
Gate
TRx (TCON)
TIMER0
TMOD
C/T Gate M1 M0 C/T Gate M1 M0
TCON
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

MODULE -
MAGNETRON
Solid state relay – RS 275-310
Turning ON/OFF Lock
P2.4

MODULE – WEIGHT SENSOR
Load Cell 0 -2Kg
Analog Output – Obtained via a Wheatstone Bridge
Output is calibrated to vary every 20mv for 100g
Connected to a serial RS232C - ADC

RS232 ADC
9600 - 115200 Baud

default 115200 Baud

RS232C
FE/SM0 SM1 SM2 REN TB8 RB8 T1 R1
BRR TBCK RBCK SPD SRC
BRL – 24 MHz - 243

DESIGN PROCESS
Requirements

Approach
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2 – Module2

(65536- RCAPH:L)
4MHz
R2CAPH:L = 20,000
2 MHz 45536 = b1e0H
FCLK
÷2
Counter 100 Hz
TX
Enable
T2CON
T2CON
T2CON

TIMER2
T2CON
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL’
T2MOD
T2OE DCEN

DESIGN PROCESS
Requirements

Approach
Architecture
Components
Sys Integration

2
MICROWAVE OVEN
8051RE2 – System Integration

4.0 0.0
4.3 0.7
4.4 1.0 BV
4.7 1.1 CH
5.0 1.2 FR
5.7 1.3 WT
1.4 AW
1.5 PL
3.7
1.6 T
Lock 3.6
1.7 TT
3.5
2.0 10M
3.4
2.1 1M
Start 3.3
2.2 10S
Stop 3.2
2.3
TXD 3.1 MAG
2.4
Load Cell RXD 3.0
2.7
X1
24M
X2
supply 8051RE2
INTERRUPTS
§ INT0,INT1 § INT0, INT1
§ KBE § Timer2
§ TIMER0 § Timer0
§ TIMER2 § KBE
§ SCI § SCI

INTERRUPTS
IE0
EA EC ET2 ES ET1 EX1 ET0 EX0
IE1
SCI2 SPI TWI KBD

INTERRUPTS
IPL0
IPH0

INTERRUPTS
IPL1
SCI2 SPI TWI KBD
IPL2
SCI2 SPI TWI KBD

INTERRUPTS
§ INT0, INT1
§ Timer2
§ Timer0
§ KBE
§ SCI

DESIGN PROCESS
MICROWAVE OVEN
8051RE2 – Software

4.0 0.0
4.3 0.7
4.4 1.0 BV
4.7 1.1 CH
5.0 1.2 FR
5.7 1.3 WT
1.4 AW
1.5 PL
3.7
1.6 T
Lock 3.6
1.7 TT
3.5
2.0 10M
3.4
2.1 1M
Start 3.3
2.2 10S
Stop 3.2
2.3
TXD 3.1 MAG
2.4
Load Cell RXD 3.0
2.7
X1
24M
X2
supply 8051RE2
MAIN ROUTINE
§ Initialise the following data parameters to the default value
Power Level 10
Weight 0
Auto Weight 1
Timer 0
10 MIN 0
1 MIN 0
10 SEC 0
Start 0
Stop 0
Cook Time 0
Count 100
Magnetron 0
PowerLevel’ 0
MAIN ROUTINE
§ Enable Port 1 for Input with Interrupt with Low Select
§ Enable INT0 and INT1
§ Initialise Timer 2 for Auto Reload and enable interrupt but do not
start the timer
§ WAI

KEY PRESS
§ Interrupt on KBE
§ Find if auto cook key is pressed
§ If auto cook – load cook time, power level and weight for the auto
cook.
§ If Weight – Increment parameter weight by 100
§ If Auto weight – Enable RS232C of 8051 ED2
§ Detect weight from load cell and write it into parameter weight.
§ If Power level decrement Power level by 2 – if Power level equal to 0
reset to 10
§ If Timer read port 2
§ Calculate cook time

KEYPRESS - START
1. If Start is pressed and all parameters are at default set cook time
to 30 seconds close door and turn on magnetron.
2. If already cooking; on increment cook time by 30 seconds.
3. If start is pressed user defined parameters
§ Start Timer 2
§ Start timer 0 for auto reload – Initialise TL0, TH0 to 131
§ Close Lock
§ Start magnetron

KEYPRESS - STOP
§ Stop magnetron
§ Stop Timer 0
§ If stop pressed once – hold cook time
§ If stop pressed twice – clear cook time
§ Release Lock

TIMER0
§ Toggle Port 1.7

TIMER 2
Decrement count for second
If second is complete decrement cook time
If cook time zero stop magnetron and Timer0. Release Lock
If cook time has not reached zero – check if power level is 10
If power level is not 10 check if magnetron is on
If on decrement power level – if power level is zero stop magnetron
If Magnetron is off – check power level‘ – decrement power level’ if
zero – turn on magnetron.

The ARM Cores
M3: Embedded Architectures- 1: RISC Architecture -
ARM
ARM- Characteristics
• Soft Processor – IP core processors
• 32- bit RISC
RL 3.1.1 Embedded System Design © K.R.Anupama &

• Load Store Architecture
• Fixed- Length 32-bit instructions
• 3-address instruction format
Inst dst,src1,src2
Register window
Meetha.V.shenoy
•
• Delayed branches
• Single cycle instructions
2
Register Windowing
Input
Registers

Local
Registers m( a+x(n!))
Output Input
Registers Registers
Local n!
Main
Registers Sub2
y = r*m( a+x(n!))
Output Input
Meetha.V.shenoy
Registers Registers
Sub1 Local
Registers
Output
Registers
3
• 32- bit RISC
• Pipelined – 3 stage
Fetch

Decode
Execute
• PC – points to inst being fetched
• Von-Neumann Architecture
• Memory Access – only load/store/swap
• Data is aligned
Meetha.V.shenoy
• Two Instruction sets
32-bit ARM
16-bit THUMB – Instruction Compression
4
ARM Cores
ARMv4 ARMv5TE ARMv6 ARMv7-A

ARMv4T ARMv5TEJ
SIMD ARMv7-R
Thumb2
Trust zone
Neon
E-Enhanced ARMv7-M
J-Jazelle DBX
Meetha.V.shenoy
next 5
•
•
•
•
SISD
MISD
SIMD
MIMD
Flynn’s Taxonomy

6
Meetha.V.shenoy
SISD

7
Meetha.V.shenoy
SIMD

8
Meetha.V.shenoy
A: I1 A,B
SIMD B: I1 C,D
Data Bus A

Data Bus A
ALU MAC Shifter ALU MAC Shifter
Meetha.V.shenoy
A B
9
MISD

Meetha.V.shenoy
10
MIMD
back

Meetha.V.shenoy
11
Features ARM7TDMI ARMcortexM3
Arch ARMv4T (Princeton) ARMv7M (Harvard)
Pipeline 3-stage 3-stage-branch

speculation
Interrupts IRQ/FIQ NMI+1-240 h/w
Int-Latency 24-42 24

Sleep None Integrated
Memory No Yes
Protection
Speed 0.95 DMIPS/MHz (A) 1.25 DMIPS/MHz
0.74 DMIPS/MHz (T)
Power 0.28mW/MHz 0.19mW/MHz
Meetha.V.shenoy
12
ARM- Programmer’s
Model & Operating
Modes
ARM
• 32- bit RISC
• Pipelined – 3 stage
Fetch

Decode
Execute
• PC – points to inst being fetched

• Von-Neumann Architecture
• Memory Access – only load/store/swap
• Data is aligned
Meetha.V.shenoy
• Two Instruction sets
32-bit ARM
16-bit THUMB – Instruction Compression
• Bi-Endian
2
•
•
•
ARM
Thumb
Switching - BX
Operating States

3
Meetha.V.shenoy
Operating Modes
• 7 modes of operation
Privileged
User Mode – default – executes applns
•
modes

• FIQ – Fast Interrupt
• Interrupt
• Supervisor mode – protected mode –OS
• Abort Mode
System Mode – privileged user mode
Meetha.V.shenoy
•
• Undefined Mode
4
Registers
• ARM has 37 registers
31 – GPRS, 6 SR
• Not all registers – available to programmers

• In ARM state – 16 GPR 1/2 SR are accessible
• In each of privileged modes – separate banks of registers
are accessible
• r0 - r15
• r15 – Program Counter –valid bits [31:2] –ARM state
• r14 – Link Register
Meetha.V.shenoy
• r13 – Stack Pointer
• CPSR – CCR/Flags
• In privileged modes – SPSR
5
r0 r0 r0 r0 r0 r0
r1 r1 r1 r1 r1 r1
r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4
r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6

r7 r7 r7 r7 r7 r7
r8 r8_fiq r8 r8 r8 r8
r9 r9_fiq r9 r9 r9 r9
r10 r10_fiq r10 r10 r10 r10
r11 r11_fiq r11 r11 r11 r11
r12 r12_fiq r12 r12 r12 r12
r13 r13_fiq r13_svc r13_abt r13_irq r13_und
Meetha.V.shenoy
r15(PC) r15(PC) r15(PC) r15(PC) r15(PC) r15(PC)
CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
User FIQ Supervisor Abort IRQ Undefined 6

r0 r0 r0 r0 r0 r0
r1 r1 r1 r1 r1 r1
r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4
r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6

r7 r7 r7 r7 r7 r7
r15(PC) r15(PC) r15(PC) r15(PC) r15(PC) r15(PC)
CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
User FIQ Supervisor Abort IRQ Undefined
Meetha.V.shenoy
Thumb State Registers
7
r0 r0
r1 r1
r2 r2
r3 r3
r4 r4
r5 r5
r6 r6
r7 r7

r8
Mapping between r9
Thumb & ARM r10
r11
r12
r13 r13
r14 r14
Meetha.V.shenoy
r15(PC) r15(PC)
CPSR CPSR
SPSR SPSR
8
Program Status Registers
7 0
I F T M4 M3 M2 M1 M0
- A1- A0
A3 A2 - - - - E A
B3 B2 B1 B0
- GE1- GE0
GE3 GE2 - - GE3 GE2 GE1 GE0
N Z C V Q - - J

31
24
M4- M0 Mode
All insts in ARM state are
10000 User executed conditionally
10001 FIQ
10010 IRQ
Meetha.V.shenoy
10011 Supervisor
10111 Abort
11011 Undefined
11111 System 9
ARM- Instruction Set
-1
ARM
Addressing Modes
• Mode 1: Shifter operands for data processing inst
• Mode 2: Load/Store word/unsigned byte

• Mode3: Load/Store half-word/signed byte
• Mode4: Load/Store multiple
• Mode5: Load/Store co-processor
Meetha.V.shenoy
2
31-28 27 26 25 24-21 20 19-16 15-12 11-0
Cond 0 0 I opcode S Rn Rd Operand 2
ADD {condn} {S} Rd, Rn, <Oprnd2>

EQ #32 bit
NE Rm LSL #5bit
CS Rm LSR #5bit

CC
Rm ASR #5bit
MI
Rm ROR #5bit
PL
Rm
VS
Rm LSL Rs
VC
HI Rm LSR Rs
Meetha.V.shenoy
LS Rm ASR Rs
GE Rm ROR Rs
LT
LE No Condition Taken as AL
AL 3
ADD R2, R2,#1
ADD R4,R5, R5, LSL #2
ADD R10,R15,#8
ADDS R4,R5,R6, LSR R7

R4 = 00 00 00 02 + 00 00 00 10
R2 = 20 02 10 55 R2 = 20 02 10 56
R10 = 00 A0 B1 08
R5 = 00 00 00 02
R4 = 00 00 00 02 + 00 00 00 08
R15 = 00 A0 B1 00
R6 = 00 00 00 02
Meetha.V.shenoy
R7 = 00 00 00 03
4
Arithmetic & Logical
Instructions
Arithmetic Logical

• ADD • AND
• ADC • ORR
• SUB • EOR
• SBC • BIC
• RSB
RSC
Meetha.V.shenoy
•
5
31-28 27 26 25 24 23 22 21 20 19- 15- 11-0
16 12
Cond 0 1 1 P U B W L Rn Rd Addr mode
LDR/STR {condn} {B} {T} Rn, Rd, <Addr Mode>

EQ
NE
CS

+/-
CC
MI size
PL
0 x post
VS
1 0 pre
VC
1 1 Pre+W
HI
Meetha.V.shenoy
LS
GE
LT
LE
AL 6
LDR R1, [R0] Address in R0
LDR R8, [R3, #4]
Address = [R3]
LDR R12, [R13, #-4] R3 = R3 +4
STR R2, [R1, #0x100] Address = [R13]
R13 = R13 -4
LDRB R5, [R9]
Address = [R1]
STRB R4, [R10, #0x200] R1 = R1 +0100H

Address in R9
Address = [R10]
R10 = R10 +0200H
Meetha.V.shenoy
7
Address = [R1]
LDR R11, [R1, R2] R1 = R1 + R2
STRB R10, [R7, -R4] Address = [R7]
R7 = R7 + R4
LDR R11, [R3, R5, LSL #2]
Address = [R13]
LDR R1, [R0, #4]! R13 = R13 + R5 * 4
LDR R3, [R9], #4 R0 = R0 +4
Address = [R0]+4
STR R2, [R5], #8

LDR R0, [R1], R2 Address = [R9]+4
STRB R7, [R6, #-1]!
Meetha.V.shenoy
8
Transfer btwn memory & reg
LDR/LDRB/LDRH/LDRSH
STR/STRB/STRH/STRSH
ADR

Meetha.V.shenoy
9
ARM- Instruction Set
– 2 & Pipelining
ARM
Addressing Modes
• Mode 1: Shifter operands for data processing inst
• Mode 2: Load/Store word/unsigned byte

• Mode3: Load/Store half-word/signed byte
• Mode4: Load/Store multiple
• Mode5: Load/Store co-processor
Meetha.V.shenoy
2
x = (a+b)-c;
ADR r4,a
LDR r0,[r4]

ADR r4,b
LDR r1,[r4]
ADD r3,r0,r1
ADR r4,c
LDR r2,[r4]
SUB r3,r3,r2
Meetha.V.shenoy
ADR r4,x
STR r3,[r4]
3
31-28 27 26 25 24 23 22 21 20 19-16 15-0
Cond 1 0 0 P U 0 W L Rn Reg List
LDM/STM {condn} <addr mode> Rn, <Reg List>
Examples

LDMIA R0, {R5 - R8}
STMDA R1!, {R2, R5, R7 - R9, R11}
STMFD R13!, {R2-R9}
STMEA R13!, {R2-R9}
Meetha.V.shenoy
Addressing Mode – IA, IB, DA, DB, FD, FA, EA,ED
4
0x204 20304050
0x200 21314151
0x1fc 22324252
0x1f8 23334353
0x1f4 24344454

0x1f0 25354555
0x1ec
0x1e8
0x1e4
0x1e0
Meetha.V.shenoy
Stack Fully
EmptyDescending
Descending
5
0x204
0x200
0x1fc
0x1f8
0x1f4
0x1f0 24344454

0x1ec 23334353
0x1e8 22324252
0x1e4 21314151
0x1e0 20304050
Meetha.V.shenoy
Stack Fully
EmptyAscending
Ascending
6
Branch instructions
conditional branch forwards /backwards up to 32MB
branch /jump can also be generated by writing a value to R15
31-28 27 26 25 24 23-0
Cond 1 0 1 L 24- immediate value

B/BL {condn} ,<Immediate Value>
Examples
B label
BCC label
BEQ label
MOV PC, #0
Meetha.V.shenoy
BL func
MOV PC, LR
LDR PC, #func
7
Pipeline in ARM
• 3 stages of pipeline
• Fetch-Decode-Execute

• Normal Instruction require three clock cycles –
inst exec latency
• 1 cycle/instruction does not hold good for all insts
• Multiple load instruction
• Several cycles during execution phase
Meetha.V.shenoy
8
add r0,r1,r2 fetch decode execute
sub r2,r3,r6 fetch decode execute
cmp r2,r4 fetch decode execute

Meetha.V.shenoy
9
add r0, r1,r2 fetch decode execute
ldmia r0,{r1,r3} fetch decode execute execute
add r0,r2,r3 fetch decode
sub r0,r0,r7 fetch

Data stall
Meetha.V.shenoy
10
stall
bne nxt fetch decode execute execute execute

sub r2,r3,r6 fetch decode execute
sub r1,r2,r5 fetch decode
nxt: add r0,r2,#3

fetch decode execute
2 holes
Meetha.V.shenoy
11
bne nxt fetch decode execute
nop fetch decode execute
nop fetch decode execute
sub r2,r3,r6

-----
nxt: add r0,r2,#3 fetch decode execute
Delayed Branching
Meetha.V.shenoy
12
ARM- Exceptions
ARM
ARM-Exceptions
• Handled by entering into different operating modes
• Exception Entry

Preserves the address of next instruction into LR
Copies the CPSR into SPSR
CPSR modes bits set to appropriate operating mode
Meetha.V.shenoy
2
Interrupts/ Address Entry F I
Exceptions Mode
Reset 0x 0000 0000 Supervisor 1 1
Undefined 0x 0000 0004 Undefined U 1
SWI 0x 0000 0008 Supervisor U 1
Pre-fetch 0x 0000 000C Abort U 1

Abort
Data Abort 0x 0000 0010 Abort U 1
IRQ 0x 0000 0018 IRQ U 1
FIQ 0x 0000 001C FIQ 1 1
Meetha.V.shenoy
3
Main Program
ADR r4,a
LDR r0,[r4]
LDR r4,[r2] FIQ
LDR r1,[r4]
ADD r3,r0,r1
r15 r14_fiq
CPSR SPSR_fiq

CPSR (Mode) - FIQ
Enters FIQ
r14_fiq - 4 r15
SPSR_fiq CPSR
Meetha.V.shenoy
4
r0
r1
r2
r3
r4
r5
r6

r7
r8 r8_fiq
r9 r9_fiq
r10 r10_fiq
r11 r11_fiq
r12 LR_FIQ r12_fiq
r13 r13_fiq
back-up
Meetha.V.shenoy
r14 r14_fiq
r15(PC)
CPSR
back-up
SPSR_FIQ SPSR_fiq
User FIQ 5
FIQ
• nFIQ pin –low
• Why FIQ – all high regs are banked – reduces int

latencies
• ARM checks for low level at the end of each instruction
• FIQ – disabled in privileged mode – F -1
Meetha.V.shenoy
6
FIQ - actions
• Actions Taken on FIQ
• R14_fiq = Address of next inst to be executed +4

• SPSR_fiq = CPSR
• CPSR[4:0] = FIQ mode
• T bit = 0 F=1 I=1
• PC = Address of FIQ ISR
Meetha.V.shenoy
• Exit From FIQ
• SUBS PC, R14,#4
7
IRQ
• nIRQ pin –low

• Actions Taken on IRQ
• R14_irq = Address of next inst to be executed +4
• SPSR_irq = CPSR
• CPSR[4:0] = IRQ mode
• T bit = 0 I=1
• PC = Address of IRQ ISR
Meetha.V.shenoy
• Exit From IRQ
• SUBS PC, R14,#4
8
Supervisor Mode
• Entry-SWI
• Actions Taken on SWI

• R14_svc = Address of SWI + 4
• SPSR_svc = CPSR
• CPSR[4:0] = Supervisor mode
• T bit = 0 I=1
• PC = Address of Supervisor Routine
Meetha.V.shenoy
• Exit From Supervisor
• MOVS PC, R14
9
Undefined
• Inst than cannot be handled by ARM/co-processor
• Actions Taken on Undefined

• R14_und = Address of Instruction + 4
• SPSR_und = CPSR
• CPSR[4:0] = Undefined mode
• T bit = 0 I=1
• PC = Address of Undefined Routine
Meetha.V.shenoy
• Exit From Undefined
• MOVS PC, R14
10
ARM- Exceptions -
Abort
ARM
ARM-Exceptions
• handled by entering into different operating modes
• Exception Entry

Preserves the address of next instruction into LR
Copies the CPSR into SPSR
CPSR modes bits set to appropriate operating mode
Meetha.V.shenoy
2
Abort- Prefetch
• Current inst cannot be completed
• ABORT i/p checks for abort at the end of every memory

access
• Allows implementation of demand-paged virtual

memory system
• Proc is allowed to generate arbitrary address
• Data at address not available - MMU generates abort
Meetha.V.shenoy
3
1
5
4
3
2
0
7
4
2
i
i
i
v
v
v
Page Table
7
2
0
F
A
Physical Memory
A
D
E
B
Disk
F
C

4
Meetha.V.shenoy
40 ADR R1,A A: ADR R1,A
ADR R2,B
44 ADR R2,B
LDR R0,[R1]
48 LDR R0,[R1]
LDR R1,[R2]
4C LDR R1,[R2]
B: ADD R2,R1,R0
50 ADR R7,D
ADD R2,R1,R0
ADR R1,C
54 ADR R1,C
R8,E

STR R2,[R1]
58 LDR R11,[R7]
STR R2,[R1] Abort
MMU
Meetha.V.shenoy
Physical Memory
5
Abort handler
• Works out the causes of abort
• Load the inst that caused the abort

• Check whether the inst modifies – base reg
• Determine the offset from inst
• Restore base reg - original value - applying opposite

offset
• Two Types of Abort

Pre-fetch
Meetha.V.shenoy
Data
6
Pre-fetch Abort
• ARM marks it
• Takes action only when it enters into execute pipeline

stage
• If inst is not executed – fails condition code/branch-

abort does not take place
• Abort handler takes over in case of abort
• Exits to original state and inst is tried again
Meetha.V.shenoy
7
Prefetch Abort
• Actions Taken on Pre-fetch Abort
• R14_abt = Address of aborted inst +4

• SPSR_abt = CPSR
• CPSR[4:0] = Abort mode
• T bit = 0 I=1
• PC = Address of Abort ISR
Meetha.V.shenoy
• Exit From Pre-fetch Abort
• SUBS PC, R14,#4
8
Data Abort
• Action depends on inst type
• LDR/STR- restores base reg

• SWP
read access – suppress write access and write to destn reg
Write access – supress write to destn reg
• LDM/STM
• Abort in middle of data t/f –rest of regs not affected
• If base reg was part of reg to be loaded – returned to
Meetha.V.shenoy
original state
9
00 FE
00 ADR R0,0
CA
04 ADR R1,B DE
08 LDMIA R0!, {R1,R2,R3} 45
0C ADD R1,R1,R2 04 11
78
0F ADD R3,R1,R3 12

13
34
R1 – 45DECAFE
R0 – 0000 0004
AA
5A
R2-
R2 –00000000
5A341278
R0-
R0 –00000000
0000 0008
Meetha.V.shenoy
MMU
Abort
10
How does it distinguish between
Pre-fetch & Data Abort?
• Pre-fetch abort occurs in fetch stage
• Data abort occurs in execute state

Meetha.V.shenoy
11
Data Abort
• Actions Taken on Data Abort
• R14_abt = Address of inst that caused abort +8

• SPSR_abt = CPSR
• CPSR[4:0] = Abort mode
• T bit = 0 I=1
• PC = Address of Abort ISR
Meetha.V.shenoy
• Exit From Data Abort
• SUBS PC, R14,#8
12
AMBA
M4: Embedded Architectures- 2: ARM based LPC23xx
Some Common Bus Terminologies
• Bundle
• Handshake
• Timing Diagram
• Changing States
• Stable States
• Timing Constraints
• Wait states
• Burst transfer
• Disconnected/Split Transfers
RL4.1.1 Embedded System Design © K.R.Anupama &

2
Meetha.V.shenoy
Option Performance Cost
Bus width Separate Multiplexing

addr/data
Data width Wider Narrower
Transfer Size Multiple words Single word
Bus Master Multiple Single
Split Yes No
Transaction
Clocking Synch Asynch

3
Meetha.V.shenoy
Low-Speed
CPU Device
Low Speed Bus
Bridge
High Speed Bus
Low-Speed
Device
High-Speed
Memory
Device

4
Meetha.V.shenoy
1000
CPU Speed
100
10
DRAM Speed
1975 1980 1985 1990 1995 2000 2005 2010

UART
ARM
Bridge
AHB/ASB APB
Timer
Memory DMAC

6
Meetha.V.shenoy
INTRODUCTION TO LPC
23XX
Features - LPC23xx series - ARM-
based microcontrollers
• 10/100 Ethernet MAC
• USB 2.0 Full Speed interface
• 4 UARTs
• 2 CAN channels
• 1 SPI interface
• 2Synchronous Serial Ports (SSP)
• 3 I2C interfaces
• 1 I2S interface,
• 1 MiniBus

2
Meetha.V.shenoy
Members of the 23xx family
• LPC2364/65/66/67/68
• LPC2377/78
• LPC2387
• LPC2388

3
Meetha.V.shenoy
Features
• ARM7TDMI-S processor, running at up to 72 MHz
• FCCO = (2 × M × FIN) / N
• Up to 512 kB on-chip Flash Program Memory with ISP& IAP
• Upto 64 kB of SRAM on the ARM local bus - high performance CPU
access
• 16 kB Static RAM for Ethernet i/f
• 8 kB Static RAM for USB i/f

4
Meetha.V.shenoy
Clk Generation
Main Osc
PLL cpu
Int RC mux mux clk div
RTC clksrcreg

5
Meetha.V.shenoy
Low Power Mode of operation
• Single 3.3 V power supply (3.0 V to 3.6 V).
• 3 Three reduced power modes:
• Idle
• Sleep
• Power-down
• Done using PCON

• 4 external interrupt inputs-
In addition every PORT0/2 pin can be
configured as an edge sensing interrupt
• Any of the ext ints along with USB,CAN or Ethernet BOD, RTC can
wake up the processor from power down

6
Meetha.V.shenoy
Brown out Detection
3.3
2.9
2.65
Int
Reset
Enable - PCON

7
Meetha.V.shenoy
RC Osc
GPIO ARM7TDMI Vec Int Cntlr
SRAM Flash PLL
P0,P1,
P2,P3, AHB2 AHB1
P4 AHB Bridge AHB Bridge
16 KB Ethern 8 KB USB+4k
SRAM et AHB-AHB Bridge SRAM SRAM+DMA
MAC+
DMA GP DMAC
AHB-APB Bridge
2k Battery RAM RTC

EINT0-3
P0,P2 External Int I2S
Timer (0-3) SPI,SSP0
6x
PWM1
PWM1 SSP1
P0,P1
Legacy GPIO SD/MMC
8x AD
ADC UART0,2,3
AOUT
DAC UART1
Watch Dog Timer CAN1,2
System control RL4.1.2 Embedded System Design © K.R.Anupama & I2C

8
Meetha.V.shenoy
AHB peripherals(256M)
APB peripherals(256M)
Reserved(512M)
Reserved
Bank(1) 64kb
Bank(0) 64kb
8K Boot Block
Reserved
Memory Map
16kb Ethernet RAM
8kb USB RAM

Reserved
32K SRAM
Reserved Memory
Space
512RL4.1.2
KBEmbedded
NV Meetha.V.shenoy
Memory
System Design © K.R.Anupama &
9
LPC 23XX- GPIO
Features
• GPIO PORT0 & PORT1
• accessible
• group of reg providing enhanced features accelerated port access
• legacy group of reg
• PORT2/3/4 are accessed as fast ports only.

• Accelerated GPIO functions
• GPIO regs are relocated to the ARM local bus so that the fastest possible
I/O timing can be achieved

2
Meetha.V.shenoy
Features
Mask reg allow treating sets of port bits as a group
All GPIO registers are byte and half-word addressable
Entire port value can be written in one instruction
Bit-level set and clear
Direction control of individual bits
D31 D30 D29 D28 D27 D26 D25 D24

D23 D22 D21 D20 D19 D18 D17 D16
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0

3
Meetha.V.shenoy
Interrupt generating digital ports
• PORT0 & PORT2 provide an interrupt for each port pin
• Each int can be programmed to generate an int on a rising edge, a
falling edge, or both
• Asynch
• GPIO0 & GPIO2 ints share the same VIC slot with EI3

4
Meetha.V.shenoy
Total pins -112
• Port 2
• Pin 14-31 NA
• Port 3
• Pin 8-22 NA
• Pin 27-31 NA
• Port 4
• Pin 16-23 NA
• Pin 26-27 NA

5
Meetha.V.shenoy
Port 0 & 1 How do they func ?
• Use as GPIO/ Fast I/O - SCS Reg Bit 0 – GPIOM
• Pin Select Registers
• Every pin has alternate functions
• 00 – GPIO P0.0
RD
TXD3 PIN0.0
SDA
• Pin Mode Registers – Select Pull-up/Pull down

6
Meetha.V.shenoy
How to use GPIO?
• Regs – Legacy –Only for port0/1
• IOxPIN
• IOxSET
• IOxCLR
• IOxDIR

7
Meetha.V.shenoy
How to use FGPIO?
FIOxPIN
FIOxPIN0-3
FIOxPINL / FIOxPINU
FIOxSET
FIOxSET-3
FIOxSETL / FIOxSETU
FIOxCLR
FIOxCLR-3
FIOxCLR / FIOxCLRU
FIOxDIR
FIOxDIR0-3
FIOxDIRL / FIOxDIRU
FIOxMASK
FIOxMASK0-3
FIOxMASKL / FIOxMASKU

8
Meetha.V.shenoy
Input with Interrupt
• IntEnR
• IntEnF
• IntStatR
• IntStatF
• IntClr
• IntStatus
Int2S Int0S

9
Meetha.V.shenoy
LPC 23XX- TIMER
Features
• Four Timer/Counters
• 4 channels/Timer
• A minimum of 2 capture i/ps & 2 Match o/ps are pinned out for all 4
timers
• Choice of several pins for each
• 32 bit Timer/Counter with programmable 32 bit Prescaler
• Counter / Timer operation

2
Meetha.V.shenoy
Example
• Program LPC 23xx to count the no. of objects crossing a particular
point within a period of 1 second. Also find the time interval
between two objects

3
Meetha.V.shenoy
INPUT CAPTURE

4
Meetha.V.shenoy
Channel 0 CAP0.0
Channel 1 CAP0.1
Channel 2
Channel 3
Timer 0

5
Meetha.V.shenoy
Input Capture EDGB:EDGA
CLK
32-bit
000A
0005
Counter
H PT
Edge
Capture
000A
0005HReg Detector
CF
CI Interrupt Logic
Interrupt Request

6
Meetha.V.shenoy
Program for Input Capture
Turn on Timer 0/1/2/3
PCONP
Bit1 :PCTIM0
Enabled on Reset
Bit2 :PCTIM1
Bit22 :PCTIM2
Bit23 :PCTIM3
PINSEL Registers

7
Meetha.V.shenoy
Input Capture 0.0 P1.26 AltF3, P3.23 AltF2
Input Capture 0.1 P1.27 AltF3, P3.24 AltF2
Input Capture 1.0 P1.18 AltF3




8
Meetha.V.shenoy
Clock for Timer 0/1/2/3
PCLK Selection Register 0 0 0 CCLK/4
Bit2-3 :PCLK_TIMER0
0 1 CCLK
Bit4-5 :PCLK_TIMER1
PCLK Selection Register 1 1 0 CCLK/2
Bit12-13 :PCLK_TIMER2
1 1 CCLK/8
Bit14-15 :PCLK_TIMER3

9
Meetha.V.shenoy
Pre Scale for Timer 0/1/2/3
TxPR
TxPC
TxC

10
Meetha.V.shenoy
Select Clock for Timer/Counter
Counter Control Register for Timer 0/1/2/3
CCxR
CIS1 CIS0 CM1 CMO

CAP x.0 0 0 0 0 Rising Edge
PCLK
CAP x.1 1 0 0 1 Rising edge

CAP
Resv 0 1 1 0 Falling edge

CAP
Resv 1 1 1 1 Both edges

CAP
11
Meetha.V.shenoy
PCLK SEL 0:1 CPR
÷1/2/4/8 Pre-Scale+1
CCLK
Counter
CAP
CCR

12
Meetha.V.shenoy
Capture Registers for Timer 0/1/2/3
TxCCR
CA1I CAP1FE CAP1RE CA0I CAP0FE CAP0RE
Program Interrupt Unit

13
Meetha.V.shenoy
TxCR
TR TE

14
Meetha.V.shenoy
TxIR
IC3 IC2 IC1 IC0 IM3 IM2 IM1 IM0
Ack Interrupt

15
Meetha.V.shenoy
Capture Registers for Timer 0/1/2/3
TxCR0-TxCR3

16
Meetha.V.shenoy
OUTPUT COMPARE

17
Meetha.V.shenoy
Features
4 32 bit match registers that allow
Continuous op with optional int generation on match
Stop timer on match with optional int generation
Reset timer on match with optional int generation
Up to 4 external o/ps corresponding to match regs
Set low on match
Set high on match
Toggle on match
Do nothing on match
18
Meetha.V.shenoy
Output Compare
Reset/Continue/Stop
on Match
CLK
32-bit
0005
0004
0003
0002
0000
0001
counter
OL0
OL1 PT
PTx
32-bit comparator CF
Logic
Match
0005Reg
CI INT
Logic
Interrupt
19
Meetha.V.shenoy
Output Compare 0.0 P1.28 AltF3, P3.25 AltF2
Output Compare 1.0 P1.22 AltF3



Output Compare 3.1 P0.11 AltF
RL4.1.4 Embedded 3Design © K.R.Anupama &
System
20
Meetha.V.shenoy
Program for Output Compare
Match Registers for Timer 0/1/2/3
TxMR0-TxMR3
TxMCR
MR2S MR2R MR2I MR1S MR1R MR1I MR0S MR0R MR0I
MR3S MR3R MR3I

21
Meetha.V.shenoy
Program for Output Compare
External Match Registers for Timer 0/1/2/3
TxEMCR
EMC1 EMC0 EM3 EM2 EM1 EMO
EMC3 EMC2

22
Meetha.V.shenoy
Program LPC 23xx to count the no. of
objects crossing a particular point within a
period of 1 second. Also find the time
interval between two objects.

23
Meetha.V.shenoy
LPC 23XX- WATCH DOG
Feed Sequence WDTC
Feed Ok
WDFEED
Feed Error
RTC Osc
32-bit down cntr
PCLK ÷4
Internal
RC OSC
WD CLK Sel Shadow bit
WDINT WDTOF WDRESET WDEN

Int
Reset
Feed Sequence FFH
Feed Ok
AA
55HH
Feed Error
RTC Osc
FFH
00
PCLK ÷4
Internal
RC OSC
WD CLK Sel Shadow bit
WDINT
1 WDTOF
1 WDRESET WDEN
Int
Reset
CLK Select
PCLKSELREG0 0:1
WDCLKSELECT Reg WDSEL
WDTCReg
Minimum value = 256
Minimum Time out – TwCLK*4*256

Maximum Time out – TwCLK*4*232
WDMOD
WDTV Reg
LPC 23XX- VIC
Features
• Vectored Int Cntlr
• Mapped to AHB addrs space for fast access
• Supports 32 vectored IRQ int
• 16 programmable int priority levels
• Fixed h/w priority within each programmable priority level

• H/w priority level masking
• Any i/o can be assigned as an FIQ int
• s/w int generation

2
Meetha.V.shenoy
FIQ
32 Int . Vectored
sources Int Controller
.
.
IRQ

3
Meetha.V.shenoy
Interrupt Sources
Bit 31 30 29 28 27 26 25 24
Src I2S I2C2 UART3 UART2 Timer3 Timer2 GPDMA SD/MMC
Bit 23 22 21 20 19 18 17 16
Src CAN1&2 USB Ether BOD I2C1 AD0 EINT3 EINT2
Bit 15 14 13 12 11 10 9 8
Src EINT1 EINT0 RTC PLL SSP1 SPI1 / I2C0 PWM1

SSP0
Bit 7 6 5 4 3 2 1 0
Src UART1 UART0 Timer1 Timer0 ARM ARM - WDT

Core1 Core0

4
Meetha.V.shenoy
Soft Int Clr Int Enable Clr
FIQ
Soft Int Int Enable FIQ Status
Int 0-31
IRQ Status
Raw Int
Int Select

5
Meetha.V.shenoy
H/w & S/w Mask
bits
s/w priority mask
IRQ
A Status 0 Latch VIRQ0
S/w priority Mask0 Priorit Priority
H/w priority Mask0 y Mask Logic
IRQ
Logic
Vector Priority0 VIRQ1
Vector Address 0
Vector
Select
IRQ
Status 1
Vect Addr
or
Addr
IRQ ess
Status 31
6
Meetha.V.shenoy
VIC Interrupt Selection Registers
(32-bit Reg)
Classifies each Interrupt as IRQ/FIQ

7
Meetha.V.shenoy
Software Interrupt Register
VICSoftInt -32 –bit Register
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
ORED
Peripheral interrupts
VICSoftIntClr
Clearing S/w Interrupt bits
VICIntEnClr
8
Meetha.V.shenoy
Vector Address Registers
VICVR0 – VICVR31

9
Meetha.V.shenoy
Software Priority Mask Register
VIC Protection Enable Register

1 Bit – To indicate whether the int register can be
accessed in User Mode

10
Meetha.V.shenoy
Vector Priority Registers
VICVPR0 – VICVPR31
P3 P2 P1 P0

11
Meetha.V.shenoy
Vector Enable Register
Each Bit for enabling each channel

12
Meetha.V.shenoy
Status registers
IRQ Status Register
FIQ Status Register
VICRawIntr

13
Meetha.V.shenoy
Status registers
VIC Address Register

14
Meetha.V.shenoy
External Interrupt
Registers
EXTINT
EXTMOD
EXT POL
EINT3 EINT2 EINT1 EINT0

15
Meetha.V.shenoy
LPC 23XX- ADC /DAC
ADC

2
Meetha.V.shenoy
Features
• 10 bit successive approximation
• I/p multiplexing among 6 pins or 8 pins.
• Power down mode
• Measurement range 0 to 3 V
• 10 bit conversion time ≥ 2.44 μs.
• Burst conversion mode for single or multiple i/ps
• Optional conversion on transition on i/p pin or Timer Match signal
• Individual result regs for each A/D channel

3
Meetha.V.shenoy
VREF
AD0
AD1
AD2
AD3
ADC
AD4
AD5
AD6 VDDA
AD7 VSSA
ADC clock
10-bit data

4
Meetha.V.shenoy
PCONP: 8
PCLKSEL0: 25-24
PINSEL

5
Meetha.V.shenoy
AD0INTEN
ADGINTEN
ADINEN
Program Interrupt Unit

6
Meetha.V.shenoy
AD0CR
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
CLKDIV
PDN CLKS Burst
EDGE START
000 No Start ADC clock < 4.5 MHz
001 SOC
010 SOC – EINT0
011 SOC-CAP0.1
100 SOC-MAT0.1
101 SOC-MAT0.3
110 SOC-MAT1.0
111 SOC-MAT1.1
7
Meetha.V.shenoy
AD0STAT
CHD7 CHD6 CHD5 CHD4 CHD3 CHD2 CHD1 CHD0
CHO7 CHO6 CHO5 CHO4 CHO3 CHO2 CHO1 CHO0
ADINT

8
Meetha.V.shenoy
10-bit data 15:6
AD0DR0:AD0DR7 30-Overrun
AD0GDR 31- Done
26:24- CH No.
Ack Interrupt

9
Meetha.V.shenoy
DAC

10
Meetha.V.shenoy
Features
10 bit DAC
Buffered output
Power down mode
Selectable speed vs. power
VREF
AOUT
VDDA
VSSA
10-bit data
11
Meetha.V.shenoy
DAC always on
PCLKSEL0 23:22
PINSEL1, PINMODE1

12
Meetha.V.shenoy
DACR
DATA
BIAS
0 - 1µs
1 - 2.5µs

13
Meetha.V.shenoy
LPC 23XX- SPI & SSP
SPI

2
Meetha.V.shenoy
Features
• Synchronous, Serial, Full Duplex Communication
• SPI master or slave
• Maximum data bit rate of one eighth of the input clock rate
• 8 to 16 bits per transfer
• Single Master/Slave

3
Meetha.V.shenoy
MOSI
MISO
Master
Slave SPI
SPI
SCLK
SS
PCONP: 8 (On reset enabled)

PCLKSEL0 :16,17
4
Meetha.V.shenoy
SCLK CPOL =0
SCLK
CPOL =1
SS
CPHA =0
MOSI
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
CPHA =1
MOSI
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

5
Meetha.V.shenoy
Master Slave
SPCR SPCR
SPIE LSBF M CPOL CPHA BITE SPIE LSBF M CPOL CPHA BITE
1 0 1 0 0 0 1 0 0 0 0 0
BITS BITS
X X X X X X X X
2 1
3
SPDR
MOSI
Shift Reg Shift Reg
SPICLK(0:7) 1 SPDR 3
SPSR
SPF WCOL ROVR MODF ABRT
SPSR
SPICLK(0:7)
SPIR
SPIF SPF WCOL ROVR MODF ABRT
4 SPIR
6
2
Meetha.V.shenoy
SPIF
PCONP: 12 – Default on
PCLKSEL0: 16-17
PINSEL

7
Meetha.V.shenoy
S0SPCCR – even no. ³ 8
SPCR
SPDR

8
Meetha.V.shenoy
SPIR
SPSR

9
Meetha.V.shenoy
SSP 0/1

10
Meetha.V.shenoy
Features
• Synchronous Serial Communication
• Master or slave operation
• 8 frame FIFOs for both transmit and receive
• 4 to 16 bits frame
• DMA transfers supported by GPDMA
• 2 I/f SSP0,SSP1
• Supports three formats-TI,SPI,Microwire

11
Meetha.V.shenoy
MOSI/DX/SO
MISO/DR/SI
Master
Slave SPI
SPI
SCLK/CLK/SK
CS/FS/SS
PCONP: 10,21 (On reset enabled)

PCLKSEL1 :10,11 PCLKSEL0 :20,21
12
Meetha.V.shenoy
SCLK
FS
DX/DR
Bit4 Bit3 Bit2 Bit1
FS
DX/DR Bit4 Bit3 Bit2 Bit1 Bit4 Bit3
TI Format

13
Meetha.V.shenoy
SK
SS
SO
Microwire Format

14
Meetha.V.shenoy
SSPxCR0
CPHA CPOL FRF DSS
SCR
SSPxCR1
SOD MS SSPE LBM
SSPxCPR 7:1 (2-254 – even)

CLK = PCLK/SSPxCPRx[SCR+1]
SSPxDR
15
Meetha.V.shenoy
SSPxSR
BSY RNF RFE TNF TFE

16
Meetha.V.shenoy
SSPxRISR
TXRIS RXRIS RTRIS RORRIS

SSPxIMR
TXIM RXIM RTIM RORIM
SSPxMISR INT
TXMIS RXMIS RTMIS RORMIS
SSPxICR
RTIC RORIC

17
Meetha.V.shenoy
SSPxDMACR
TDMAE RDMAE

18
Meetha.V.shenoy
LPC 23XX- 2
IC & 2
IS
2
IC – 0/1/2

2
Meetha.V.shenoy
Features
• Moderate Speed 100kbps- 400 kbps
• Serial Data Line (SDL) /Serial Clock Line (SCL)
• Synchronous
• Master/Slave PE 2
(Slave)
PE 1 Data
(Master)
Clock
PE 3
(Slave)

3
Meetha.V.shenoy
Ack bit Stop bit
start bit R/W Ack bit
address data
D0 D1 – D7 D8 D9 D10 – D17 D18D19

4
Meetha.V.shenoy
Features
• Configured as Master, Slave, Master/Slave
• Arbitration betwn simultaneously txing masters without
Programmable clock
• Bidirectional data t/f between masters & slaves
• Serial clock synch allows devices with different bit rates to
communicate via one serial bus
• Serial clock synch- can be used as handshake mechanism to
suspend & resume t/f
• SDA0/1/2- SCL0/1/2

5
Meetha.V.shenoy
2
I C Types of Data T/f
• Master transmitter to a slave receiver
• 1st byte txed by master - slave addr
• Next follows a no. of data bytes
• Slave returns an ack bit after each rxed byte

6
Meetha.V.shenoy
2
I C Data Type
• Slave transmitter to a master receiver
• 1st byte – slave address - txed by the master
• Slave returns ack bit
• Next follows data bytes txed by the slave to master
• Master returns ack bit after all received bytes other than the last byte
• Last received byte, a “not ack” is returned
• Master generates SCL , START & STOP conds
• T/f ends with STOP condn /repeated START condn

7
Meetha.V.shenoy
I2C Operating Modes
Appln – I2C may operate - master/ slave/ both
Master Mode
Slave
Bus No
free?
Yes
Master
Yes Arbit
lost?
No
8
Meetha.V.shenoy
I2C Operating Modes
Appln – I2C may operate - master/ slave/ both
Slave Mode
Addr
=mine
Yes
?
No
No Addr
=bcas
t?
Yes
Int
9
Meetha.V.shenoy
Master Transmission
S Slave addr 0 A Data A A P
Master Receive
S Slave addr 1 A Data A A P
Master Receive Þ Master Transmit

S S addr 1 A Data A A S S addr 0 A Data A A P

10
Meetha.V.shenoy
Arbitration Loss
Master Tx
Master Rx
Wired AND Logic –SDA - Arbitration
Wired AND Logic- SCL - Synchronization

11
Meetha.V.shenoy
M1
M2
Bus
Arbitration Loss
Arbitration
12
Meetha.V.shenoy
CL1
CL2
SCL
Synchronization Process

13
Meetha.V.shenoy
Address Register 8
I2ADR
I/p Comparator
SDA Filter
O/p
Stage Shift Register ACK I2DAT
8
Bit cntr/
APB Bus
I/p Timing PCLK
SCL Filter Arbt/
Sync &
O/p
Control INTR
Stage Serial
Clock
Generato
I2CONSET
r
I2CONCLR Control/CLK Reg 16
I2SCH:I2SCL
Status Status Decoder 8
Reg RL4.2.4 Embedded System Design © K.R.Anupama &
Meetha.V.shenoy I2STAT 14
2
IS

15
Meetha.V.shenoy
Features
• Std commn i/f for digital audio appns
• Defines a 3-wire serial bus - data, clock, word select
• One master- always the master
• Separate transmit & receive channel
• Capable of handling 8, 16, and 32 bit word sizes

• Mono and stereo audio data supported

16
Meetha.V.shenoy
Features
• Sampling frequency range 16 - 96 kHz. (16, 22.05, 32, 44.1, 48, 96
kHz)
• 2 -8 byte FIFO data buffers
• Generates int req when buffer levels cross boundary
• Two DMA requests
• Controls include reset, stop & mute options
• Supports NXP Inter IC Audio format for 8, 16 & 32 bits audio data
both for stereo & mono modes

17
Meetha.V.shenoy
SCK
WS
SD
Left channel data Right channel data
TX_SCK, TX_WS, TX_SD

RX_SCK, RX_WS,RX_SD
18
Meetha.V.shenoy
SD
SCK Audio o/p
Tx Unit WS
SD
SCK Audio i/p
WS
Rx Unit

19
Meetha.V.shenoy
Data Formats
Mono -8 bit
data4 data3 data2 data1
Stereo-8bit
data2r data2l data1l data1r
Mono-16bit
Stereo-16bit
data2r data2l data1l data1r
Mono-32bit
20
Meetha.V.shenoy
Digital Audio Output/Input Register
ws_sel reset stop mono Size
Mute WS_Size
TxFIFO Reg
RxFIFO Reg
TxCLK Reg/ RxCLK Reg – 0:9
Sample Rate – 48 KHz
Then value of clock - 48KHz x 2x16

21
Meetha.V.shenoy
LPC 23XX- CAN
Features
• Serial commn protocol
• Efficiently supports distributed real-time control with a very high

level of security
• CAN has been subdivided into different layers
◊ (CAN-) object layer

◊ (CAN-) transfer layer
◊ physical layer

2
Meetha.V.shenoy
Appln Layer
Object Layer
•Message Filtering
•Message & Status Handling
Transport Layer
•Fault Confinement
•Error Detection & Signaling
•Message Validation
•Ack
•Arbitration
•Message Framing
•T/f rate & Timing
Physical Layer
•Signal level & Bit Repsn
•Tx medium
3
Meetha.V.shenoy
Message Transfer is done in frames
Frame Types
Data Frame
Remote Frame
Error Frame
Overload Frame
Frames are separated by IFS
Bit – Dominant/Recessive

4
Meetha.V.shenoy
Frame Format ACK EOF
Arbitration Control Data CRC
CRC
SOF de-limiter

5
Meetha.V.shenoy
Arbitration Field
I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 RTR
Control Field
R R DL3 DL2 DL1 DL0

6
Meetha.V.shenoy
CAN Features in LPC 23xx
• 2 CAN controllers & buses
• Supports 11-bit/29-bit identifier
• Double Rx Buffer & Triple Tx Buffer
• Programmable Error Warning Limit & Error Counters with
read/write access
• Arbitration Lost Capture
• Error Code Capture with detailed bit position

• Listen Only Mode
• Reception of "own" messages
• RD1/2,TD1/2

7
Meetha.V.shenoy
CAN core
APB Bus I/f mngmnt block
Logic Error
mngmnt RXD
Logic CAN Txr
VIC
TXD
Tx Buffers Bit
Common 1,2,3 Timing
Status Logic
Regs
Bit
Acceptan Rx Buffers stream
ce Filter 1,2 processor

8
Meetha.V.shenoy
LPC 23XX- USB
Features
• Bus between a host system & a no. of interconnected systems
• Designed
• Allow peripherals to be connected using a single standardized i/f

socket
• To improve plug-and-play capabilities - hot swapping
• Providing power to low-consumption devices
• Many devices to be used without requiring manufacturer specific
individual device drivers to be installed

2
Meetha.V.shenoy
USB Signalling
• USB supports four data rates
• Low Speed - (1.1, 2.0) rate of 1.5 Mbit/s
• Mostly used for Human Interface Devices (HID) such as keyboards, mice &
joysticks
• Full Speed (1.1, 2.0) rate of 12 Mbit/s
• Full Speed was the fastest rate before the USB 2.0 specification
• Many devices fall back to Full Speed
• Hi-Speed (2.0) rate of 480 Mbit/s

• Super-Speed (3.0) rate of 4.8 Gbit/s
• Due to the inclusion of a fiber optic link that works with traditional copper
connectors

3
Meetha.V.shenoy
USB Signals
• USB cable has four lines
• + 5V
• Gnd
• Two for data (D+, D-)
• NRZI – NRZ with zero stuffing when there are more than 6 one’s
• Sync field – sync tx and rx clocks

4
Meetha.V.shenoy
USB Interface
Device Host Device

Root Hub
hub2 hub1 Device
Device Device Device hub3
Device Device

5
Meetha.V.shenoy
Device Classes
• Devices can be full-custom devices requiring a full-custom device
driver or may belong to a device class
• These classes defn an expected behavior in terms of device & i/f
descriptors so that the same device driver may be used
• An OS is supposed to implement all device classes so as to provide
generic drivers for any USB device

6
Meetha.V.shenoy
Class Usage Description Examples
Use class info in the
00h Device -
I/f Descriptors
01h I/f Audio speaker, microphone, sound card
02h Both Communications ethernet adapter, modem
Human Interface
03h I/f keyboard, mouse
Device (HID)
05h
06h
07h I/f Printer
USB flash drive, memory card reader,
08h I/f Mass Storage
digital audio player
09h Device USB hub
(This class is used together with class 02h -
0Ah I/f Commn-Data
Communications and CDC Control.)
0Bh I/f Smart Card

7
Meetha.V.shenoy
Class Usage Description Examples
0Dh I/f Content Security
0Eh I/f Video webcam
DCh Both Diagnostic Device
E0h I/f Wireless Controller Wi-Fi adapter, Bluetooth adapter
EFh Both Miscellaneous ActiveSync device
FEh I/f Application Specific IrDA Bridge
FFh Both Vendor Specific

8
Meetha.V.shenoy
Device Recognition
3.3 V
Host/ D+ D+
Device
Hub D- D-
Full Speed

9
Meetha.V.shenoy
Device Recognition
3.3 V
Host/ D+ D+
Device
Hub D- D-
Low Speed

10
Meetha.V.shenoy
Data Transfer types
• Controlled data transfer
• Bulk data transfer
• Interrupt driven data transfer
• Iso- synchronous data transfer

11
Meetha.V.shenoy
USB transaction consists of three
packets
• Token packet (header)
• Optional Data packet (info)
• Status packet (ack)
• SOF – 11-bit frame sent every 1ms ± 500ns FS /125µ 0.0625 µs
Sync PID ADDR ENDP CRC5 EOP
Sync PID Data CRC16 EOP
Sync PID EOP

Sync PID Frame No. CRC5 EOP

12
Meetha.V.shenoy
Pipes & Endpoints
• A single phy USB device may consist of several logical sub-devices
• Referred to as device functions
• Each individual device may provide several functions
Host Controller
Logic Pipes
End Points
Devices
13
Meetha.V.shenoy
Pipes & Endpoints
• A USB device can have - 32 active pipes- 16 into/ 16 out of host
cntlr
• Endpoint can t/f data in one direction only- each pipe is uni-
directional
• Endpoints grouped into i/fs - each i/f is associated with a single
device func
• Exception - endpoint zero- used for device config - not associated
with any i/f

14
Meetha.V.shenoy
USB Functions
• Bus is Host Centric- host may send data to end-point buffer any
time
• Device cannot write to the bus – so writes to end-point buffer and
waits for bus to read
• Host cntlr polls the bus for traffic - in a round-robin fashion- no USB
device can t/f data on the bus without an explicit req from the host
cntlr
• Pipes have a set of params defn
• Type of data t/f
• Dir of data flow
• Max pkts/buffer size

15
Meetha.V.shenoy
V Bus
DMA USB
Bus master I/f Connect
Engine
USB ATX
EP_RAM D+
Serial I/f
AHB Bus
Reg I/f Access

Engine D-
Control
USB Up
LED
EP_RAM
(4k)

16
Meetha.V.shenoy
LPC 23XX- GPDMA
Features
• Two DMA channels
• GPDMA provides 16 peripheral DMA req lines
• Single DMA and burst DMA request signals
• DMA burst size is set by programming the GPDMA
• Memory-to-memory, memory-to-peripheral, peripheral-to-

memory & peripheral-to-peripheral t/f s
• Scatter or gather DMA is supported through the use of linked lists

2
Meetha.V.shenoy
Features
• Hardware DMA channel priority
• AHB slave DMA programming i/f
• AHB bus master for transferring data
• 32 bit AHB master bus width
• Incrementing /non-incrementing addring for src & dst

• Internal four-word FIFO /channel

3
Meetha.V.shenoy
Features
• Supports 8, 16, and 32 bit wide transactions
• Big-endian and little-endian support
• Int to the processor can be generated on a DMA completion/ DMA
error
• Int masking
• Raw int status

4
Meetha.V.shenoy
DMA Block Diagram
AHB Control
AHB Bus Slave Reg &
I/f Logic
DMA req DMA AHB

Channel
req/ Master AHB Bus
DMA res Reg &
res I/f
Logic
I/f
DMA int Int

Req

5
Meetha.V.shenoy
Programming a DMA channel
• Choose a free DMA ch with the priority reqd
• Clear
any pending int on the ch to be used by writing to the
DMACIntTCClr Register /DMACIntErrClr
• Src addr - DMACCxSrcAddr Reg
• Destn addr - DMACCxDestAddr Reg
• Write the addr of the next Linked List Item (LLI) into the
DMACCxLLI Reg - if the t/f consists of a single packet of data then
0 must be written into this reg

6
Meetha.V.shenoy
RC Osc
GPIO ARM7TDMI Vec Int Cntlr
SRAM Flash PLL
P0,P1,
P2,P3, AHB2 AHB1
P4 AHB Bridge AHB Bridge
16 KB Ethern 8 KB USB+4k
SRAM et AHB-AHB Bridge SRAM SRAM+DMA
MAC+
DMA GP DMAC
AHB-APB Bridge
2k Battery RAM RTC

EINT0-3
P0,P2 External Int I2S
Timer (0-3) SPI,SSP0
6x
PWM1
PWM1 SSP1
P0,P1
Legacy GPIO SD/MMC
8x AD
ADC UART0,2,3
AOUT
DAC UART1
Watch Dog Timer CAN1,2
System control RL4.3.3 Embedded System Design © K.R.Anupama & I2C

7
Meetha.V.shenoy
Introduction to DSP
M5: Embedded Architectures- 3: DSP Architectures
Characteristics &
Embodiments of a DSP
RL5.1.1 Embedded System Design © K.R.Anupama & Meetha.V.shenoy 2

D D D D
x
hn-1 hn-2 hk h0
Y
TAP
FIR Filtering
Sx*h

adr r6,x0
adr r7,h0 data
memory
adr r5,b path
loop:
ldaa r0,[r6],#4
ldaa r1,[r7] ,#4
mul r1,r1,r0
add r2,r1
staa r2,[r5],#4
decs r4
bnz loop

Issues with using GPP for
u Memory bandwidth bottleneck

u Control code & addressing overhead
u Possibly slow multiply
u (Computes one tap per loop iteration)

Characteristics of DSP Systems
Algorithms
u Algorithms specify arithmetic operations to be

performed
u Implemented in general purpose processors, or
programmable DSP processor or custom integrated
circuits
u Implementation technology depends on required speed
& arithmetic precision
u e.g. Speech coding, decoding, speech encryption,
decryption, Speech recognition, Speech Synthesis,
Speaker Identification, Vision, Image Compression,
decompression

Characteristics of DSP
Systems – Sample Rate
u Rate at which samples are consumed, processed, or produced
u Algorithm & Sample rate determines speed of implementation
technology
u e.g. CD player produces samples at a rate of 44.1KHz to be
converted to digital audio tape rate of 48 KHz.
u Ratio of sample rates is awkward- Conversion is done in stages
u Two intermediates stages
u Input must be accepted every 22.6 s
u New Output sample must be produced every 20.8 s
u System fails with producing sample on time -> data corrupted
u Multi-rate systems

Characteristics of DSP
Systems – Clock Rate
u Rate at which system does a basic unit of work
u Usually 100 MHz
u Higher rates in high performance products
u Ratio of clock rate : sample rate important
u Determines amount of h/w needed to implement
algorithm
u Ratio ß amount and complexity of h/w Ý

Numeric Representations and Arithmetic
DSP Processors
Fixed-point Floating point
16-bit 24-bit 32-bit
IEEE 754 Other

Introduction to DSP
Numeric Representations
in DSP

Fixed Point
u Numbers with fixed range between –1.0 to +1.0

u Finite number of bits of precision- word width
u 8-bit fixed point- resolution of 1/256 between –1.0 and
+1.0
u Numbers outside this range cannot be represented
u Arithmetic Operations with results outside the range
u Saturate

Floating Point
u Number represent in two parts mantissa and exponent
u Mantissa must lie between –1.0 to +1.0
u Exponent keeps track of how much mantissa has been
scaled by power of 2
u Value = mantissa X 2 exponent
u Probability of Overflow and scaling reduced
u Simplify algorithm and software design
u Floating point arithmetic slower and more expensive
u Complexity of hardware increases

Dynamic Range
u Dynamic Range :
Largest Number
Smallest Number
u usually represented in dB

Quantization Error
u Error introduced when a larger numeric format no. is

converted to a shorter numeric format
u e.g. when 1.325 is rounded of to 1.33 Q.E. IS 0.005
u Greater the Q.E. w.r.t to size of the operand the lesser
is the precision
u Ratio of a the size of the value represented to size of
maximum Q.E. due to rounding off -> Precision

Precision
u Maximum Precision(in bits)=

log2 (|maximum value|/| maximum Q.E.|)
u 16-bit number largest value in fixed point is –1.0

u Max quantization error is 2-16
u Precision = log2(1/2-16) = 16

Fractional Representation – Fixed point Format
-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7
Radix Point
Sign bit
0 1 0 1 0 0 0 0
2-1+2-3 = 0.5+0.125 0.625

Largest Positive no. - 0.9921875
1 0 1 0 0 0 0 0
-20+2-2+2-4 = -1.0+ 0.25+ 0.0625 -0.6875

Fractional Representation –Floating point Format
Mantissa
S 1(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7
Sign bit Radix Point

Assumed to be present
Exponent
- 23 22 21 20
-128 => can be converted to -1.28 x 10 2
- 128 => can be converted to -1.0 x 27

Mantissa will be –1.0 10000000
Exponent will be 7 0111

Fractional Representation –Floating point Format
Mantissa
0 1 0 1 0 0 0 0
1 is assumed to be present
1.0+ 2-1+2-3 = 1.625
Exponent
0 1 0 1
22 + 20 = 5
Number is 1.625 x 25 = 52.0

IEEE 754 format of representation
Single precision
2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23
2-08 2-09 2-10 2-11 2-12 2-13 2-14 2-15
E0 2-01 2-02 2-03 2-04 2-05 2-06 2-07
S E7 E6 E5 E4 E3 E2 E1

Eg 1
0 1000 0011 1100……0
Exponent 1000 0011 = 131d
Mantissa = 0.75+1.0 = 1.75
+ve no.
X = (1.75) x 2131-127 = 28
Eg 2
1 0000 1111 0110……0
1.375 x 2-112 = 2.648 x10-34

Dynamic Range
u 32-bit fixed point

u Minimum number is 2 –31
u Maximum number is 1.0 – 2-31
u Ratio is 2.15 x 109
u Dynamic range is 187 dB
u 32-bit Floating point

u 24-bit mantissa 8-bit exponent
u Minimum Number is 5.88 x 10 -39 (1x2-127 )
u Maximum Number is 3.40 x 10 38 (1 x2127 )
u Ratio is 5.79 x 10 76
u Dynamic Range is 1539 dB

Introduction to DSP
DSP Architectures

Embodiments of a DSP – Fast
Multiply & Accumulate
u MAC operations – used in algorithms in Digital Filters,
Correlation and Fourier Transform
u Completed in single cycle
u DSP processors include multiplier and accumulator
integrated into main arithmetic processing unit (data
path)
u DSP processors generally provide extra bits in their
accumulator register
u Accommodate growth of accumulated result

Embodiments of a DSP –
Multiple Memory Access
u High bandwidth between processor and memory is
essential for good performance-> especially in case of
repetitive algos
u All but one memory location must be on-chip
u Multiple memory access are restricted to some
instructions
u Support for multiple access thro’ multiple on-chip buses
u Multiple independent memory banks
u Harvard Architecture

Program
P - Bus Memory
X-bus X- data memory
Y-bus Y-data memory

Data Bus A
Data Bus B
ALU MAC Shifter ALU MAC Shifter
A B
A: I1 A,B
SIMD B: I1 C,D
Internal Program
Memory (Cache)
8x32
Inst fetch, decode

& dispatch
VLIW nx32
L1 S1 M1 D1 L2 S2 M2 D2
Register File A Register File B
Internal
RL5.1.3 Embedded System Design Data
© K.R.Anupama RAM
& Meetha.V.shenoy 7
Superscalar Architecture
u Current superscalar architectures for DSP apps:

u ZSP ZSP164xx, Siemens TriCore (DSP/µC hybrid)
u Characteristics:
u Multiple (usually 2-4) instructions issued per instruction
cycle
u Instruction scheduling handled in hardware, not by
programmer
u RISC-like instruction set
u Lots of parallelism

Embodiments of a DSP Processor
– Special Addressing Mode
u Allow arithmetic processing to proceed at maximum

speed
u Multiple operands in a small instruction word
u DSP have dedicated DAG
u DAG operate in the background and ||ly with execution
of arithmetic instructions
u E.g. register-indirect with post increment

Embodiments of a DSP Processor
– Specialized Execution Unit
u DSP algorithms involve repetitive computations

u Efficient looping S Xn Yn
u Execution control features such as fast context
switching, low interrupt and branch latency
u Stacking/banking

Embodiments of a DSP
Processor – Peripherals
u For interface with I/O devices serial ports
u Specialized I/O handling mechanism such as DMA
u Peripheral devices are designed for direct i/f with
common peripherals such as DAC, ADC
u Some DSP processors have on chip ADC and DAC

Introduction to DSP
DSP Data Path
Fixed Point

Data Path of a DSP
u Vital arithmetic manipulation of signals
u Highly specialized to achieve high performance on the
types of computation most common in DSP applns
u Data path and memory arch-distinguishes DSP from
other processors
u Data path for floating-pt. processor is different from
that of a fixed pt. processor

Fixed Point DSP
u Multiplier
u ALU
u Operand registers
u Accumulator
u One or more Shifters
u Address calculation unit is separate from data path
u RISC – expect for addressing modes

X data bus
24
Y data bus
24
X0
X1 Operand registers
Dual Ported Y0
Y1
24 24
Multiplier
56 48
Shifter (-1, 0,+1)
ALU
56 24
Accumulators A (56)
24
B (56)
56 56
Shifter (-1, 0,+1) Limiter
24
24

5
Meetha.V.shenoy
PMD
DMD
Mux
MX (2x16) MY(2x16)
Mux Mux
16
16 16 16
X Y
Multiplier MF(16)
P
MV Adder/ Subtractor
40 Mux Mux Mux
MR2 8 MR1 16 MR0 16
Mux
6
Meetha.V.shenoy
DO dotprod UNTIL CE;
dotprod:
MR=MR+MX0*MY0(SS), MX0=DM(I0,M0), MY0=PM(I4,M4);

Shifter
u Guard bits do not remove the need for scaling

u Guard bits only prevent overflow
u If guard bits are 4
u Shifting must be done by 4 (i.e. scaling is done by 2–4)
u Some processors are shifted bit by bit
u Barrel Shifter are shifted totally by n bits.

Overflow & Saturation
u Overflow occurs when results becomes too large to fit

into acc
u For e.g. if addition of two 8-bit numbers results in a
value that is greater than 8-bits
u 01111111 + 0000 0001 – greater than size
u 01111111

Truncation
u One method to overcome overflow is saturation

u Second possible method is TRUNCATION where the LSB
are cutoff for e.g. 2.345-> can be truncated to 2.34
u 0111 1111 0.9921875
u 0111 0.875
u QE 0.1171875

Rounding
u Rounding can be of two types

u Simplest -> Rounding to nearest
u E.g. 2.346 -> is rounded 2.35
u Problem is with 2.345
u Convergent Rounding - if LSB is 0 number is rounded
downwards else upwards
u Available in NXP and ADSP processors

Data Path of a DSP processor
Operand A
A7 A6 A5 A4 A3 A2 A1 A0
B3 B2 B1 B0 Operand B
Round to nearest b3:b0 = a7:a4

Convergent rounding
If a3:a0 >1000 b3:b0 =a7:a4+a3
If a3:a0 <1000 b3:b0 =a7:a4+a3
If a3:a0 = 1000 b3:b0 =a7:a4+a4

Convergent Rounding -
Significance
u 4-bit format result 8-bit
u 00101000 0.3125 00011000 0.1875
u 0011 0010 0.25 0010 0010 0.25
u Diff : -0.0625 Diff:- +0.0625

Introduction to DSP
DSP Data Path
Floating Point

Data Path of a DSP
u Most floating point data paths can also do fixed pt.
functions
u But only one of them can be carried out per inst cycle
u Some floating point processors provide two data paths -
>one for fixed pt. and the other for floating point
numbers
u In such processors the fixed point data path usually does
not include a multiplier

Data Path of a DSP -
Multiplier
u Do not usually follow law of conservation of bits
u In case of 32-bit nos. 8-bits are for exponent and 24 bits
are mantissa
u By law of conservation of bits mantissa must be 48
u But in floating pt processors product is larger only by
few bits (8/12)

32 DU1
Operand
32 DU2
registers
X Y
Data Converter
Multiplier
S
P
45 40
Floating point adder
40
40
A0(40) Accumulators
A1(40)
A2(40)
A3(40)
32
5
Meetha.V.shenoy
Shifter
u In case of arithmetic operation results tend to grow
u Shifters are hence provided in the data path
u Here scaling is done automatically
u Shifter is usually invisible to user
u In case of processors where fixed-point and floating-
point data paths are the same-> shifter can be
controlled by user

TMS 6455
TMS 64X+ CPU -
Introduction

TMS 320 DSP Family
u Fixed-point
u Floating-point
u Multiprocessor
u TMS320 DSPs – arch is designed specifically for real-
time signal processing
u C2000, C5000, C6000
u C6000 – 1600 MIPS

TMS320C64x DSP Features
and Options
u C6000 devices execute max of 8 32-bit inst/ cycle
u 64 general-purpose 32-bit regs & 8 func units
u Two multipliers
u Six ALUs

Internal Program
Memory (Cache)
8x32 VelociTI
Inst fetch, decode

& dispatch
nx32
L1 S1 M1 D1 L2 S2 M2 D2
Register File A Register File B
Internal
RL5.2.1 Embedded System Design Data& Meetha.V.shenoy
© K.R.Anupama RAM 5
Features
u Instruction packing: reduced code size

u All instructions can operate conditionally: flexibility of
code
u Variable-width inst: flexibility of data types
u Fully pipelined branches: zero-overhead branching
u 8/16/32-bit data support

Features
u Each multiplier can perform 2 16x16 , 4 8 x 8 bit

multiplies every clock cycle
u Quad 8-bit & dual 16-bit inst set extensions
u Supports non-aligned word & double word memory
accesses
u Special commn specific insts for error-correcting codes
u Bit count & rotate h/w extends support for bit-level
algo

Features
u Compact instructions
u Protected mode operation
u Each multiplier can perform 32 x 32 bit multiplies
u Additional insts to support complex multiplies allowing
up to 8 16-bit multiply/add/subtracts/ clock cycle
u Exceptions support for error detection and program
redirection to provide robust code execution

64x
Program Cache/Program Memory
(32-bit addr/ 256-bit data)
Pwr Program Fetch

Dwn Control
Inst Dispatch
Regs
Inst Decode
Control
EDMA, Reg File A Reg File B Logic
EMIF
Test
.L1 .S1 .M1 .D1 .L2 .S2 .M2 .D2
Emulation
Ints
Data Cache/ Data Memory

Additional
(32-bit addr/ 8,16,32,64-bit data)
Peripherals
RL5.2.1 Embedded System 9
Design © K.R.Anupama &
64x+
L1P Cache/SRAM (32kB)
L2 PMC
Cache/
UMC
SRAM IDMA
(2M)
EMC
DMC Int Cntl

Pwr Cntl
L1D Cache/SRAM(32K)
Peripherals
u HPI
u I2C
u McASP
u McBSP
u PCI
u Power-down logic allows reduced clocking
u Two 32-bit general-purpose timers
u Time events
u Count events
u Generate pulses
u Interrupt the CPU

256
Program Fetch
SPLOOP Buffer
16/32- bit Inst Dispatch
Inst Decode
Reg File A Reg File B
.L1 .S1 .M1 .D1 .L2 .S2 .M2 .D2
64 64

S/W Pipelining
u Loop:
u Stage 1
u Stage 2
u Stage 3
u Stage 4

Stage1
Prolog
Stage2 Stage1
Stage3 Stage2 Stage1
Stage4 Stage3 Stage2 Stage1 Kernel
Stage4 Stage3 Stage2
Stage4 Stage3 Epilog
Stage4

Example
Iteration i Iteration i+1 Iteration i+2
LD F0, 0(R1)
ADDD F4, F0, F2 LD F0, 0(R1)
SD 0(R1), F4 ADDD F4, F0, F2 LD F0, 0(R1)
SD 0(R1), F4 ADDD F4, F0, F2
SD 0(R1), F4

TMS 6455
64X+ Computational Units

64x+
PMC
L2
Cache/
UMC
SRAM IDMA
(2M)
EMC
DMC Int Cntl

Pwr Cntl
L1D Cache/SRAM(32K)
src1 Odd
src2 Reg
.L1 odd dst
even dst
8
Even
long src
src1
Reg
src2
.S1 odd dst
even dst
long src 8
src1
.M1 src2
dst1
dst2
ST1b
ST1a
LD1b
LD1a
1X
src1
DA1 .D1 src2
dst
src1
DA2 .D2 src2

dst
.L
32/40-bit arithmetic & compare operations
32-bit logical operations
Leftmost 1 or 0 counting for 32 bits
Normalization count for 32 and 40 bits
Byte shifts
Data packing/unpacking
5-bit constant generation
Dual 16-bit arithmetic operations
Quad 8-bit arithmetic operations
Dual 16-bit minimum/maximum operations
Quad 8-bit minimum/maximum operations
.S
32-bit arithmetic operations
32/40-bit shifts
Branches
Constant generation
Reg t/fs to/from con reg file (.S2)
Byte shifts
Data packing/unpacking
Dual 16-bit compare operations
Quad 8-bit compare operations
Dual 16-bit shift operations
Dual 16-bit saturated arithmetic operations
Quad 8-bit saturated arithmetic operations
.M
32 x 32-bit multiply operations
Quad 8 x 8-bit multiply operations
Dual 16 x 16-bit multiply operations
Dual 16 x 16-bit multiply with add/subtract op
Quad 8 x 8-bit multiply with add operation
Bit expansion
Bit interleaving/de-interleaving
Variable shift operations
Rotation
Galois Field Multiply
.D
32-bit add, subtract, linear & circular addr
calculation
Loads and stores with 5-bit constant offset
Loads and stores with 15-bit constant offset
(.D2 only)
Load and store doublewords with 5-bit constant
Load and store nonaligned words and
doublewords
5-bit constant generation
LDW .D1T2 *A0[4],B1
TMS 64xx
Instruction Set 1

Parallel Operations
u Inst are always fetched 8 words at a time

u This constitutes a fetch packet
u On the C64x+ CPU- as many as 14 insts
u Fetch pkts are aligned on 256-bit boundaries

Instruction Packet
A p B p C p D p E p F p G p H p
●Fully serial
●Fully parallel
●Partially serial

A 0 B 1 C 1 D 0 E 0 F 1 G 1 H 0
1 A
2 B,C,D
3 E
4 F,G,H

ADD .S1 A0,A1,A2
|| SHR .S1 A3,A5,A4
MV .S1X B0,A0
|| MV .L1X B1,A1
ADD .L1X A0,B1,A1
|| ADD .S1X A2,B1,A2
MV .S1X B0,A0
|| MV .L1X B0,A1
|| MV .D1X B0,A2
ADD .S1 A0, A0, A1
||ADD .S2X A1, B0, B1
LDNW .D2T2 *B2[B12],B13 ;
|| LDB .D1T1 *A2,A14

MPY .M1 A1, A1, A4
|| ADD .L1 A1, A1, A5
|| SUB .D1 A1, A2, A3

Conditional Operations
Condition is controlled by a 3-bit creg & 1-bit z
creg z Codn
31 30 29 28
0 0 0 0 Uncodn
0 0 1 z B2
0 1 0 z B1
0 1 1 z B0
1 0 0 z A2
1 0 1 z A1
1 1 0 z A0
[B0] ADD .L1 A1,A2,A3

|| [!B0] ADD .L2 B1,B2,B3
Addressing Modes
Addressing No Pre Post
Type Modification
Register *R *++R *R++
Indirect *--R *R--
Register *+R[ofst5] *++R[ofst5] *R++[ofst5]
Relative *-R[ofst5] *--R[ofst5] *R--[ofst5]
Register *+B14/B15
Relative [ofst15]
Based + *+R[reg] *++R[reg] *R++[reg]
Indexed *-R[reg] *--R[reg] *R--[reg]

LDB .D1 *-A5[4],A7
LDB .D1 *++A4[5],A8
LDB .D1 *A4++[5],A8
LDB .D1 *++A4[A12],A8

LDW .D1 *A10,A1
LDW .D1 *A4++[1],A6
LDW .D1 *++A4[1],A6
LDDW .D1 *+A10[1],A1:A0

Circular Addressing
LDW .D1 *++A4[9],A1
A7M A6M A5M 0 1
B7M B6M B5M B4M
BK1 0 0 1 0 0

Adding offsets
.D1, .D2
ADDAB .D1 A4,A2,A4 A2 0000 000B
ADDAB .D1X B14,42h,A4

ADDAH .D1 A4,A2,A4
A4 0000 0100
ADDAH .D1X B14,42h,A4

AMR 0002 0001
ADDAW .D1 A4,A2,A4
ADDAW .D1X B14,42h,A4 B14 0020 1000
ADDAD .D1 A1,A2,A3

TI 6455
TMS 64X+ Instruction Set
Fixed Point

ADD (.unit) src1, src2, dst
unit = .D1, .D2, .L1, .L2, .S1, .S2
ADD (.L1 or .L2) src1, src2_h:src2_l, dst_h:dst_l
ADD (.D1 or .D2) src2, src1, dst

ADD
31-29 28 27-23 22-18 17-13 12 11-5 4 3 2 1 0
creg z dst src2 src1 X opcode 1 1 0 s p

ADD .L2X A1,B1,B2
A1 0000 325A B2 0000 316C
FFFF FF12
B1
ADD .L1 A1,A3:A2,A5:A4

A1 0000 325A A5 0000 0000
A3 0000 00FF A4 0000 316C
A2 FFFF FF12
ADD .L1 -13,A1,A6

ADD .D1 A1,26,A6
ADD .D1 A0,5,A2
ADDU (.unit) src1, src2, dst

unit = .L1 or .L2
ADDU .L1 A1,A2,A5:A4
A1 0000 325A A5 0000 0001
A2 FFFF FF12 A4 0000 316C

ADD2 (.unit) src1, src2, dst
unit = .L1 , .L2, S1,S2,D1,D2
ADD2 .S1X A1,B1,A2
A1 0021 37E1 A2 03BB 1C99
B1 039A E4B8
ADD2 .L1 A0,A1,A2

unit = .L1 , .L2
ADD4 .L1 A0,A1,A2
A0 FF 68 48 3D A2 3E 5E 39 42
A1 3F F6 F1 05

Adding 16-bit constant
.S1, .S2
ADDK .S1 3C29h,A1
ADDSUB Parallel ADD and SUB Operations On

Common Inputs
ADDSUB (.unit) src1, src2, dst_o:dst_e
unit = .L1 or .L2
ADDSUB .L1 A0,A1,A3:A2

Multiply Signed 16 LSB x Signed 16 LSB
MPY (.unit) src1, src2, dst
unit = .M1 or .M2
MPY .M1 A1,A2,A3

MPY .M1 13,A1,A2
Multiply Signed 16 MSB x Signed 16 MSB

MPYH (.unit) src1, src2, dst
unit = .M1 or .M2

MPYHL Multiply Signed 16 MSB x Signed 16 LSB
MPYHL (.unit) src1, src2, dst
MPYHL .M1 A1,A2,A3
MPYLH Multiply Signed 16 LSB xSigned 16 MSB

MPYLH (.unit) src1, src2, dst
MPYLH .M1 A1,A2,A3

Multiply 16 MSB x 32-Bit Into 64-Bit Result
MPYHI (.unit) src1, src2, dst_o:dst_e
MPYHI .M1 A5,A6,A9:A8
MPYHI .M2 B2,B5,B9:B8
MPYIH Multiply 32-Bit x16-MSB Into 64-Bit Result

MPYIH (.unit) src2, src1, dst
MPYIH .M1 A5,A6,A9:A8
MPYIH .M2 B2,B5,B9:B8

MPYHLU .M1 A1,A2,A3
MPYLHU .M1 A1,A2,A3
MPYHSLU .M1 A1,A2,A3
MPYHU .M1 A1,A2,A3
MPYHSU .M1 A1,A2,A3
MPYHUS .M1 A1,A2,A3
MPYHULS .M1 A1,A2,A3
MPYLI .M1 A1,A2,A5:A4
MPYIL .M1 A1,A2,A4:A5

Multiply 16 MSB x 32-Bit – rounded to a 32 –bit
result
MPYHIR (.unit) src1, src2, dst
MPYHIR .M2 B2,B5,B9

MPYU4 Multiply Unsigned X Unsigned, Four 8-Bit Pairs for Four
8-Bit Results
MPYU4 (.unit) src1, src2, dst_o:dst_e
MPYU4 .M1 A5,A6,A9:A8
MPY2 Multiply Signed by Signed, 16 LSB X16 LSB and 16 MSB

X16 MSB
MPY2 (.unit) src1, src2, dst_o:dst_e
MPY2 .M1 A0, A1, A3:A2
MPY .M1 A0, A1, A2
MPYH .M1 A0, A1, A3

MPY32 Multiply Signed 32-Bit x Signed 32-Bit Into Signed
64-Bit Result
MPY32 .M1 A5,A6,A9:A8
SMPY32 Multiply Signed 32 x Signed 32 With Left Shift and

Saturation
SMPY32 (.unit) src1, src2, dst
SMPY32 .M1 A5,A6,A8

0 1 1 0
X
0 1 1 0
0 0 0 0
0 1 1 0
0 1 1 0
0 0 0 0
0 1 0 0 1 0 0
0 0 1 0 0 1 0 0

CMPEQ Compare for Equality, Signed Integer
CMPEQ (.unit) src1, src2, dst
unit = .L1 or .L2
CMPEQ .L1X A1,B1,A2
CMPGT .L1X A1,B1,A2
CMPGTU .L1X A1,B1,A2
CMPLT .L1X A1,B1,A2

B Branch Using a Displacement
B (.unit) label
unit = .S1 or .S2
0000 0000 B .S1 LOOP
0000 0004 ADD .L1 A1, A2, A3
0000 0008 || ADD .L2 B1, B2, B3
0000 000C LOOP: MPY .M1X A3, B3, A4
0000 0010 || SUB .D1 A5, A6, A6

BDEC Branch and Decrement
Syntax BDEC (.unit) src, dst
unit = .S1 or .S2
BDEC .S1 func, A10
CMPLT .L1 A10,0,A1
[!A1] SUB .L1 A10,1,A10
||[!A1] B .S1 func (10-bit signed offset)

SHL Arithmetic Shift Left
SHL (.unit) src2, src1, dst
or
SHL (.unit) src2_h:src2_l, src1, dst_h:dst_l
unit = .S1 or .S2
SHL .S1 A0,4,A1
SHL .S2 B0,B1,B2
SHL .S1 A5:A4,0,A1:A0

adr r6,x0
adr r7,h0
adr r5,b
loop:
ldaa r0,[r6],#4
ldaa r1,[r7] ,#4
mul r1,r1,r0
add r2,r1
staa r2,[r5],#4
decs r4
bnz loop
data path memory

Loop

|| SMPY32 .M1X A2,B2, A0
|| LDW .D2 *B4++, B2
|| LDW .D1 *A4++,A2
|| BDEC .S2 Loop,B0

TMS 64X+ Instruction Set
Fixed Point

ADD (.unit) src1, src2, dst
unit = .D1, .D2, .L1, .L2, .S1, .S2
ADD (.L1 or .L2) src1, src2_h:src2_l, dst_h:dst_l

ADD
31-29 28 27-23 22-18 17-13 12 11-5 4 3 2 1 0
creg z dst src2 src1 X opcode 1 1 0 s p

ADD .L2X A1,B1,B2
A1 0000 325A B2 0000 316C
FFFF FF12
B1

A1 0000 325A A5 0000 0000
A3 0000 00FF A4 0000 316C
A2 FFFF FF12
ADD .L1 -13,A1,A6

ADD .D1 A1,26,A6
ADD .D1 A0,5,A2
ADDU (.unit) src1, src2, dst

unit = .L1 or .L2
ADDU .L1 A1,A2,A5:A4
A1 0000 325A A5 0000 0001
A2 FFFF FF12 A4 0000 316C

unit = .L1 , .L2, S1,S2,D1,D2
ADD2 .S1X A1,B1,A2
A1 0021 37E1 A2 03BB 1C99
B1 039A E4B8
ADD2 .L1 A0,A1,A2

unit = .L1 , .L2
ADD4 .L1 A0,A1,A2
A0 FF 68 48 3D A2 3E 5E 39 42
A1 3F F6 F1 05

Adding 16-bit constant
.S1, .S2
ADDK .S1 3C29h,A1
ADDSUB Parallel ADD and SUB Operations On

Common Inputs
ADDSUB (.unit) src1, src2, dst_o:dst_e
unit = .L1 or .L2
ADDSUB .L1 A0,A1,A3:A2

Multiply Signed 16 LSB x Signed 16 LSB
MPY (.unit) src1, src2, dst
unit = .M1 or .M2
MPY .M1 A1,A2,A3

MPY .M1 13,A1,A2
Multiply Signed 16 MSB x Signed 16 MSB

MPYH (.unit) src1, src2, dst
unit = .M1 or .M2

MPYHL Multiply Signed 16 MSB x Signed 16 LSB
MPYHL (.unit) src1, src2, dst
MPYHL .M1 A1,A2,A3
MPYLH Multiply Signed 16 LSB xSigned 16 MSB

MPYLH (.unit) src1, src2, dst
MPYLH .M1 A1,A2,A3

Multiply 16 MSB x 32-Bit Into 64-Bit Result
MPYHI (.unit) src1, src2, dst_o:dst_e
MPYHI .M1 A5,A6,A9:A8
MPYHI .M2 B2,B5,B9:B8
MPYIH Multiply 32-Bit x16-MSB Into 64-Bit Result

MPYIH (.unit) src2, src1, dst
MPYIH .M1 A5,A6,A9:A8
MPYIH .M2 B2,B5,B9:B8

MPYHLU .M1 A1,A2,A3
MPYLHU .M1 A1,A2,A3
MPYHSLU .M1 A1,A2,A3
MPYHU .M1 A1,A2,A3
MPYHSU .M1 A1,A2,A3
MPYHUS .M1 A1,A2,A3
MPYHULS .M1 A1,A2,A3
MPYLI .M1 A1,A2,A5:A4
MPYIL .M1 A1,A2,A4:A5

Multiply 16 MSB x 32-Bit – rounded to a 32 –bit
result
MPYHIR (.unit) src1, src2, dst
MPYHIR .M2 B2,B5,B9

MPYU4 Multiply Unsigned X Unsigned, Four 8-Bit Pairs for Four
8-Bit Results
MPYU4 (.unit) src1, src2, dst_o:dst_e
MPYU4 .M1 A5,A6,A9:A8
MPY2 Multiply Signed by Signed, 16 LSB X16 LSB and 16 MSB

X16 MSB
MPY2 .M1 A0, A1, A3:A2
MPY .M1 A0, A1, A2
MPYH .M1 A0, A1, A3

MPY32 Multiply Signed 32-Bit x Signed 32-Bit Into Signed
64-Bit Result
MPY32 .M1 A5,A6,A9:A8
SMPY32 Multiply Signed 32 x Signed 32 With Left Shift and

Saturation
SMPY32 (.unit) src1, src2, dst
SMPY32 .M1 A5,A6,A8

0 1 1 0
X
0 1 1 0
0 0 0 0
0 1 1 0
0 1 1 0
0 0 0 0
0 1 0 0 1 0 0
0 0 1 0 0 1 0 0

CMPEQ Compare for Equality, Signed Integer
CMPEQ (.unit) src1, src2, dst
unit = .L1 or .L2
CMPEQ .L1X A1,B1,A2
CMPGT .L1X A1,B1,A2
CMPGTU .L1X A1,B1,A2
CMPLT .L1X A1,B1,A2

B Branch Using a Displacement
B (.unit) label
unit = .S1 or .S2
0000 0000 B .S1 LOOP
0000 0004 ADD .L1 A1, A2, A3
0000 0008 || ADD .L2 B1, B2, B3
0000 000C LOOP: MPY .M1X A3, B3, A4
0000 0010 || SUB .D1 A5, A6, A6

BDEC Branch and Decrement
Syntax BDEC (.unit) src, dst
unit = .S1 or .S2
BDEC .S1 func, A10
CMPLT .L1 A10,0,A1
[!A1] SUB .L1 A10,1,A10
||[!A1] B .S1 func (10-bit signed offset)

SHL Arithmetic Shift Left
SHL (.unit) src2, src1, dst
or
SHL (.unit) src2_h:src2_l, src1, dst_h:dst_l
unit = .S1 or .S2
SHL .S1 A0,4,A1
SHL .S2 B0,B1,B2
SHL .S1 A5:A4,0,A1:A0

adr r6,x0
adr r7,h0
adr r5,b
loop:
ldaa r0,[r6],#4
ldaa r1,[r7] ,#4
mul r1,r1,r0
add r2,r1
staa r2,[r5],#4
decs r4
bnz loop
data path memory

Loop

|| SMPY32 .M1X A2,B2, A0
|| LDW .D2 *B4++, B2
|| LDW .D1 *A4++,A2
|| BDEC .S2 Loop,B0

TMS 6455
TMS 64X+ CPU – Modes of
Operation & Control Registers

Modes of Operation
u User Mode
u Supervisor Mode
u control the operation of unprivileged software
u protect access to critical system resources (ints)
u control entry to itself
u Privilege system allows 2 distinct types of op
u Supervisor-only execution
u Two-tiered system

Entry Into Supervisor Mode
u On reset
u On Interrupt
u On exception
u User Mode Entry
u TSR 6:7 – CXM
u For re-entry into Supervisor Mode
u SWE / SWENR

Control Registers
u AMR
u CSR
u PCE1
u DNUM
u SSR
u TSCH
u TSCL
u TSR

PGIE GIE
PWRD SAT EN
REV ID
CPU ID
CSR

Control Registers – Interrupts
u ICR
u IER
u IFR
u IRP
u ISR
u ISTP
u NRP
u ITSR

Control Registers – Exceptions
u ECR
u EFR
u IERR
u REP

TMS 6455
6455 Execptions

Exceptions
u Error Detection & Debugging

u Error signals outside - Single Input to CPU
u Exceptions within - One internal exception flag
u Fatal Errors Outside CPU - One Non-maskable

Exceptions
u Three types of exceptions on the C64x+ CPU

u One externally generated maskable exception
u One externally generated non-maskable exception
u Set of internally generated non-maskable exceptions

NMI
u Can be used as Int/Exception

u To use as Exception GEE -1 (TSR2)
u NMIE -1 (IER1)
u NXF (EFR31) - NMIF (IFR1)

EXCEP
u GEE -1 (TSR2)
u XEN -1 (TSR3)
u NMIE -1 (IER1)
u EXF (EFR30)

Internal Exceptions
u GEE -1 (TSR2)
u IXF (EFR1)

Exception Ack
u Exception processing (EXC) bit in TSR – o/p at CPU

boundary
u When CPU begins processing an exception- it
references IST
u NMI ISFP is used to service all exceptions

IERR
LBX PRX RAX RCX OPX EPX FPX IFX
MSX
TMS 64xx
Interrupts

Interrupt - Types
u Reset
u Maskable
u Non-maskable
u Exception

Reset
u Used to halt the CPU and return it to a known state
u Active-low signal
u Must be held low for 10 clock cycles before it goes high
again to reinitialize the CPU properly
u Inst exec in progress is aborted & all regs - returned to
default states
u ISR fetches pkt from specific address
u Not affected by branches

Resets
u Power-on Reset
u Warm Reset
u Max Reset
u System Reset
u CPU Local Reset

NMI
u 2nd highest priority int & is generally used to alert the
CPU of a serious h/w problem such as imminent power
failure
u For NMI processing to occur
u NMIE (IER) = 1
u NMIE - 0 at reset
u NMIE -0 at the occurrence of an NMI

IER
IE7 IE6 IE5 IE4 NMIE 1
IE15 IE14 IE13 IE12 IE11 IE10 IE9 IE8

Maskable Interrupts (INT4-
INT15)
u CPU has 12 interrupts that are maskable
u Ints can be associated with external devices, on-chip
peripherals, s/w control
u Foll conds must be met for ints
u GIE (CSR) =1
u NMIE (IER) = 1
u Corresponding IE (IER) =1

How is int serviced
u Processing of subsequent ints is disabled
u PGIE = GIE; GIE =0
u ITSR = TSR
u MVC writes to the TSR are completed before the TSR is
saved to the ITSR
u The next exec packets are annulled
u Address of the 1st annulled exec pkt IRP
u A branch to the addr formed from ISTP
u IFm is cleared

TSR
CXM XEN GEE SGIE GIE
IB SPLX EXC INT

XXXX 000 RESET ISFP
IST
XXXX020 NMI ISFP
XXXX040
XXXX060
XXXX080 INT4ISFP
XXXX0A0 INT5ISFP
XXXX0C0 INT6ISFP
XXXX0E0 INT7ISFP
XXXX100 INT8ISFP
XXXX120 INT9ISFP
XXXX140 INT10ISFP
XXXX160 INT11ISFP
XXXX180 INT12ISFP
XXXX1A0 INT13ISFP
XXXX1C0 INT14ISFP
XXXX1E0 INT15ISFP
Control Registers
u CSR - globally set /disable ints
u ICR
u IER
u IFR
u IRP -B IRP instruction
u ISR
u ISTP
u ITSR
u NRP -B NRP instruction.
u NTSR
u TSR

Interrupt Processing
u CPU int on C6455 device are configured thro’ C64x+
Megamodule Interrupt Controller
u Allows for up to 128 sys events to be programmed to
u Any of 12 CPU int i/ps (CPUINT4 - CPUINT15)
u CPU exception input (EXCEP)
u The advanced emulation logic
u The 128 system events
u Internally-generated events (megamodule)
u Chip-level events

Reset Reset
Exception
combiner
Excep
NMEvt NMI
Event IACK
Event combiner
Flags
Evt[3:0]
Evt[127:4] Int INT[15:4]
Selector
INTERR IDROP Mask IDrop[15:4]
CPU

64x+
PMC
L2
Cache/
UMC
SRAM IDMA
(2M)
EMC
DMC Int Cntl

Pwr Cntl
L1D Cache/SRAM(32K)
Peripherals
u HPI
u I2C
u McASP
u McBSP
u PCI
u Power-down logic allows reduced clocking
u Two 32-bit general-purpose timers
u Time events
u Count events
u Generate pulses
u Interrupt the CPU

INTRODUCTION
M6: DISTRIBUTED & MULTIPROCESSOR EMBEDDED SYSTEM DESIGN
SYSTEM
¡ H/w
¡ Control
¡ Data
RL6.1.1 EMBEDDED SYSTEM DESIGN © K.R.ANUPAMA & MEETHA.V.SHENOY 2

DISTRIBUTED SYSTEM
¡ Distributed H/w - Different Sys provide different funcs

¡ Distributed Control -Logical Resources/ Physical resources
¡ Distributed data
¡ Multiple copies of data at diff locations
¡ Single copy distributed over multiple locations
¡ Replication/ partitioning of data

CHARACTERISTICS OF A DISTRIBUTED SYSTEM
¡ Arbitrary No. of system and appln process (logical resources)

¡ Modular Physical Architecture
¡ Communication by message passing using shared commn. systems
¡ System wide control

SCHROEDER'S DEFINITION
¡ A list of symptoms of a distributed system

¡ Multiple processing elements (PEs)
¡ Interconnection hardware
¡ PEs fail independently
¡ Shared states

ENSLOW’S DEFINITION
¡ Distributed system = distributed h/w + distributed control + distributed data

¡ A system could be classified as a distributed system if all three categories
(hardware, control, data) reach a certain degree of decentralization

HARDWARE
¡ A single CPU with one control unit

¡ A single CPU – multiple ALUs – single control unit
¡ Separate Specialized functional units, such as one CPU with one floating pt. co-
processor
¡ Multi-processors with multiple CPUs but only one single I/O system and one global
memory
¡ Multiple computers with multiple CPUs, multiple I/O systems and local memories

CONTROL
¡ Single Fixed Control pt. – Physically the system may or may not have multiple
CPUs
¡ Single Dynamic Control point
¡ A fixed master - slave structure
¡ Dynamic master – slave structure
¡ Multiple Homogeneous control points – copies of the same controller are used
¡ Multiple Heterogeneous control points – different controllers are used
RL6.1.1 EMBEDDED SYSTEM DESIGN © K.R.ANUPAMA & MEETHA.V.SHENOY

DATA
¡ Centralized Data bases with a single copy of both files and dir
¡ Distributed files with a single centralized dir and no local dir
¡ Replicated database with a copy of files and dir at each site
¡ Partitioned data base with a master that keeps a complete duplicate copy of all
files
¡ Partitioned database with a master that keeps only a complete dir
¡ Partitioned database with no master file/dir

10

Item Network sys. Distributed sys. Multiprocessors
Like a virtual uni- No Yes Yes
processor
Run the same No Yes Yes

operating system
Copies of the N copies N copies 1 copy

operating system
Means of Shared files Messages Shared files

communication
Agreed up network Yes Yes No

protocols?
A single run queue No Yes Yes
Well defined file Usually no Yes Yes

sharing 11

SYSTEM DESIGN EXAMPLE
M6: DISTRIBUTED AND MULTIPROCESSOR EMBEDDED SYSTEM DESIGN
2

MEV
¡ The vehicle is six-wheeled with an on-board robotic arm to pick up samples and
on-board scientific instruments and cameras
¡ The primary aim of the vehicle is to explore the terrain, transmit images
captured by a CCD camera, measure atmospheric conditions in the mine and
assess samples of rocks and soil
¡ This can be controlled remotely from above the ground
¡ All subsystems on the vehicle are controlled by the remote unit and are in
contact with the remote unit through Memory & Alternate Application
subsystem.

MEV
¡ The MEV is made of the following subsystems

¡ Vehicular & Sample Collection
¡ Camera, Power & Sensor
¡ Memory & Alternate Application

MEV - COMMUNICATION
¡ All communications are at minimum of 10Kbps.

¡ You may assume that the antenna interface provides data inputs of suitable width
to your system.
¡ Each subsystem may have one or more controllers.

2

MEMORY & ALTERNATE
APPLICATIONS SUB-SYSTEM

SPECIFICATIONS
¡ 32 KB of SRAM and 512 KB of Flash Memory are required.

¡ If necessary, a new application program sent from the remote console (in not
larger than 8 KB Blocks) can be loaded into the internal memory.

SPECIFICATIONS
¡ There is a UHF antenna with the required transmitter and receiver circuit is
mounted on the vehicle.
¡ The vehicle should be able to uplink data using the UHF antenna to the remote
console available aboveground.
¡ The remote console analyses the data from the camera and also makes the
required navigation decisions.

2

CAMERA & SENSOR SUB-SYSTEM

SPECIFICATIONS
¡ The vehicle is powered by a Lithium ion battery.

¡ The on-board processors can operate at temperatures between – 50 C to 250C.
¡ If necessary a heating coil is available that can be switched on to increase the
local temperature and a cooling fan is available which can be switched on to
decrease the local temperature.
¡ These can be powered from the battery.

SPECIFICATIONS
¡ The on-board MEMS (Mine Environment Monitoring Station) consist of a sensor

package mounted on the camera mast and measures levels of combustible gases.
¡ The gases monitored are HCN, CH4, CO, C3H8.
¡ The sensor outputs are in the range of 0 – 5V.

SPECIFICATIONS
¡ There is one monochromatic Navigation camera.

¡ The navigation camera outputs 32-bit data that must be compressed to 16-bit
data.
¡ Data from the camera requires at least 12Kb of temporary storage space while
it is being processed.
¡ Data is sent from the camera as Frames.
¡ Eight frames are sent at a time.

SPECIFICATIONS
¡ Each frame is made up of 32-bits of data sent serially MSB first.

¡ Clock has to be provided to the camera for the data to be shifted.
¡ The camera first sends out a high pulse on its STB line indicating valid data is
available.
¡ This STB pulse is sent one clock cycle before data is shifted on the data lines.
¡ Maximum rate at which data is sent is 1 Mbps.

SPECIFICATIONS
¡ The camera subsystem functions as a slave subsystem to the sensor subsystem

and relays the compressed data to the sensor sub-system.
¡ Which in turn is sent to the Memory & Alternate sub-system immediately.

2

VEHICULAR MOTION & SAMPLE
COLLECTION SUB-SYSTEM

SPECIFICATIONS
¡ Each of the six wheels is to be powered by an individual motor so that the

vehicle is capable of climbing over obstacles not exceeding a certain height.
¡ The vehicle can execute a 3600 turn in-place.
¡ The front and rear wheels are used for steering.
¡ An upright position is to be maintained at all times and hence the suspension of
the vehicle cannot have a tilt > 450.
¡ The tilt is usually not allowed to exceed 300 during normal operation.

SPECIFICATIONS
¡ The vehicle should be capable of digging up to small depths.

¡ Digging is to be accomplished by spinning one of the front wheels in place to
grind into the soil.
¡ The same mechanism that is used for tilting the vehicle upwards is also used for
tilting the vehicle downwards.
¡ The vehicle is designed to remain motionless while the digging wheel is spinning.

SPECIFICATIONS
¡ DC motors are used for rotating the wheels and stepper motors are used for
steering.
¡ The two front wheels are locked together by the same steering mechanism; the
same is done in case of the rear wheels.
¡ A Robotic arm is used for sample collection.
¡ The robotic arm is capable of movement both in the horizontal plane and in the
vertical plane.

SPECIFICATIONS
¡ Allegro 3901 – Dual Full Bridge Motor Driver

¡ Internal PWM – DC Motor
¡ OUT
¡ IN 1 & IN2
¡ IN 1 – Low IN2 – High – Reverse
¡ IN 1 – High IN2 – Low – Forward
¡ IN 1 – High IN2 – High – Brake
¡ IN 1 – Low IN2 – Low - Sleep

SPECIFICATIONS
¡ Allegro A3967– Translator + Driver is available for Stepper Motor

¡ PINS
¡ RESET’
¡ ENABLE’
¡ SLEEP’
¡ MS0, MS1
¡ DIR
¡ STEP – high minimum 1µs –high/low

SPECIFICATIONS
¡ Data regarding movement and sample collection is obtained from Memory and
Alternate Program sub-system.

2

VEHICULAR MOTION & SAMPLE
COLLECTION SUB-SYSTEM

VEHICULAR – BASIC BLOCKS
¢ Tilt – Stepper Motors

¢ Front Wheel Steering – Stepper Motors
¢ Rear Wheel Steering – Stepper Motors
¢ Rear Wheel Rotation – DC Motors
¢ Front Wheel Rotation – DC Motors
¢ Robotic Arm – Horizontal Movement - Stepper Motor
¢ Robotic Arm – Vertical Movement – Stepper motor
¢ Communication Serial – Maximum 10 kbps – with Memory & Alternate Program
Subsystem

STEPPER MOTOR INTERFACE
RESET’
ENABLE’
SLEEP’
MS0 0 -GND
MS1 1- 5 V
DIR
STEP

HOW MANY STEPPER MOTOR INTERFACES
¢ Tilt – Stepper Motor

¢ Front Wheel Steering – Stepper Motor
¢ Rear Wheel Steering – Stepper Motor
¢ Robotic Arm – Horizontal Movement - Stepper Motor

¢ Robotic Arm – Vertical Movement – Stepper Motor
¢ 5

GENERATE A WAVEFORM FOR STEPPER
¢ 5 Compare Channels (PIN 1.2 – PIN 1.6)

¢ Rear Wheel
¢ Front Wheel
¢ Robotic arm – Horizontal
¢ Robotic arm – Vertical
¢ Tilt

DC MOTOR INTERFACE
¢ IN0
¢ IN1
¢ How Many
¢ Rear Wheel -1
¢ Front Wheel -1

COMMUNICATION WITH MEM & ALT PROG
¢ SCI
¢ TXD
¢ RXD
¢ 9600 Baud – Standard Rate

STEP1-T P3.0 P1.0 IN0 – R
STEP2-FS P3.4 P1.1 IN1 – R
STEP3-RS P3.5 P3.6 IN0 – F 8051RE2
STEP4-AH P3.6 P3.7 IN1 - F
STEP5- AV P3.7 P1.5 MISO
RESET’1 P2.0 P1.7 MOSI
RESET’2 P2.1 P1.6 SCLK
RESET’3 P2.2 P3.2 SS’
RESET’4 P2.3 P2.6 DIR2
RESET’5 P2.4 P2.7 DIR3
ENABLE’1 P0.0 P0.6 DIR4
ENABLE’4 P0.3
ENABLE’5 P0.4
10
SLEEP’ P2.5 24 MHz
SPCON
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
0 1 0 0 0 0 0 0

CMOD
CIDL WDTE CPS1 CPS0 ECF
0 0 0 0 0 0 1 0

ECOM CAPP CAPN MAT TOG PWM ECCF
1 0 0 1 0 0 1
CCAPM0-4
Compare Registers 0 - 4

CF CR CCF4 CCF3 CCF2 CCF1 CCF0
CCON

EA EC ET2 ES ET1 EI1 ET0 EI0
1 1 0 0 0 0 0 0
IE0

ES1 ESPI ETWI EKB
0 0 0 0 0 1 0 0
IE1

2

CAMERA & SENSOR SUB SYSTEM

BASIC BLOCKS – ON BOARD TEMP
MAINTENANCE
¢ Temperature Sensor ¢ ADC

¢ Heating Coil ¢ Relay – Port
¢ Cooling Fan ¢ Relay - Port

BASIC BLOCKS – SENSOR UNIT
¢ HCN ¢ ADC
¢ CH4
¢ CO
¢ C3H8

Heating
P4.0
Coil
Cooling AD0 HCN
P4.1
Fan AD1 CH4
AD2 CO
AD3 C 3 H8
AD6 Temp
LPC2378
6

¢ Camera Subsystem
TMS 6455 LPC 2378

INTERFACE
LPC 2378 TMS 6455

¢ Ports ¢ HPI

HDS1’
HR/W’ P3.4
HD0-HD15 P1.16-1.32
HINT EINT0
TMS 6455
HCNTL P3.2
P3.1
HHWIL P3.0
HCS’ P3.5
5V
HAS’
HDS2
HSIZE LPC2378
9

CAMERA INTERFACE
CAMERA TMS6455 - McBSP

¢ 32-bit ¢ DR
¢ 8 Frames
¢ Needs Clock ¢ CLKR
¢ Generates Ready 1 Clock Cycle ¢ FSR
before shifting out data

HDS1’
HR/W’ P3.4
HD0-HD15 P1.16-1.32
HINT EINT0
TMS 6455
HCNTL P3.2
P3.1
HHWIL P3.0
Data DR
AD0 HCN
Clk CLKR HCS’ P3.5
AD1 CH4
5V
STB FSR HAS’ AD2 CO
AD3 C 3 H8
AD6 Temp
HDS2
Camera HSIZE LPC2378
11

2

MEMORY & ALTERNATE PROGRAM
SUBSYSTEM

BASIC BLOCKS
¢ Commn with Vehicular System ¢ SSP0

¢ Remote Unit ¢ SCI
¢ No Multiple Access Scheme Required

¢ Large Amount of Memory
¢ Co-ordination
LPC 2378
MOS1
TXD0
Remote unit
RXD0 MISO
Vehicle Sub-system
SS
LPC SCLK
2378
12x2x12x1 = 48MHz
6
12 MHz

System Modeling -
UML
M7: Embedded Software Design
UML
§ Modeling System Behavior & Relationships
§ Static Behavior
§ Outside view of system
§ System Interaction
§ Dynamic Behavior
§ Concurrency
§ Persistence
§ Thread of control
§ System behavior whiles task execute
§ Interaction between system
Common UML Diagrams
§ Class
§ Use Case
§ Component
§ Communication
§ State Chart
§ Timing
§ Sequence
§ Activity
§ Object
§ Package
§ Composite Structure
§ Interaction
§ Deployment
Use Cases
§ Outside view of the system
§ Public i/f of module/system
§ What is system behavior as user sees it
§ Main components of system
§ User interaction with main components
§ Can be hierarchical
Actors
§ Executes use case
§ Supporting Actor
§ Active
§ Passive
Use Cases
How system can be used
Various Behaviors of the system
Encapsulates event/actions that must occur to implement intended behavior
of the system
Stated and expresses from point of view of user
All services offered to the user
Each use case has a textual component fully describing it
Very powerful tool during requirement phase
Use case diagram has to be as simple as possible
University Reg Program – use
cases
Student
Prof Info
Info
Create
Course Info Course
Catalog
Use Case - Relationships
General Browse
<<extends>> <<extends>>
Specialized Search
Use Case - Relationships
case2 Give Price
<<uses> <<uses>
Locate
case1
Book
Actors & Use Cases
Gives
money
ATM Customer
Data Acquisition System
§ Measures Voltage
§ Measure Temp
§ Data – Initial Analysis done and sent for further processing
§ Analysis result sent back
UML
Measure
Volts
Data
Analysis
Measure Data
Actor0 Temp Processing
Textual Description – Measure Volts
User
Select measure volts mode
Select measurement range
System
If range specified
Configure to specified gain
Make Measurement
If in range – display results
If exceed range – display largest value & flash display
If auto range
Configure to midrange gain
Make Measurements
If In range- display result
If above/below range – adjust gain repeat measurement
Textual Description
§ Normal Activity
§ Exceptional Conditions
Class Diagram
§ Help Indentify/Formulate – Modules
§ Describe object/modules
§ Relationship between objects
§ Public i/f to object
§ Properties – op that instances of the object can perform
§ Indentifies any constraints the appln imposes on these op
Class Diagram
Object Name
- Properties
+ Operations()
Class Relationships
§ Parent – Child/ Inheritance/Generalization
§ Interface
§ Wrapper around one piece of functionality
§ Allows to present diff set of capabilities to public view
§ Containment
§ One object made up of several others
§ Whole part relationship
§ Aggregation
Owned module may be used out of aggregation
§ Composition
Ownership is very strong
Inheritance/Generalization
Driver
+port number: unsigned char
+buffer address: int
+status: unsigned char
+ Read(): Boolean
+Write(): Boolean
Serial Parallel
+ Read(): Boolean + Read(): Boolean

+Write(): Boolean +Write(): Boolean
Interface
Voltmeter
<<interface>>
Measure Pressure
+ Measure(): Float
+ Measure(): Float
-Covert (): Float
Containment -Aggregation
Statistical Analysis 0-n Algorithms Algorithm
+buffer: int
Containment -Composition
Schedule Interval
1-n
Dynamic Modeling
§ Recognizing inter-module interaction
§ Ensuring proper order of task execution
§ Understanding what activities can be done in parallel
§ Schedule alternate paths of execution
§ Indentify tasks that are active and what are not
Interaction Diagram
§Interaction among tasks – messages
§ Events
§ Rendezvous
§ Message
§Receipt of a message results in action
§Actions
§ Call & Return
§ Create & Destroy
§ Send
Call & Return
:Task i :Task j
action()
return()
Create & Destroy
:Task i :Task j
<<create>>
<<destroy>>
Send
:Task i :Task j
action()
Sequence Diagrams
§ Objects
§ Lifeline
§ Focus of Control
§ Messages
Sequence Diagram – Time Interval
Measurement
Measur Get Exec
Convert Display
e Task Attrib Meas
measure ()
get range ()
range()
get edge ()
edge()
send data ()
result()
send data ()
formatted data()
Display data ()
ok()
done()
Fork& Join
Parent
Child 0
Child 2
Child 1
Parent
Branch & Merge
Activity 0
When:[guard codn]
Activity 1
Activity 2
Activity 3
Activity 4
Activity Diagram
Activity 0
Activity 1
When:[guard codn]
Activity 5 Activity 3
Activity 2
Activity 4
Activity 6
Activity 7
Activity 8
Measure
Time
Get range
Get edge
Open meas
window
Close meas Update
window Display
Read count
Min value convert Max value
Flash Flash
State Chart Diagrams
Same as state diagrams with some extensions
Transitions
event
State2 State7
State2
State2 State7
Guard Condition
State2 State9
Event [guard]
State10
Composite States
Substate0 Substate1
Event [guard]
Substate 3 Substate 2
astate
Concurrent States
astate
State8 State9
State10 State11
Control & Data Graphs
Program Model - CDFG
Data Operations
Control Operations
a b c d e
w=a+b
x= a–c
+ + -
y= x+d x1
x= a+c +
z= y+e
x2 w y
Single assignment form
w = a+b
x1 = a – c +
y = x1 + d
x2 = a + c
z
z = y+e
if (codn1)
basic_block1();
else
basic_block2(); T
cond1 basic_block1()
basic_block3();
switch(test1){
case c1:basic_block4();break; F
case c2:basic_block5();break; basic_block2()
case c3:basic_block6();break;
}
basic_block3()
test1
basic_block5() basic_block6() basic_block7()

UML Example
System design
Digital Counter
System Description
§ Measure
§ Frequency
§ Period
§ Time Interval
§ Events
§ Measurement Range
§ 3 for signals
§ 2 for events
§ Remote Operation support should be provided

for future expansion
§ Can work on battery/power-line
System Inputs
§ Frequency
§ High 50.000 MHz
§ Mid 50.000KHz
§ Low 100.000Hz
§ Period
§ High 1.0000ms
§ Mid 10.000ms
§ Low 1.000 sec
System Inputs
§Time Interval
§ High 1.0000ms
§ Mid 10.00ms
§ Low 1.000sec
§Events
§ Fast 200 events/min
§ Slow 2000 events/hr
§All inputs
§ Digital
§ 0-4.5 V DC
Resolutions
§ Frequency
§ 1 MHz
§ 1 KHz
§ 10 Hz
§ Period/Time Interval
§ ± 0.001ms
§ ± 0.01ms
§ ± 0.001s
User Interface
MHz/ ms/min
KHz Start
Hz/sec/hr
Freq Period Intervl Events

Fr Range Stop
Pwr Reset
Use Case – Local Mode
Measure
Freq
Measure
Period
Measure
Interval
Count
User Events
Reset
Use Case – Remote Mode
Measure
Freq
Measure
Period
Measure
Interval
Count
User Events
Reset
Measure Frequency
§ Frequency measured continuously
§ Start Trigger
§ Exceeds allowable maximum – flash maximum
§ Exceeds allowable minimum – display ‘0’ and flash
§ Within bounds – display
Use Case – Measure Freq
Select
Mode
Select
Range
Select
User Trigger
Textual Description – Measure Freq
User
Select measure freq mode
Select measurement range
Select measurement Trigger
System
Configure to specified range and trigger
Make Measurement
If in range – display results
If below range – display zero value & flash display
Measure Period
§ Period measured continuously
§ Start Trigger
Use Case – Measure Period
Select
Mode
Select
Range
Select
User Trigger
Measure Interval
§ Interval measured within a window
§ Start Trigger
§ Stop Trigger
Use Case – Measure Interval
Select
Mode
Select
Range
Select Start
User Trigger
Select Stop
Trigger
Count Events
§ Event done continuously
§ Start Trigger
Use Case – Count Events
Select
Mode
Select
Range
Select Edge
User
Other Specifications
§ Automatic Power Line Voltage Regulation
§ Temperature Staability 0 -50C
§ < 6 x10-6
§ Aging Rate
§ 90 day
§ < 3x10-8
§ 6 month
§ <6 x10-7
§ 1 year
§ <25 x10-6
Other Specifications
Safety : IEC-1010
MTBF : 10,000 hrs
Measure Frequency
Get range
Get edge
Open meas
window
Close meas
window Update Display
Read count
Flash Flash
Measure Period
Get range
Get edge
Open meas window
Close meas window Update Display
Read count
Flash Flash
Measure Interval
Get range
Get start edge
Open meas window
Get stop edge

Update Display
Close meas window
Read count
Min value Max value

convert
Flash Flash
Compilers,
Assemblers &
Debuggers
Embedded Code
Rich functionality
Run at the required rate
Fit within a certain amount of memory
Meet power consumption requirements
Robust, Reliable and Maintainable
Source
code
Pre-
processor Compiler Assembler
Object
code
Linker
.s19/ hex
Loader
Preprocessor
Builds Temporary File – Translation unit
Header File - # include
# define, #ndef
Unresolved external references
Compiler
Cross compiler
Important to understand how a high-level language program®

instructions
Control inst seq that handle ints
Control placement of data and insts in mem
Applns are performance sensitive
Compilation = translation + optimization

Compiler
Statement Translation
a*b + 5*(c - d)
Flow Graph for Statement
Translation
a b c d
1 - 2
* w 5
x
* 3
y
4 +
z
Register Allocation
w=a+b
x= c+w
y= c+d
Registers – not sufficient -spill

a
b
c
d
w
x
y
1 2 3
w=a+b
x= c+w
y= c+d
Color Graphs
Smallest no. of colors to represent all variables
a b
w
d
x
c
y
w=a+b
x= c+w
y= c+d
Compiler
Optimization Tech
Dead Code Elimination
Procedure Inlining
Expression Simplification
a * b + a*c = a*(b+c)
Instruction Selection
Scheduling
Choose the order in which instructions

are executed
Scheduling problems Þ Resource Table
Instructions can be scheduled to avoid
pipeline bubbles
Pipeline bubbles Þ Software Pipelining
Loop Transformations
Loop Unrolling
Loop Fusion
Loop Distribution
Array Padding
for (j = 0; j<M; j++)
for (i =0; i<N; i++)
a[j][i] = a[j][i]+ b[j][i]*c
Compiler support
Inst i Inst i+1 Latency
FP ALU op FP ALU op 3
FP ALU op Store 2
Load double FP ALU op 1
Load double Store double 0
Example Code
for (i = 1000; i > 0; i = i-1) Loop: L.D F0,0(R1)
x[i] = x[i] + s; ADD.D F4,F0,F2
S.D F4, 0(R1)
DADDUI R1,R1,# -8
BNE R1,R2,Loop
Delays
Loop: L.D F0,0(R1) 1
stall 2
ADD.D F4,F0,F2 3
stall 4
stall 5
S.D F4,0(R1) 6
DADDUI R1,R1,#-8 7
stall 8
BNE R1,R2,Loop 9
stall 10
Scheduled Program
Clock cycle issued
loop: L.D F0, 0(R1) 1
Stall 2
ADD.D F4,F0,F2 3
Stall 4
Stall 5
S.D F4, 0(R1) 6 OLD
DADDUI R1,R1,#-8 7
Stall 8
BNE R1,R2, loop 9
Stall 10
Clock cycle issued

loop: L.D F0, 0(R1) 1
DADDUI R1,R1,#-8 2
ADD.D F4,F0,F2 3 NEW
2-cycle Stall 4
latency BNE R1,R2, loop 5
S.D F4, 8(R1) 6
Compiler Tasks
Clock cycle issued
loop: L.D F0, 0(R1) 1
DADDUI R1,R1,#-8 2
ADD.D F4,F0,F2 3
Stall 4
BNE R1,R2, loop 5
S.D F4, 8(R1) 6
OK to reorder DADDUI and ADD.D

OK to reorder S.D and BNE
OK to reorder DADDUI and S.D, but requires
0(R1) à 8(R1)
Loop Overhead
Clock cycle issued
loop: L.D F0, 0(R1) 1
DADDUI R1,R1,#-8 2
ADD.D F4,F0,F2 3
Stall 4
BNE R1,R2, loop 5
S.D F4, 8(R1) 6
6 is the minimum due to dependencies & pipeline latencies

Actual work of the loop is just 3 instructions:
¡ L.D, ADD.D, S.D
Other instructions are loop overhead:
¡ DADDUI, BNE
Loop unrolling
Loop: L.D F0,0(R1)
ADD.D F4,F0,F2
S.D F4,0(R1)
L.D F0,-8(R1)
ADD.D F4,F0,F2
S.D F4,-8(R1)
L.D F0,-16(R1)
ADD.D F4,F0,F2
S.D F4,-16(R1)
L.D F0,-24(R1)
ADD.D F4,F0,F2
S.D F4,-24(R1)
DADDUI R1,R1,#-32
BNE R1,R2,Loop
Loop unrolling
Loop: L.D F0,0(R1)
L.D F6,-8(R1)
L.D F10,-16(R1)
L.D F14,-24(R1)
ADD.D F4,F0,F2
ADD.D F8,F6,F2
ADD.D F12,F10,F2
ADD.D F16,F14,F2
S.D F4,0(R1)
S.D F8,-8(R1)
DADDUI R1,R1,#-32
S.D F12,16(R1)
BNE R1,R2,Loop
S.D F16,8(R1)
Compiler Tasks for
Unrolled Scheduled Version
OK to move S.D after DADDUI and BNE if S.D offset is adjusted

Determine that unrolling is useful because loop iterations are
independent
Use different registers to avoid name hazards
Eliminate extra test and branch instructions and adjust iteration
code
OK to move L.D and S.D instructions in unrolled code (requires
analyzing memory addresses)
Keep all the real dependencies, but reorder to avoid stalls
Compilers
Programs need not always be compiled

then executed
On –the fly translation
Interpreters
JIT
Interpreters- translates program
statements one at a time
JIT comes in between Interpreters and
compilers
Assembler
LABEL1 1000
Creates Symbol Table LABEL2 1008
Program Location Counter (PLC) LABEL3 1010
ORG $1000
PLC -1000
LABEL1 ADR r4,c
PLC -1004 LDR r0,[r4]
LABEL2 ADR r4,b
LDR r1,[r4]
LABEL3 SUB r0,r0,r1
Linker
Allows program to be stitched together from smaller pieces
Lib - preassembled
Labels
defined and used in same file
defined and used in different files
Entry Point
External Reference
Proceeds in two steps
absolute address of start of each obj file
specified by user
merges all symbol tables relative address – absolute address
DLL
Makefiles
Files to compile
Standard and custom lib
Name of executable
Whether debug info
hw:hw.o
gcc hw.o –o hw
hw.o:hw.c
gcc –c hw.c
Debug & Release Builds
Debugging tool
Larger Executable
Tasks & Task Management
RL8.1.1 Embedded System Design ©

K.R.Anupama & Meetha.V.Shenoy 1
Embedded program – collection of Firmware Modules
Firmware Module executes – Process/Task
Control ensures that task execution satisfies –set of

timing constraints - RT
RL8.1.1 Embedded System Design © K.R.Anupama & Meetha.V.Shenoy 2

Multi –tasking/ Concurrent Processing
Tasks
¡ Exchange/share data
¡ Synchronization
¡ Sharing resources (processor)
¡ Schedule

Process created – allocated resources by OS
¡ Process stack
¡ Registers including PC
¡ I/O ports
¡ Ntk connections
¡ File Descriptors
Resources are not generally shared

Current Value of PC, Present Value of
data in memory/ registers

Duration btwn when task enters to
termination

Scheduling Scheduling
Execution Execution
Threads within a Resource Ownership
process share
resources

Threads are easier to create than processes since they
don't require a separate address space
Multithreading requires careful programming since
threads share data structures that should only be
modified by one thread at a time
Unlike threads- processes don't share the same
address space
Threads are considered lightweight because they use
far less resources than processes
Processes are independent of each other- Threads
share the same address space are interdependent, so
caution must be taken so that different threads don't
step on each other.
A process can consist of multiple threads

Single process – Single process –
single thread multi thread
Multiple process – Multiple process –

single thread multi thread
9
RL8.1.1 Embedded System Design © K.R.Anupama & Meetha.V.Shenoy
Interleaved
Blocked
Simultaneous

Address space allocated to a single process is
limited
Thread/process – access memory out of
range –stopped
Privilege levels
Processor Modes of operation
Access violation – exception
Process – spawn child process – resources ??

Factors
¡ Info
¡ Place/places – source
¢ Identifiers – named variables, pointer variables
¡ Control & sync of actions – movement of info
¢ Shared variables
¢ Messages
¢ Buses

Global Variables
Adv – Backup
Disadv – two tasks may try to modify simultaneously

Shared Buffer
Producer T0 T1 Consumer
Bool Full()
Bool Empty()

Ping pong Buffer /Shared Double
B0
T0 T1
B1
16
Ring Buffers T0 - head
T1- Tail

MailBox
T0 T1
post pend

IPC
How is link established?
Can link be associated with multiple tasks?
How many links between a pair of tasks
What is link capacity, and are there any
buffers?
What is message size?
Links unidirectional – bidirectional?

T0 Network T1
send receive
B0 B1

Meetha.V.Shenoy 20
MailBox
Network Network
T0 T1
send recieve
B0 B1

Zerocapacity – rendezvous/ Idle IRQ
Bounded Capacity
Unbounded Capacity – Continous RQ

Foreground Background
¡ Process that interact with user or other I/O
devices
¡ Remainder

Schedules
Dispatch
Ensure commn & Syncg

TCB /PCB
The identifier of the process
Register values for the process - program counter and stack
pointer values for the process.
The address space for the process
Priority
Process accounting information, such as when the process was
last run, how much CPU time it has accumulated, etc.
Pointer to the next PCB
I/O Information

Static
¡ Usually used in Embedded Systems
Dynamic

Context – important info regd task state
When task is stopped/blocked/pre-empted –

context must be saved
On return – context is restored

Duplicate Hardware
TCB
Stacks
¡ Stack Frame/Activation Record

Task Synchronization
M8: Embedded Software – Tasks & Task
Management
• Share Logical Address space

Cooperating Tasks
• Concurrent access to common
data T1
T0
• Data Inconsistency
• Aberrant/unexpected behavior
3
Co-operating Tasks
Producer Consumer
while(1) while(1)
if not full if not empty
add item get item
inc count dec count
else else
wait for space wait for item
endwhile endwhile
4
Problem ??
• Simultaneous access of count
• 3 different values at any instant of time
• Critical Section – Mutually exclusive access
5
Non-CS
Synchronization
Entry Section
• Mutually exclusive Critical Section
• Condition
Exit Section
Non-CS
6
Requirements – Soln
• Mutual exclusion
• Deadlock
• Bounded Waiting
7
Soln 1: Flags
• Each Task has a flag
• Atomic procedure await
await (codn)
{
statements
} variable
8
Flags
Producer Consumer
While(1) While(1)
if not full if not empty
add item get item
await(!T1Flag) {T0 await(!T0Flag) {T1
Flag= true} Flag = true}
inc count dec count
T0Flag = False T1Flag = False
else else
wait for space wait for item
endwhile endwhile
9
Soln 2 Token Passing

• Similar to token passing protocols
10
Problems
• Task process not wanting to co-operate can hold
token forever
• Task/Process with token crashes
• Token corrupted/lost
• Task with token terminates without giving up token
• Task added/removed
11
Solution
• Add Task for token management
• Every time a task enters/leaves – registers with
token management
• Disadvantages
▫ No. of tasks increase
▫ IPC reqd for new task
12
Soln 3 – Manage interrupts

• Disallow interrupts
▫ Entry sec – disable int
▫ CS
▫ Exit sec – enable int
• Disadv
▫ Loops in CS – too long
• Soln
▫ Disable ints below a certain level
▫ Works for single processing environment
13
Soln 4: Semaphores
• Semaphores: Introduced by Dijkstra in 1960s
• Semaphores have two purposes

▫ Mutex: Ensure threads don’t access critical section at
same time
▫ Scheduling constraints: Ensure threads execute in
specific order
14
Semaphores
• Variables that can be accessed only thro’ atomic op
• wait – p(s)
• signal – v(s)
• p(s) – test & set
• v(s) - reset
15
Semaphores – Critical resources

Producer Consumer
{ {
…. ….
wait(s) wait(s)
critical section critical section
signal(s) signal(s)
…. ….
} }
16
Semaphores
wait(s) signal(s)
{ {
while(s); s = false;
s = true; }
}
17
Spin Lock & Busy Waiting

• Lock on resource – spin lock
• Waits for Lock to open – busy waiting
• Binary Semaphore - mutex
18
Semaphores – Counting
• Takes value 0 – N-1
• List of associated processes
• Process executes wait instruction – semaphore not available
• Task blocks itself
▫ Block – waiting queue of semaphore (task waiting)
▫ Control Transferred to scheduler
• Restarted when signal op is executed
▫ Wake –up
▫ Task in ready state – ready queue
19
Semaphores
wait(s) signal(s)
{ {
s = s+1; s = s -1;
if(s >1) if (s>1)
{ {
add process to waiting remove process from
queue; waiting queue;
block; wakeup(p);
} }
} }
20
Semaphore implementation
typedef struct {
int value;
queue tlist;
} semaphore;
21
How to use semaphores – example 1

• Mars Rover – data management of an extensible digital imaging
system
• Data collected from cameras, IR scans, atmospheric analysis,
topographic mapping
• Data collected into a set of buffers – uploaded via satellite to earth
22
Buffer 0
Buffer 1
Buffer n-2
Buffer n-1
23
Requirements
• Imaging System – Producer
• Satellite System – Consumer
• Count no. of free/full buffers
• Controlled access to individual buffers for read/write
24
Algorithm - Producer
• Producer checks if any buffer is empty
• If empty – waits for exclusive access to buffer pool.
• Access gained – data added – then exit
25
Algorithm - Consumer
• Consumer checks whether any buffer has data
available
• If yes waits for exclusive access
• Buffer pool – available consumer gets data and
exits
26
Semaphores
• mutex (1)
• empty (n-1)
• full (0)
27
Camera Satellite
while(1) while(1)
…. wait(full);
produce an item wait(mutex);
…. ….
wait(empty); remove item from
wait(mutex); buffer;
…. ….
add item to buffer; signal(mutex);
…. signal(empty);
signal(mutex); ….
signal(full); consume item
…. ….
endwhile
endwhile
28
Semaphores
wait(empty) signal(empty)
sem_wait (semaphore *S) sem_signal (semaphore *S) {
{ S->value++;
S->value--; if (S->value <= 0) {
if (S->value < 0) { remove thread t from
add this process to S->tlist;
S->tlist;
wakeup(t);
block();
}
}
}
29
Classic Synch Problem

30
Modified Rover
• Imaging System can gather data simultaneously
• Data can be uploaded using several links
• Data object shared by several concurrent processes
▫ Readers – Writers
Readers access data simultaneously
Writer and reader try simultaneously
▫ Reader – Writer Problem
• No Reader waits unless a writer is accessing the buffer
31
Semaphores
• wrtSem (1)
• mutex (1)
• numReaders (0)
32
writer Reader
wait(wrtSem); while(1)
…. wait(mutex);
numReaders++;
perform writing;
if(numReaders==1)
…. wait(wrtSem);
signal(wrtSem); endif
signal(mutex);
….
Perform reading;
…
wait(mutex);
numReaders--;
if(numReaders==0)
signal(wrtSem);
endif
signal(mutex);
endwhile
33
Soln 5: Monitors
• Monitors provide control by allowing only one process to access a
critical resource at a time
▫ A class/module/package
▫ Contains procedures and data
Data – object state
• Data abstraction mechanism that encapsulates a repsn of an
abstract object
34
An Abstract Monitor
monitor monName
{
… some local declarations
… initialize local data
procedure name(…arguments)
… other procedures
permanent variables (static)
}
35
Monitor Rules
• Only procedure names are visible – Public interface
• Permanent variables can be changed only thro’ one of the
procedures
• Any process can access any monitor procedure at any time
• Only one process may enter a monitor procedure
▫ Simultaneous access of two different proc
▫ Two invocations of same proc
• No process may directly access a monitor’s local variables
• A monitor may only access it’s local variables
36
Things Needed to Enforce Monitor
• “wait” operation
▫ Forces running process to sleep
• “signal” operation
▫ Wakes up a sleeping process
• Condition
▫ Synchronisation
37
Bounded Buffer Problem

• Codn variables
▫ Not Empty
Tracks empty buffers -0
Signaled when buffer count >0
▫ NotFull
Tracks full buffers – 0
Signaled when count < n-1
• Procedures
▫ put(data)
▫ get(data)
• Protected Entity
▫ bufferPool
38
Monitor - implementation
Monitor boundBuffer
bufferPool;
count = 0;
cond notEmpty;
cond not Full;
39
put(anItem)
{
while(count==n)wait(notFull);
put an item into buffer;
signal(notEmpty);
}
40
get(anItem)
{
while(count==0)wait(notEmpty);
get an item from buffer;
signal(notFull);
}
41
Producer Consumer
while(1) while(1)
…. ….
produce an item boundBuffer.get(anItem)
…. ….
boundBuffer.put(anItem) produce an item
…. ….
endwhile endwhile
42
Problems
• Starvation
▫ Block one process from running – while a
processor is waiting – other process are added and
removed in LIFO
• Deadlock
RTS
M8: Embedded Software - Tasks, Task Management & RTS

Timing Characteristics of Embedded System
} Embedded computing systems do more than one thing
} Environment causes Mode changes ® Embedded System to
behave differently
} May perform logically different tasks – different rates
} Data may arrive at different rates
} Asynchronous input
2 RL8.3.1 Embedded System Design © K.R.Anupama & Meetha.V.Shenoy

RTOS
} Allocate Resources of Computing System – programs that request them
} Scarcest Resource – CPU
} Schedule process
} OS considers the process to be in any one of 3 states
} Waiting
} Ready
} Executing
} Common way to select a process - priority

RTOS
Executing
needs data
gets data
& CPU
Pre-empted ready
Chosen to run
Rxd data
Ready Waiting
needs data

Scheduling – Priority Driven
Process Priority Exec Ready
P1 1 10 15
P2 2 30 0
P3 3 20 18
P2 P1 P2 P3
0 10 20 30 40 50 60
Timing Requirements of Processes

Initiation Time – Process goes from Wait state Þ Ready state
Deadline

Aperiodic Process
P1
Deadline
Initiating event
Periodic Process
P1
period
Deadline
Initiating event
Periodic Process
P1
period
Deadline
Initiating event
Periodic Process
P1
period
Deadline
Initiating event

Scheduling
7 RL8.3.1 Embedded System Design ©

K.R.Anupama & Meetha.V.Shenoy
Independent Periodic Tasks
Rate Monotonic Scheme (RMS)
} Fixed priority
} Preemptive Scheduling
} Priorities are assigned according to the periods
} Shorter the period higher is the priority
} Results show that as long as processor utilization of a task set
is less than 69 % - task set is schedulable using RMS
} Bound is obtained using the formula
Si=1n ci/pi £ n(21/n -1)

2Þ ¥ utilization -0.69
Simple periodic tasks – 100 %

Independent Periodic/Aperiodic Tasks
Earliest Deadline First (EDF)
} Dynamic priority
} Priorities are assigned according to the deadline
} Earlier the deadline higher is the priority
} Results show that as long as processor utilization of a task set
is lesser than 100 % - task set is schedulable using EDF
} Bound is obtained using the formula
Si=1n ci/pi £ 1
utilization – 100 %

Independent Periodic/Aperiodic Tasks
Least Laxity First (LLF)
} Dynamic priority
} Priorities are assigned according to the laxity of task
} Laxity li =(di – ci’ – ti)
} Smaller the laxity higher is the priority
} More preemptions
} May result in Thrashing

Task Comp period
time
T1 2 6
T2 2 8
T3 3 12
11 RL8.3.1 Embedded System Design ©

K.R.Anupama & Meetha.V.Shenoy
12
Resource Reclaiming
} Correctness
} Inexpensiveness
} Bounded Complexity
} Effectiveness
} Cost of rescheduling < Time reclaimed
} Cost of scheduling must be lesser than 10 % of the worst case computation
time of the tasks

Resource Reclaiming
} Resource reclaiming in a uni-processing environment with independent
tasks – straight forward
} Resource reclaiming in such environments – greedy in nature
} Work conserving/ band width conserving
} Resource Reclaiming will never leave a processor idle if there is a
dispatchable task

Resource Reclaiming
T1 =( 0,10,22)
T2 = (0,6,25)
T3 = (10,8,26)
T4 = (8,10,35)
T1 T2 T3 T4
0 10 16 24 34
T1 T2 T3 T4
0 5 10 16 20 24 34
T1 T2 T3 T4
0 5 11 15 25

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M1 – Introduction to Embedded Systems

§ Dedicated computer/processor based system built for

Embedded System Design - RL1.1.1 © K.R.Anupama & Meetha.V.Shenoy 2

Embedded System Design - RL1.1.1 © K.R.Anupama & Meetha.V.Shenoy 3

Embedded System Design - RL1.1.1 © K.R.Anupama & Meetha.V.Shenoy 4

Embedded System Design - RL1.1.1 © K.R.Anupama & Meetha.V.Shenoy 5

§ Testability & Debug-ability

Embedded System Design - RL1.1.1 © K.R.Anupama & Meetha.V.Shenoy 6

Hardware Design Software Design

Hardware Implementation Software Implementation

Hardware Testing Software Testing

Operation & Maintenance

Embedded System Design - RL1.1.2 © K.R.Anupama & Meetha.V.Shenoy 2

Embedded System Design - RL1.1.2 © K.R.Anupama & Meetha.V.Shenoy 3

Embedded System Design - RL1.1.2 © K.R.Anupama & Meetha.V.Shenoy 4

Embedded System Design - RL1.1.2 © K.R.Anupama & Meetha.V.Shenoy 5

Embedded System Design - RL1.1.2 © K.R.Anupama & Meetha.V.Shenoy 6

Embedded System Design - RL1.1.2 © K.R.Anupama & Meetha.V.Shenoy 7

Sensors ADC CPU DAC Actuators

Diagnostic Human I/f

Sensors ADC CPU DAC Actuators

Diagnostic Human I/f

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 3

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 4

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 6

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 7

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 8

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 9

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 10

IF1 ID1 IE1

IF2 ID2 IE2

IF3 ID3 IE3

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 12

Embedded System Design - RL1.2.1 © K.R.Anupama & Meetha.V.Shenoy 13

§ Used for complex real –time functions

Embedded System Design - RL1.2.2 © K.R.Anupama & Meetha.V.Shenoy 2

Embedded System Design - RL1.2.2 © K.R.Anupama & Meetha.V.Shenoy 3

Embedded System Design - RL1.2.2 © K.R.Anupama & Meetha.V.Shenoy 4

§ An atomic operation must be performed entirely or not performed

Embedded System Design - RL1.2.2 © K.R.Anupama & Meetha.V.Shenoy 5

Embedded System Design - RL1.2.2 © K.R.Anupama & Meetha.V.Shenoy 6

§ Faster than s/w solution using GPP

§ ASSP is used as an additional processing unit – instead of

Embedded System Design - RL1.2.2 © K.R.Anupama & Meetha.V.Shenoy 7

§ Multiple processors are used when a single processor cannot

Embedded System Design - RL1.2.2 © K.R.Anupama & Meetha.V.Shenoy 8

§ Processing speed in MIPS

§ 1 MIPS = 1757 Dhrystones – VAX 11/780

Embedded System Design - RL1.2.2 © K.R.Anupama & Meetha.V.Shenoy 9

Sensors ADC CPU DAC Actuators

Diagnostic Human I/f

Embedded System Design - RL1.2.3 © K.R.Anupama & Meetha.V.Shenoy 3

Embedded System Design - RL1.2.3 © K.R.Anupama & Meetha.V.Shenoy 4

Embedded System Design - RL1.2.3 © K.R.Anupama & Meetha.V.Shenoy 5

RAM Hybrid ROM

EEPROM NVRAM Flash

SRAM DRAM EPROM PROM

Embedded System Design - RL1.2.3 © K.R.Anupama & Meetha.V.Shenoy 6

Embedded System Design - RL1.2.3 © K.R.Anupama & Meetha.V.Shenoy 7

§ Program – segment – main & overlay

Embedded System Design - RL1.2.3 © K.R.Anupama & Meetha.V.Shenoy 8

Embedded System Design - RL1.2.3 © K.R.Anupama & Meetha.V.Shenoy 9

§ Signature Analysis - ROM

Embedded System Design - RL1.2.3 © K.R.Anupama & Meetha.V.Shenoy 10