Department of Electrical Engineering

Riphah College of Science & Technology

Faculty of Engineering & Applied Sciences
Riphah International University, Lahore

Program: B.Sc. Electrical Engineering Semester: III

Subject EE-203 Digital Logical Design Date: ……………….

Experiment 12: Introduction to VHDL and write VHDL code for Basic
Gates.

Student Name: ……………………………………………………………

Lab Performance

No. Title Marks Obtained

Marks
1 Ability to conduct experiment 5
2 Data Analysis & Interpretation 5
3 Total 10

Lab Reports

No. Title Marks Obtained

Marks
1 Calculations and Data Presentation 5
2 Total 5

Remarks (if any): ………………………………….

Name & Signature of faculty: …………………………………