Department of Electrical Engineering

Riphah College of Science & Technology

Faculty of Engineering & Applied Sciences
Riphah International University, Lahore

Program: B.Sc. Electrical Engineering Semester: III

Subject EE-203 Digital Logical Design Date: ……………….

Experiment 11: To implement JK flip flop circuits.

Student Name: ……………………………………………………………

Lab Performance

No. Title Marks Obtained

Marks
1 Ability to conduct experiment 5
2 Data Analysis & Interpretation 5
3 Total 10

Lab Reports

No. Title Marks Obtained

Marks
1 Calculations and Data Presentation 5
2 Total 5

Remarks (if any): ………………………………….

Name & Signature of faculty: …………………………………

 Experiment11 (a)

1 Objective
Implementation of JK Flip Flop

2 Purpose
Having completed this experiment you will be able to:

• To understand the function of JK Flip Flop.

• To Construct JK Flip Flop by using NAND gate.

3 Apparatus
• Logic Trainer
• 74LS00 (NAND Gate)
• 74LS02 (NOR Gate)

• Power Supply
• Connecting wires

4 Theory
The J and K inputs of the J-K flip-flop are synchronous inputs because data
on these inputs are transferred to the flip-flops output only on the triggering
edge of the clock pulse. When J is HIGH and K is LOW, the Q output goes
HIGH on the triggering edge of the clock pulse, and the flip-flop is SET. When
J is LOW and K is HIGH, the Q output goes LOW on the triggering edge of
the clock pulse, and the flip-flop is RESET. When both J and K are LOW, the
output does not change from its prior state. When J and K are both HIGH,
the flip-flop changes state. This called the toggle mode.

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4.1 Procedure
• Connect the Logic Trainer to 220V AC power supply.
• Turn On the trainer and verify its DC voltage, it should be +5 volts
exactly.
• Install the ICs 7400 and 7402 on the trainers breadboard.
• Connect the +VCC (pin 14) and Ground (pin 7) pins of the respective IC
to +5V and Ground supply of the trainer board.
• Make the appropriate circuit connections as shown in Fig. 1. Use the
trainers logic switches to provide 0 and 1 at the input and use the trainers
LEDs to display the outputs. And record its result in table 1.

4.2 Schematic diagrams for JK Flip Flop

Figure 1: JK Flip Flop by using NAND Gate.

4.3 Experimental Results

Table 1: Truth Table of JK Flip Flop by using NAND Gate.

J K CLK Q Q̄ Mode of Operation
0 0
0 1
1 0
1 1

4.3.1 In Case of Trouble

• Check the power supply.
• Check the Vcc and GND at pin number 14 and 7 of the IC under test.
• Check all the wire connections and remove the breaks.
• Check the IC under test using truth table.

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5 Conclusion
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