Prajit Nandi

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TCAD.2015.2474379, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper Control Number: 1
Date: July 24, 2015
Dear Editor,
Enclosed is a revised manuscript, entitled "A Novel Approach to Design SAR-ADC: Design Partitioning Method” to be
considered for publication in the “IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems". All
the modifications are highlighted by Yellow background.
Author Details:
1. Prajit Nandi
Design Engineering Director, Sankalp Analog Solutions,
Sankalp Semiconductor Pvt. Ltd., DLF II IT Park, Block 2F, AA-2, New Town, Kolkata, West Bengal-700156, India.
E-mail: prajit_n@sankalpsemi.com
2. Hirak Talukdar
Design Engineer, Sankalp Analog Solutions,
E-mail: hirak_t@sankalpsemi.com
3. Dhiraj Kumar
Technical Lead, Sankalp Analog Solutions,
E-mail: dhiraj_k@sankalpsemi.com
4. Ashvin Kumar G. Katakwar

Team Lead, Sankalp Analog Solutions,
E-mail: ashvin_k@sankalpsemi.com
We, hereby certify that we are the sole authors of this work and that no part of this work has been published or submitted for
publication in any other journal or conference. Information derived from the published and unpublished work of others has been
acknowledged in the text and a list of references is given in the bibliography.
Sincerely,
Prajit Nandi
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
A Novel Approach to Design SAR-ADC:

Design Partitioning Method
Prajit Nandi1, Hirak Talukdar2, Dhiraj Kumar3, Ashvin Kumar G. Katakwar4
Sankalp Analog Solutions, Sankalp Semiconductor Private Limited
Email: 1prajit_n@sankalpsemi.com, 2hirak_t@sankalpsemi.com
Abstract— This paper presents a Successive-Approximation-

Register Analog to Digital Converter (SAR-ADC) design
optimization platform. A novel ADC modelling approach,
Design-Partitioning-Method (DPM) is used in the proposed
platform. It uses Look-Up-Tables (LUT) along with conventional
behavioral modelling technique, which captures the design
parameters and process non-idealities. An individualistic as well
as collective study of the impact of these parameters and non-
idealities on the performance of SAR-ADC has been carried out.
Proposed platform aims to achieve a perfect balance between
architecture evaluation time (3.2% with respect to spice-netlist)
and accuracy in performance estimation (98% with respect to
spice-netlist). A comparative study between spice-model,
structural-modelling and proposed modelling scheme (DPM) is
reported here. As a case study 14bit, 4.2MSPS SAR-ADC
architecture is evaluated, designed and verified.
Fig.1. Modelling optimization aspects
Index Terms— Successive-Approximation-Register Analog to
Digital Convertors, Design Partitioning Method, Verilog-A,
Look-Up-Table, Integrated Circuit Modelling, Architecture
combined performance can be observed. In DPM, sampling-
Evaluation switch and DAC architecture is completely flexible unlike the
previous design automation work. A MATLAB-based
I. INTRODUCTION numerical tool to assist the design of charge redistribution
DACs in SAR-ADCs has been presented recently in another
reported work [12]. The overall SAR-ADC performance
I N recent times the time-to-market has been one of the most
important motivating factor in an IC design cycle, which
makes it very crucial to predict the overall performance and
depends on combined non-idealities of Capacitive-DAC and
Sample-Hold network. Unlike DPM, the reported tool tries to
optimize the Capacitive-DAC independently. Though the
avoid possible cock-pit errors at the early stages of analog effects of capacitive-mismatch and parasitic-capacitance are
circuit design. A transistor level implementation and analysis captured, voltage-dependency of unit-capacitors and switch-
has been found highly time consuming [1] as well as limiting resistances are not considered in the MATLAB model. As
to perform yield analysis on large systems like data- DPM works with spice device models, it is more compatible
converters. Hence, performing a Design-for-Manufacturability with analog design environment, which results in significantly
(DFM) analysis becomes cumbersome. Behavioral models [2- lower design cycle time.
10] of the desired mixed signal circuits have been proven to be
the better solution to perform system-level analysis. In the proposed modelling scheme along with conventional
behavioral modelling, Look-Up-Tables are generated for
Recently a SAR-ADC design automation work [11] based different modules to develop a faster and more accurate SAR-
on Knowledge-Based and Simulation-Based approach has ADC design methodology. Details of Look-Up-Table
been reported. In the work, all the blocks are designed generation methodology are discussed in the following
independently based on automated design-algorithms for sections. It helps in optimal-designing and analyzing the SAR-
predefined block-structures. It focusses on ~10bit resolution ADC with due consideration to the process non-idealities.
SAR-ADC design where power-optimization is the main Thus, it reduces design cycle-time by avoiding unforced
concern. Unlike bottom-up approach of the previous work, performance degradation after top-level integration. In the
DPM mixes the top-down and bottom-up design approaches. conventional structural modelling all the blocks are
Block-level simulation data can be examined independently behaviorally modelled [5-8] and organized as they are actually
through block-level test-benches as well as those data can be connected in the schematic. In the proposed modelling scheme
feed at top-level test-benches through LUTs and their the whole SAR-ADC is partitioned into different blocks
according to their functionality rather than their actual used as S/H circuit in SAR-ADC. Bottom-plate-sampling
structure. Thus, it can be viewed as a technique to partition the technique [13] is employed in CDAC based S/H circuits. For
whole design. Hence, the name Design-Partitioning-Method simplicity single ended bottom plate sampling mechanism is
(DPM) has been used. Root-cause analysis can be done easily shown in the Fig.4b. The clock (φ) and delayed clock (φ d) are
by making individual blocks real while keeping all the other used for bottom-plate sampling. Output voltage of S/H circuit
blocks ideal. It aims at striking an optimized analysis across can be described by Eq.1 and Eq.2 in ideal scenario. Based on
the design vectors, as illustrated in Fig.1. The proposed rms-jitter of the sampling clock, Half-Cycle-Jitter [14] is
platform uses Verilog-A [4] language to model different
components of SAR-ADC.
This paper is organized as follows. Flowchart of the

platform along with implementation details of different blocks
and their integration are discussed in section-II. Section-III
covers the analysis and results. The advantages of the
proposed model over other modelling platforms are discussed
in Section-IV. As a case study, a 14 bit, 4.2MSPS SAR-ADC
is discussed.
II. IMPLEMENTATION
Fig.2 shows a generic block diagram of SAR-ADC which

consists of Switched-Capacitor-Network, Comparator and
SAR-Logic. The Switched-Capacitor-Network functions as
both Sample-and-Hold (S/H) and Digital-to-Analog-Converter
(DAC) circuits [13]. The control signals control the DAC and
S/H block. The aim of the proposed modelling scheme is to
realize the SAR-ADC based on optimal mix of Look-Up-
Tables (LUT) based modelling and conventional behavioral
modelling.
Fig.2 Generic Block Diagram of SAR-ADC

Operational flow of the proposed platform is shown
in Fig.3. Basic parameters VDD, VSS, unit-resistance (Runit),
unit-capacitance (Cunit), etc. are selected. Then the LUTs for
S/H and DAC are generated by simulating spice-netlists. The
platform provides options to consider various non-ideality
parameters like clock-jitter, device-noise, device-mismatch (an Fig.3 Flowchart of the proposed SAR-ADC design platform
equivalent to Monte-Carlo analysis), etc. while generating data modeled. Spread of sampling clock transition-edges is shown
for the LUTs. Behavioral model of Comparator and SAR- in Fig.4c (for 5000 cycles).
Logic are used (discussed in the sections II.C and II.D). Each
functional sub-block of a SAR-ADC is modeled as a separate Vout  Vcm (Sampling Phase) (1)
module having its own set of parameters. Post simulation
extraction of ADC parameters is also a part of the platform.
Details of modelling techniques of the major sub-blocks are Vout  2 * Vcm - Vin ( Hold Phase) (2)
discussed here.
R on_sampling  f1 ( R0 , Vin , VDD , T) (3)
A. Sample and Hold (S/H)
Where, Vout is output voltage of S/H, Vin is input voltage
As shown in Fig.4a, S/H model takes different non-idealities and Vcm is the common mode reference voltage, Ron_sampling is
in consideration. In general, Capacitive DAC (CDAC) itself is the on-resistance of the input sampling-switch, R0 is on-
resistance of sampling-switch at zero-input, nominal- B. Digital to Analog Converter (DAC)

Temperature (270C) and nominal-Supply (2.5V), T is the
absolute temperature. Conventionally Capacitive Digital to Analog Converter
(CDAC) is used as DAC in SAR-ADC as the same DAC can
For LUT generation, input-signal amplitude (Ain) and be used as S/H circuit. As shown in Fig.5a, CDAC consists of
frequency (Fin) are selected. Fin is selected for coherent an array of capacitors. During the conversion-time, bottom-
sampling [15-16]. Rise-time, fall-time, rms-jitter are added to plates of those capacitors can be connected to the common-
the sampling-clock. Voltage and temperature dependency mode reference voltage (Vcm) or positive reference voltage
sampling-switch on-resistance (described by Eq.3) and (Vrefp) or negative reference voltage (Vrefn) depending on the
parasitic at different nodes of sampling network are intermediate bit-pattern generated by SAR-Logic. Bottom-
considered. Top-plates of the sampling capacitor arrays are plate of the terminating-capacitor (CT) [17-18] is connected to
loaded with the input differential pair of MOS devices of the only Vcm (though half-portion of the terminating-capacitor can
comparator, as shown in Fig.4d. In the bottom-plate sampling be connected to Vrefp or Vrefn to make the mean of the
mechanism, sampled voltages across capacitor-arrays are quantization-error zero at the output of ADC). If required,
scaling-capacitor (CS), Hybrid-DAC, Charge-Redistribution
stored into LUTs (S/HLUTp and S/HLUTn). One set of data get
DAC, DAC-Calibration, Redundancy, Non-binary Algorithm
stored in every conversion cycle for differential S/H blocks.
[19-23] can also be incorporated in the proposed modelling
Settling behavior of S/H block is captured. The stored data in
platform by modifying the configuration of the DAC.
the LUTs are more than (N+3)-bit accurate (where N is the
resolution of ADC) as they are generated by simulating spice-
models. It ensures less than 0.125-LSB top-level simulation
error. The simulations become fast as standalone S/H block is
simulated. For S/H circuit, the stop-time of the block-level
transient simulation is equal to the stop-time of the top-level
simulation.
Fig.5 a) Structure of a 4bit CDAC and b) Structure of a 4bit

Hybrid-DAC (Capacitive DAC for MSB 2-bits and Resistive
DAC for LSB 2-bits)
Ci  Di
N
Vout_p_C  Vcm    (Vrefp  Vcm )  e Cp (4)
i 1 C tot
N
C  Di
Vout_n_C  Vcm   i  (Vrefn  Vcm )  e Cn (5)
i 1 C tot
Fig.4 a) S/H Port diagram b) Bottom-Plate Sampling Where,
mechanism (Single-Ended) c) Spread of sampling clock e Cp , e Cn  f 2 ( C ,  C , clk FT , clk CI , Q LEAK ,
transition-edges (σ stands for RMS value of the uncorrelated (6)
clock-jitter) d) Structure of S/H corresponding to a 4bit CDAC COMPLOAD , N KT/C )
a)
C gs_sw
clk FT  VCLK * (7)
C tot
W L C 1
clk CI  sw sw OX * (VCLK  VREF  VTH ) * (8)
2 C tot
kT
N KT/C  (9)
C tot
N
C  Di K R j
Vout_p_R  Vcm  (  i  ) b)
i Q 1 C tot j0 R tot (10)
 (Vrefp  Vcm )  e Rp
N
Ci  Di K R j
Vout_n_R  Vcm  (   )
i Q 1 C tot j0 R tot (11)
 (Vrefn  Vcm )  e Rn
Where,
Q
K   2 (x -1)  Dx (12)
x 1
e Rp , e Rn  f 3 ( R ,  R , clk FT , clk CI , Ron sw , N 0T ) (13)

Ron sw  f 4 (R 0 , VREF , VDD , T) (14)
N 0T  2 * 4kTR unit
Q
(15)
Output voltages of an N-bit generic CDAC can be described

by Eq.4 and 5, where, Vout_p_C and Vout_n_C are the differential
output voltages of CDACs, Vrefp and Vrefn are the positive and
negative reference voltages respectively, Ci is the capacitance
value of the capacitor at ith position, Di is the value of ith bit (1
or 0) generated by SAR-Logic, Ctot is the total capacitance of
the capacitor array, N is resolution of CDAC (4-bits), eCp and
eCn are the errors in CDAC outputs.
Different components of eCp and eCn are shown in Eq.6. σC

represents the standard-deviation of the capacitor mismatch
(device-mismatch), τC is the time-constant of the switch-
capacitor network (settling-error), clkFT (Eq.7) and clkCI (Eq.8)
are the effects of clock-feedthrough and charge-injection
respectively (output-glitches due to switches), QLEAK
represents the charge leakage from capacitors, COMPLOAD is
the comparator load, NKT/C is the KT/C noise (Eq.9) [24-25]. k
is the Boltzmann's constant (1.38 x 10-23 J/K).
In the hybrid-DAC is shown in Fig.5b, CDAC is used for

MSB-bits and RDAC is used for LSB-bits. Its output voltages
can be described by Eq.10 and 11, where, Vout_p_R and Vout_n_R
are the differential output voltages, Rj is the resistance value of
the resistor at jth position, Rtot is the total resistance of resistor-
ladder, K is the index of the on-switch (Eq.12) and Q is the
resolution of Resistive sub-DAC (2-bits), eRp and eRn are the
errors in the RDAC outputs.
Fig.6 a) Binary Tree for 3 bit SAR-ADC and b) Flowchart for
Different components of eRp and eRn are shown in Eq.13. σR
DAC Look-Up-Table generation methodology
represents the standard-deviations of the resistor mismatch
(device-mismatch), τR is the time-constant of the switching- 1) Pre- Amplifier

network (settling-error), Ronsw is the non-linear on-resistance
of output-switch (Eq.14), N0T is the power spectral density of As shown in Fig.7, the Pre-Amplifier is modeled as a
the thermal noise generated by resistor-string (Eq.15) [26-27]. system comprising of three sub blocks, i.e., non-linearity
block, slew block, and small-signal block.
Design parameters can be mathematically modelled by using
functions f1, f2, f3 and f4, but in reality those parameters are
highly non-linear and technology-node dependent. In the
proposed platform block level spice models are simulated
instead of using the functions to extract the accurate numerical
points. Similar to the S/H, in case of DACs, top-plates of the
capacitor arrays are loaded with the input differential pair of Fig.7 Block diagram of Pre-Amplifier Model
MOS devices of the comparator, as shown in Fig.5. DAC
output voltages are stored into Look-Up-Tables (DACLUTp and Three blocks collectively produce the behavioral equivalence
DACLUTn) with respect to input codes. of a real Pre-Amplifier. The model captures the impact of
parameters such as slew-rate limitation, bandwidth limitation,
In case of the DACs of SAR-ADC, any input bit-pattern is dc-offset, gain limitations and device mismatch. Pre-
presided by a typical bit-pattern only, as shown in Fig.6a for a Amplifiers non-linearity is realized through the Non-Linear
3-bit SAR-ADC. The searching-algorithm is analogous to a block using the Eq.16.
binary-tree. Every node of a binary-tree (input bit-pattern) has
only one parent-node (previous bit-pattern). To capture the AnonlinearOut  1 * (input)   2 *[(input) 2 ]   3 *[(input)3 ] (16)
memory-effect (impact of the previous phase on the very next
phase) of DACs, LUTs are generated by following the
Where, “AnonlinearOut” (NL) is the DC output of the Non-Linear
flowchart described in Fig.6b. In phase-1 DACs are reset.
block for the applied input signal (IP). The signal (NL) is then
Followed by phase-2, where DACs are excited with the
passed through Slew-Block, which imitates the amplifier slew-
previous bit-pattern to capture the memory-effect. A separate
rate limitations as per the flowchart shown in Fig.8. Here
algorithm based on the binary-tree is used to search the
“SRO” is the voltage reached by slew block, “TimeRequired”
previous bit-pattern corresponding to the current bit-pattern. In
is the slewing time of the amplifier, “HoldTime” is the time
phase-3 DACs are excited with current bit-pattern. At the end
available for that Pre-Amplifier and “timeLeft” (TL) is the
of phase-3 DAC output voltages corresponding to current bit-
available time for small-signal block. The output of slew block
pattern are stored in LUTs. Simulations for DACs are done by
(SM) is passed to the small-signal block, which realizes
considering input-code as a parameter.
amplifier settling and bandwidth limitations using the
characteristics of small-signal unit-step time response to a
The DACs can be made up with resistors, capacitors
and switches modeled in Verilog-A or devices from second order system. Parameters of the small-signal block are
technology library. For DAC simulations, standard-deviation damping-ratio “ξ” and natural frequency of oscillation “ω n”.
of capacitor and resistor mismatches, parasitic at different Output of the small-signal block is evaluated as per Eq.17, 18,
nodes of capacitors, resistors and switches, on-off resistance 19 and 20.
of switches, voltage dependency of on-resistance of switches,
transient glitches, capacitor leakage, etc. non-idealities can be Vdmp1  SM  [1  {e ( n TL ) } {1  (n  TL )}] (17)
considered optionally. As spice-models are used for DAC
(  n t )
simulations with memory-effect, here also results are more
(1 2 )
than (N+3)-bit accurate (where N is the resolution of ADC). Vdmp2  SM  [1  {e }  {sin( n  (1   2 )
1  2
 t  arctan )}] (18)
C. Comparator 
(   2 - 1 )
In order to ensure 0.5-LSB comparator-resolution-error, Pre- Vdmp3  SM  [1  {  e ((    2 -1 )n t )
}
Amplifiers with Output-Offset-Cancellation (OOC) followed 2   2 -1
by latch architecture [28-29] is used in 14-bit SAR-ADC.
Different stages of comparator are behaviorally modeled. The
comparator output can be generated by solving few multi- (   2 - 1 )
variable time-independent equations only. It makes the {  e ((    2 -1 )n t )
}] (19)
comparator model faster by reducing the number of iterations. 2   -1 2
Modelling methodologies of the different sections of

comparator are discussed here. Vdmp4  0 (20)
examples are shown in Fig.9 and Fig.10. The platform also

presents scope to have standalone Pre-Amplifier modelling
and testing. It helps in deriving Pre-Amplifier specifications.
2) Latch
Calculated Pre-Amplifier output voltage (OP) is applied to the

Latch model. Parameters for the latch model are T Latch (time
available for the latch to take a decision) and τ L (Time
Constant of Latch). Output of Comparator Vcomp is calculated
based on the conventional latch characteristic equation, shown
in Eq.21 [30-33]. Optionally the latch-offset can be included
in the model.
TLatch
( )
L
Vcomp  OP  e (21)
D. SAR-Logic Block
SAR-Logic block is modeled in Verilog-A [34] to save

simulation-time. SAR-Logic generates all the control-signals
for switches and clocks for offset-cancellation, latch and D-
flip-flops. The whole conversion-time is sub divided into 17-
cycles. First 3-cycles are used for sampling and remaining 14-
cycles are used for 14-bit conversion. For the 4.2MSPS ADC,
Fig.8 Flowchart of the modeled Slew Block and Small-
a 71.4MHz (17 x 4.2MSPS) clock is used. At the end of
Signal Block conversion SAR-Logic provides an N-bit ADC output along
with an End-of-Conversion (EOC) signal.
E. SAR-ADC Top-Level: Design-Partitioning-Method
In the top-level, Sample and Hold circuits and DACs are

implemented as Verilog-A modules. Sample and Hold
modules produce outputs from pre-generated Look-Up-Tables.
Outputs of S/H blocks are function of time. DAC modules
produce outputs corresponding to the input bit-pattern
generated by SAR-Logic. DAC modules also use the data
from Look-Up-Tables which are already prepared by
Fig.9 Transient response of the modeled Pre-Amplifier simulating spice-netlist of standalone DACs. Outputs of S/H
modules and DAC modules are summed and the summer
outputs go to the comparator model. As per the comparator
outputs SAR-Logic takes bit by bit decision and produces
appropriate control signals.
Fig.10 Frequency response of the modeled Pre-Amplifier
The transient analysis of the Pre-Amplifier model can be

done by varying the time available for that Pre-Amplifier
(“HoldTime”). AC analysis of the model can also be done to
capture the small-signal behavior of the model. The final- Fig.11 Proposed modelling scheme of SAR-ADC Top-Level:
output (OP), has similar characteristics of a real amplifier, Design-Partitioning-Method
As shown in Fig.11, in the proposed modelling scheme each B. Comparative Study of Digital to Analog Converter (DAC)
block is realized separately (i.e. separate S/H and DAC,
though in reality they are a single block with dual A hybrid-DAC [20, 26] is used in the 14-bit SAR-ADC design
functionality). It results in easy root-cause analysis. (Capacitive DAC for MSB-bits and Resistive DAC for LSB-
bits). Unit resistance (Runit) and unit capacitance (Cunit) values
III. ANALYSIS AND RESULTS for hybrid-DAC are determined based on their mismatch
numbers. σR and σC represents the Standard-Deviations (S.D.)
As a case study 14bit, 4.2MSPS SAR-ADC architecture is of the resistor-mismatch and capacitor-mismatch respectively.
evaluated. Conventional static and dynamic tests have been
done. In static testing a dc-analysis is done by applying a dc-
sweep voltage at input. In dynamic testing a transient analysis a)
is performed with sine-wave input. In post-simulations,
standard parameters of ADC [35-37] are evaluated. For apple
to apple comparison all the simulations are done on spice-
netlist, structural-model and proposed modelling scheme
(DPM).
A. Comparative Study of Sample and Hold (S/H)
In general, performance of S/H circuit degrades with input-

signal frequency (fin) for settling issues. Comparative study of
Sample and Hold circuit accuracy is done by looking at top-
level performance with respect to fin. For different fin, Signal
to Noise and Distortion ratio (SINAD) and Spurious-Free
Dynamic Range (SFDR) plots are shown in Fig. 12a and
Fig.12b (x-axis is normalized in terms of sampling frequency
fs). The pattern of SINAD and SFDR numbers came from
proposed modelling scheme closely follows that of spice-
b)
netlist.
Fig.13 a) SINAD vs. (σR – σC) plots and b) SFDR vs. (σR – σC)
plots (RED: Spice- Netlist, YELLOW: Structural-Model,
BLUE: DPM)
Worst-case SINAD and SFDR numbers from Monte-Carlo

simulations for different σR and σC values are shown in
Fig.13a and Fig.13b. As expected, SINAD and SFDR
degrades with higher σR and σC values. The specifications for
the DAC are derived through the proposed modelling
platform. Runit value corresponding to 0.1061% σR and Cunit
value corresponding to 0.0509% σC are chosen for final
design. With those values top-level performance is found to be
Fig.12 a) SINAD vs. Fin plots and b) SFDR vs. Fin plots (RED: satisfactory.
Spice- Netlist, YELLOW: Structural-Model, BLUE: DPM)
C. Comparative Study of Comparator In the proposed modelling scheme top-level simulations are
done with different number of Pre-Amplifier stages with
different values of Latch-Time-Constant (τL). For simplicity,
a) Voltage Gains (Av) of all the Pre-Amplifier stages are kept
same. The SINAD and SFDR results are shown in Fig.14a and
Fig.14b. The specifications of the Comparator are also derived
using the behavioral-model of the comparator. Three-stage
Pre-Amplifier along with a latch of τL ≈ 80ps are used in the
actual design. Spice-netlist simulation of the final top-level
design reviles ADC performance is satisfactory with the
derived comparator architecture.
b)
Fig.15 ADC Offset vs. No. of Pre-Amplifier stages for 100mV

of Latch Offset
Fig.15 shows the plot of dc-offset in SAR-ADC output for

different number of Pre-Amplifier stages for 100mV Latch-
Offset (intentionally applied). Here also results from proposed
model closely follow the spice-netlist simulation results.
Fig.16 shows the sub-blocks of the comparator. Schematic

of single stage Pre-Amplifier and schematic of latch are shown
in the Fig.17a and 17b respectively. Time constant of the latch
Fig.14 a) SINAD vs. No. of Pre-Amplifier stages and Time is lesser than 80ps in the worst corner.
Constant of Latch (τL) and b) SFDR vs. No. of Pre-Amplifier
stages and Time Constant of Latch (τL)
Fig.16 Sub-blocks in the comparator schematic
a) D. Top-Level (SAR-ADC) Results
Fig.18 Measured FFT plot from DPM
Fig.18 shows a FFT plot of SAR-ADC output through

proposed modelling scheme for 262,144 (2 18) FFT-points
using “Blackman” window. 84.78dB SINAD and 95.99dB
SFDR are achieved at top-level of SAR-ADC.
b) Fig.19 shows the Blocks in the SAR-ADC schematic. Only

major blocks are demarcated in the Figure. The SAR-Logic
generates the appropriate Control-Signals based on bit by bit
decisions.
IV. COMPUTATIONAL EFFORT AND MODEL ADVANTAGES
In the proposed modelling scheme, the whole SAR-ADC is

realized through models of S/H, DAC, Comparator, and SAR-
Logic blocks. Here, S/H and DAC blocks are LUT based
which results in fast top-level simulations. At the same time
data for LUTs of S/H and DAC are generated by simulating
spice-netlists with memory-effects, which produces accurate
data containing all non-idealities. At the beginning of the
clock-cycles the block outputs are selected from LUTs. The
modules at top-level retain the selected outputs for the whole
Fig.17 a) Schematic diagram of single stage Pre-Amplifier and
clock-cycle. Dynamic response of comparator pre-amplifier is
b) Schematic diagram of the Latch
Fig.19 Blocks in the SAR-ADC schematic
realized by a set of multi-variable time-independent equations. Data in the LUTs for DAC as well as S/H are stored in uV
The equations accurately calculate the final comparator output order with 6-digits after decimal point, effectively the data
by solving algebraic equations only, which makes the model accuracy is in the order of pV. As the LUT files contain arrays
independent of iterations. Spice-netlists need iterations in of numbers only, so the memory requirement is insignificant.
continuous-time as they work by solving differential- As shown in the Table-III, for a 2^14 point FFT simulation,
equations. In the proposed model, iterations are required only ~1.2MB memory is required for storing the LUTs.
at clock-edges. This helps in reducing the computational-
In the case of Monte-Carlo simulation, mismatched element
effort.
values are generated using random numbers. The values of
Standard-Deviation for those random numbers are derived
from the Process-Design-Kit (PDK) and Monte-Carlo
simulation results. Then the mismatched element values are
used to generate block level LUTs. In multiple Monte-Carlo
runs different seed values are used to generate different sets of
random numbers.
In the proposed modelling scheme, each functional-block is

realized separately in top-level (Design ‘Partitioning’
Method). In case of undesired top-level performance,
individual blocks can be made real while keeping other blocks
ideal, which makes root-cause analysis easy.
Fig.20 Accuracy and Simulation-Time (RED: Spice-Netlist, TABLE I. SIMULATION TIME COMPARISON
YELLOW: Structural Model and BLUE: DPM)
Proposed Structural Spice
Analysis
Fig.20 shows simulation-time reduction in the proposed Platform Model Netlist
modelling scheme while providing better accuracy than the Dynamic
structural-model. The accuracy numbers are evaluated by Testing
13.5 hrs 88 hrs 416 hrs
calculating percentage accuracy in terms of SINAD (Fig.12a (16384 FFT
and 13a), SFDR (Fig.12b and 13b) and offset measurement Points)
(Fig.15), assuming spice-netlist results are 100% accurate
(reference results). Structural model lags in accuracy as
individual blocks are not as accurate as spice-netlist while in TABLE II. SIMULATION TIME BREAK-UP
the proposed modelling scheme; data for each individual block
is generated by simulating spice-netlist only. The simulation- Analysis Attributes DAC S/H Top-Level
time of Structural Model is also 7-times that of the proposed
Simulation 1.15
modelling scheme. The extremely fast top-level simulation (by Dynamic 4.8 hrs 0.8 hrs
Time hrs
eliminating the need of iteration) results in this simulation- Testing
Simulator
time reduction. (16384 2 2 2
Licenses
FFT
Points) Effective 2.3
Time taken by the proposed modelling platform for a 9.6 hrs 1.6 hrs
Time hrs
dynamic-simulation (16,384 point FFT) is only ~3% of the
time taken by equivalent spice-netlist. Detail simulation-time
measurements are given in Table-I. Effective simulation-time
is calculated by multiplying actual simulation time and
number of simulator licenses. TABLE III. MEMORY REQUIREMENT FOR LUT
LUT Memory
The simulation-time advantage becomes more pronounced Block Data- No. of
Size Requirement
in the cases where design changes are required in selective Name Points LUTs
(KB) (KB)
blocks only. Any changes in a single block results in re-
generation of that block’s data only. Table-II describes the 16384
DAC ~300 2 ~600
simulation-time (13.5hrs mentioned in Table-I) break-up for (2^14)
different blocks. Similarly for large number of FFT points 16384
S/H ~300 2 ~600
only S/H block and top-level need longer simulation times, (2^14)
same DAC data can be re-used there. It also increases the Total Memory Requirement (KB) ~1200
reusability of the model.
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This article has been accepted for publication in a future issue of this journal, but has not been

Date: July 24, 2015

4. Ashvin Kumar G. Katakwar

A Novel Approach to Design SAR-ADC:

Email: 1prajit_n@sankalpsemi.com, 2hirak_t@sankalpsemi.com

Abstract— This paper presents a Successive-Approximation-

This paper is organized as follows. Flowchart of the

Fig.2 shows a generic block diagram of SAR-ADC which

Fig.2 Generic Block Diagram of SAR-ADC

resistance of sampling-switch at zero-input, nominal- B. Digital to Analog Converter (DAC)

Fig.5 a) Structure of a 4bit CDAC and b) Structure of a 4bit

e Rp , e Rn  f 3 ( R ,  R , clk FT , clk CI , Ron sw , N 0T ) (13)

Output voltages of an N-bit generic CDAC can be described

Different components of eCp and eCn are shown in Eq.6. σC

In the hybrid-DAC is shown in Fig.5b, CDAC is used for

(device-mismatch), τR is the time-constant of the switching- 1) Pre- Amplifier

Modelling methodologies of the different sections of

examples are shown in Fig.9 and Fig.10. The platform also

Calculated Pre-Amplifier output voltage (OP) is applied to the

SAR-Logic block is modeled in Verilog-A [34] to save

E. SAR-ADC Top-Level: Design-Partitioning-Method

In the top-level, Sample and Hold circuits and DACs are

Fig.10 Frequency response of the modeled Pre-Amplifier

The transient analysis of the Pre-Amplifier model can be

A. Comparative Study of Sample and Hold (S/H)

In general, performance of S/H circuit degrades with input-

Worst-case SINAD and SFDR numbers from Monte-Carlo

Fig.15 ADC Offset vs. No. of Pre-Amplifier stages for 100mV

Fig.15 shows the plot of dc-offset in SAR-ADC output for

Fig.16 shows the sub-blocks of the comparator. Schematic

Fig.16 Sub-blocks in the comparator schematic

a) D. Top-Level (SAR-ADC) Results

Fig.18 Measured FFT plot from DPM

Fig.18 shows a FFT plot of SAR-ADC output through

b) Fig.19 shows the Blocks in the SAR-ADC schematic. Only

IV. COMPUTATIONAL EFFORT AND MODEL ADVANTAGES

In the proposed modelling scheme, the whole SAR-ADC is

Fig.19 Blocks in the SAR-ADC schematic

In the proposed modelling scheme, each functional-block is

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