8258I Service Manual

SERVICE MANUAL FOR
8258I
BY: Sanny Gao

Technical Maintenance Department /GTK MTC
Jun.2006 / R01
8258I N/B Maintenance
Contents
1. Hardware Engineering Specification …………………………………………………………………… 4

1.1 Introduction ……………………………………………………………………………………………………………. 4
1.2 System Hardware Parts ….……………………………………………………………………………………………. 6
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1.3 Other Functions ……………………………………………………………………………………………………….. 33
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1.4 Power Management …………………………..…………………………………………………………….………….
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1.5 Appendix 1: Intel ICH7-M GPIO Definitions ………………………………………………………………………. 41
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1.6 Appendix 2: W83L951DG KBC GPIO Pins Definitions ……..…………………………………………………….. 43
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2. System View and Disassembly ………………………………………………………………………….. 49
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2.1 System View ……………………………………………………………………………………………………………. 49
2.2 Tools Introduction …………………………………………………………………………………………………..…. 52
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2.3 System Disassembly ……………………………………………………………………………………………………. 53
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3. Definition & Location of Connectors/Switches …………………………………………………………
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3.1 Mother Board (Side A) ….………………………………………………………..…………………………………… 72
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3.2 Mother Board (Side B) ….…………………………...………………………………………………………………… 74
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4. Definition & Location of Major Components ………………………………………………………….. 76
4.1 Mother Board (Side A) ….……………………………………………………………………………………..……… 76

4.2 Mother Board (Side B) ….……………………………………………………………………………………..……… 77
5. Pin Description of Major Component ………………………………………………………………….. 78
5.1 Intel Yonah Processor CPU …………………………………………………………………………………………… 78

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Contents
5.2 Intel 945GM North Bridge ……………………………………………………………………………………………. 83

5.3 Intel ICH7-M South Bridge …………………………………………………………………………………………… 89
6. System Block Diagram …………………………………………………………………………………… 100
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7. Maintenance Diagnostics …………………………………………………………………………………
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7.1 Introduction ……………………………………………………………………………………………………………. 101
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7.2 Maintenance Diagnostics ……………………………………………………………………………………………… 102
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7.3 Error Codes ……………………………………………………………………………………………………………. 103
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8. Trouble Shooting ………………………………………………………………………………………… 105
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8.1 No Power ………………………………………………………………………………………………………………. 107
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8.2 No Display ……………………………………………………………………………………………………………… 113
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8.3 Memory Test Error ………………………………………….…………………………………………………………
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8.4 Keyboard (K/B) or Touch Pad (T/P) Test Error ……………..…………………………………………………...… 118
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8.5 Hard Disk Drive Test Error ………………………..…………………………………………………………………. 120
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8.6 ODD Test Error …………………………………………………………………..……………………………..…….. 122
8.7 USB Port Test Error …………………………………………………………………………………………………… 124
8.8 Audio Test Error ………………………………………………………………………………………..……………... 126
8.9 LAN Test Error ………………………………………………………………………………………..……….………. 129
8.10 Mini Express (Wireless) Socket Test Error ………………………..…………………………………………….…. 131
8.11 New Card Socket Test Error …………………………………………..…………………………………………….. 133
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Contents
9. Spare Parts List ………………………………………………………………………………………….. 135
10. System Exploded Views ………………………………………………………………………………... 146
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11. Reference Material ………………………………………………………………………………….….. 148
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1. Hardware Engineering Specification
1.1 Introduction
1.1.1 General Description

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This document describes the brief introduction for MITAC 8258I portable notebook computer system.
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1.1.2 System Overview
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The MITAC 8258I model is designed for Intel Mobile Pentium-M processor Yonah 533 and 667 FSB.
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This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has
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standard hardware peripheral interface. The power management complies with Advanced Configuration and Power
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Interface. It also provides easy configuration through CMOS setup, which is built in system bios software and can
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be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system
status, such as AC/battery power indicator, battery charger indicator, HDD/ODD, NUM LOCK, CAP LOCK,
Wireless LAN indicator. It also equipped with 10/100 LAN, 56 K fax modem, 4 USB ports, S-Video, audio Line-
out/SPDIF, Line-in and internal/external microphone function.
The memory subsystem supports DDR2 SDRAM channels (64-bit wide).
The 945GM MCH host memory controller integrates a high performance host interface for Intel Yonah processor,
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a high performance PCI Express interface, a high performance memory controller, and Direct Media Interface
(DMI) connecting with Intel ICH7-M.
The Intel ICH7-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the audio
controller with Azalia interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers,
the SATA controller and Direct Media Interface technology.
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Intel graphics enhancements includes DVMT 3.0, Zone Rendering 2.0, Quad pixel pipe rendering engine, Pixel
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Shader 2.0 and 4x Faster Setup Engine.
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The Realtek RTL8100CL is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides
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32-bit performance, PCI bus master capability and full compliance with IEEE 802.3u 100Base-T specifications
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and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management
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Interface (ACPI).
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The ALC883 2-channel high definition audio codec with UAA (Universal Audio Architecture), featuring a 24-bit
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two-channel DAC and two stereo 20-bit ADCs, are designed for commercial notebook PC system. The ALC883
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provides 2 output channels, along with flexible mixing, mute and fine gain control functions. Also, supporting 32-
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bit S/PDIF output functions and a sampling rate of up to 96 KHz.
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The W83L951D is a high performance microcontroller on-chip supporting functions optimized for embedded
control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus
interface, host interface, A/D converter, D/A converter, I/O ports and other functions needed in control system
configurations, so that compact, high performance systems can be implemented easily.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus
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mastering IDE, plug and play, Advanced Power Management (APM) with application restart, software-controlled
Power shut-down.
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 System Hardware Parts
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CPU -Mobile Pentium-M Processor Yonah 533 and 667 FSB-Thermal spec 40W TDP
Core logic
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Intel 945GM + ICH7-M chipset
System BIOS
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SST49LF004A
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DDR2 533 256 MB: Nanya, NT256T64UH4A1FN-37B
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Infineon, HYS64T32000HDL-3.7-B
Memory
DDR2 533 512 MB: Nanya, NT512T64UH8A1FN-37B
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HDD
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SATA : Fujitsu, MHV2040BH (Mercury60 series)
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ODD COMBO : Panasonic, UJDA770 or HLDS, GCC-4244N
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Display 15.4” : AUO B154EW01 V8 None Glare Samsung LTN154X3-L01
Clock Generator
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ICS 9LPR310
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VGA Control -Intel 945GM
LAN RTL8100CL
Audio System Azalia CODEC: ALC883
Modem 56 Kbps(V.90) Fax Modem (MDC (Azalia I/F)) Askey 1456VQL-R2
Wireless LAN Wireless LAN Intel Pro/Wireless 3945ABG (Mini PCI-E Interface IEEE802.11a, b, g)
USB USB2.0 x 4 (individual)
New Card MINI-PCI-E interface
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1.2.1 Intel Yonah Processors in Micro-FCBGA Package

Intel Yonah Processors with 478 pins Micro-FCBGA package.
The Yonah processor is built on Intel’s next generation 65 nanometer process technology. Yonah is Intel’s first
dual core processor for mobile.
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The following list provides some of the key features on this processor:
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• First dual core processor for mobile
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• Supports Intel architecture with dynamic execution
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• On-die, primary 32-KB instruction cache and 32-KB write back data cache
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• On-die, 2 MB L2 cache with advanced transfer cache architecture
• Data prefetech logic
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• Streaming SIMD Extension 2 (SSE2) and Streaming SIMD Extension 3 (SSE3)
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• The Yonah standard voltage and low voltage processor are offered at 667 MHz FSB
• The Yonah ultra low voltage processor is offered at 533 MHz FSB
• Advanced power management features including enhanced Intel Speed-Step technology
• Digital temperature sensor
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• Micro-FCPGA and Micro-FCBGA package technologies

• Execute disable bit support for enhanced security
• Intel virtualization technology
1.2.2 Clock Generator

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ICS9LPR310 is a low power CK410M-compliant clock specification. This clock synthesizer provides a single chip
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solution for next generation P4 Intel processors and Intel chipsets. ICS9LPR310 is driven with a 14.318 MHz
crystal.
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Output Feathers
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• 2 - 0.7 V differential CPU pairs
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• 8 - 0.7 V differential PCIEX pairs
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• 1 - 0.7 V differential SATA pair
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• 1 - 0.7 V differential LCDCLK/PCIEX selectable pair
• 4 - PCI (33 MHz)
• 2 - PCICLK_F, (33 MHz) free-running
• 1 - USB, 48 MHz
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• 1 - DOT 96 MHz/27 MHz selectable pair

• 2 - REF, 14.318 MHz
Key Specifications
• CPU outputs cycle-cycle jitter < 85 ps
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• PCIEX outputs cycle-cycle jitter < 125 ps
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• SATA outputs cycle-cycle jitter < 125 ps
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• PCI outputs cycle-cycle jitter < 500 ps
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• +/- 300 ppm frequency accuracy on CPU, PCIEX and SATA clocks
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• +/- 100 ppm frequency accuracy on USB clocks
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Features/Benefits
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• Supports tight ppm accuracy clocks for Serial-ATA and PCIEX
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• Supports programmable spread percentage and frequency
• Uses external 14.318 MHz crystal, external crystal load
• PEREQ# pins to support PCIEX power management
• Low power differential clock outputs (no 50 ohm resistor to GND needed)
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1.2.3 The Mobile Intel 945GM Express Chipset

The Mobile Intel 945GM Express chipset is designed for use in Intel’s next generation mobile platform code
named NAPA.
The Intel 945GM Express chipset come with the generation 3.5 Intel integrated graphics engine, and the Intel
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Graphics Media Accelerator (GMA) 950, providing enhanced graphics support over the previous generation
(G)MCH’s.
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The (G)MCH manages the flow of information between the four following primary interfaces:
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• FSB
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• System memory interface
• Graphics interface
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• DMI
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The (G)MCH can also be enabled to support external graphics, using the x16 PCI Express graphics attach port.
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When external graphics is enabled, the internal graphics port are inactive.
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Features:
Processor Support
• All Yonah variants
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• Merom support
• 533 MHz and 667 MHz Front Side Bus (FSB) support
• Source synchronous double-pumped (2x) address
• Source synchronous quad-pumped (4x) data
• Other key features are

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- Support for DBI (Data Bus Inversion)
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- Support for MSI (Message Signaled Interrupt)
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- 32-bit interface to address up to 4 GB of memory
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- A 12 deep In-Order queue to pipeline FSB commands
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- GTL+ bus driver with integrated GTL termination resistors
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Memory System
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• Support single/dual channel DDR2 SDRAM
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• Maximum memory supported 2 GB
• 64-bit wide per channel
• Three memory channel configurations supported

- Single channel
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- Dual channel symmetric

- Dual channel asymmetric
• One SO-DIMM connector per channel
• Support for DDR2 at 400 MHz, 533 MHz and 667 MHz
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• 256 Mb, 512 Mb and 1 Gb memory technologies supported
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• Support for x8 and x16 devices
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• Maximum memory supported: 2 GB
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• Support for DDR2 On-Die Termination (ODT)
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• Supports partial writes to memory using Data Mask signals (DM)
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• Intel rapid memory power management
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• Dynamic row power-down
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• No support for fast chip select mode
• Support for 2N timings only
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Internal Graphics
• Intel Gen 3.5 integrated graphics engine
• 250 MHz core rendor clock at 1.05 V core voltage
• Supports TV-Out, LVDS, CRT and SDVO
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• Intel dual frequency graphics technology
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• Intel Dynamic Video Memory Technology (DVMT 3.0)
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• Intel smart 2D display technology
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• Intel display power saving technology 2.0
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• Video capture via x1 concurrent PCIE port
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• Higher performance MPEG-2 decoding
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• Hardware acceleration for VLD/iDCT
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• 4x pixel rate HWMC
• DX 9.1
• Hardware motion compensation
• Intermediate Z in classic rendering

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Analog CRT
• Integrated 400 MHz RAMDAC
• Analog monitor support up to QXGA (2048 x 1536)
• Support for CRT hot plug
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Dual Channel LVDS
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• Panel support up to UXGA (1600 x 1200)
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• 25-112 MHz single/dual channel
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- Single channel LVDS interface support: 1 x 18 bpp
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- Dual channels LVDS interface support: 2 x 18 bpp panel support up to UXGA (1600 x 1200)
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- TFT panel type supported
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• Pixel Dithering for 18-bit TFT panel to emulate 24 bpp true color displays
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• Panel fitting, panning and center mode supported
• CPIS 1.5 compliant
• Spread spertrum clocking supported
• Panel power sequencing support
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• Integrated PWM interface for LCD backlight inberter control
TV-OUT
• Three integrated 10-bit DACS
• Macro Vision support
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• Overscaling
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• NTSC/PAL
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• Component, S-Video and composite output interfaces
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• HDTV support 480p/720p/1080i/1080p
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DMI
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• Chip-to-chip interface between (G)MCH and Intel 82801GBM (ICH7-M)
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• Configurable as x2 or x4 DMI lanes
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• 2 GB/s (1 GB/s each direction) point-to-point interface to Intel 82801GBM
• 32-bit downstream address
• Direct Media Interface asynchronously coupled to core
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• Supports 3 virtual channels for traffic class performance differentiation
• Supports both snooped and non-snooped traffic
• Supports isochronous non-snooped traffic
• Supports legacy snooped isochronous traffic
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• Supports the following traffic types to or from Intel 82801GBM
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• Peer write traffic between DMI and PCI Express graphics port
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• DMI-to-DRAM
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• DMI-to-CPU (FSB interrupts or MSIs only)
• CPU-to-DMI
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• Messaging in both directions, including Intel Vendor-specific messages
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• Supports power management state change messages
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• APIC and MSI interrupt messaging support
• Supports SMI, SCI and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port DMA, floppy drive
and LPC bus masters
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1.2.4 I/O Controller Hub: Intel ICH7-M
The ICH7 provides extensive I/O support. Functions and capabilities include:
• PCI Express base specification, revision 1.0a support

• PCI local bus specification, revision 2.3 support for 33 MHz PCI operations (supports up to six Req/Gnt pairs)
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• ACPI power management logic support
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• Enhanced DMA controller, interrupt controller and timer functions
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• Integrated serial ATA host controller with independent DMA operation on four ports and AHCI (ICH7R
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support
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• USB host interface with support for eight USB ports; four UHCI host controllers; one EHCI high-speed USB
2.0 host controller
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• System Management Bus (SMbus) specification, version 2.0 with additional support for I2C devices
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• Supports audio codec ’97, revision 2.3 specification (a.k.a , AC ’97 component specification, revision 2.3)
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which provides a link for audio and telephony codecs (up to 7 channels)
• Supports Intel high definition audio

• Supports Intel Matrix storage technology (ICH7R only)
• Supports Intel Active Management Technology
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• Low Pin Count (LPC) interface
• Firmware Hub (FWH) interface support
1.2.5 Azalia Audio System: ALC880
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ALC880 provides 7.1 channels of outputs and multiple stereo inputs, along with flexible mixing, mute and finer
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gain ALC880 provides 7.1 channels of outputs and multiple stereo inputs, along with flexible mixing, mute and
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finer gain control functions to provide a complete integrated audio solution for PCs. Also the highest 192 KHz
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sample rate DACs and Realtek proprietary hardware content protection are applicable for DVD audio, which only
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implemented in high end consumer electronics, now is achieved by PCs with ALC880 inside. ALC880 is also the
one and only high definition audio codec integrating three pairs of stereo ADCs which can support microphone
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array with AEC (Acoustic Echo Cancellation), BF (Beam Forming) and NS (Noise Suppression) technology
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simultaneously to significantly improve recording quality for conference call. With this unique feature (3 pairs of
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Stereo ADCs), ALC880 can perform the ultimate performance of HAD like using S/PDIF to output analog data or
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multiple recording application.
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• High performance DACs with 95 dB S/N ratio
• Meets performance requirements for audio on PC2001 systems
• 8 channels of DAC support 16/20/24-bit PCM format for 7.1 audio solution
• 3 stereo ADCs support 16/20-bit PCM format, two for microphone array, one for legacy mixer recording
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• Supports 44.1/48/96/192 KHz DAC sample rate
• All ADCs support 44.1/48/96 KHz sample rate
• Applicable for 4 ch/192 KHz and 6 ch/96 KHz DVD-Audio solution
• Up to 4 channels of microphone input are supported for AEC/BF application
• Support power off CD function

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• Support external PCBEEP input and built in BEEP generator
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• PCBEEP Pass-Through when link is in RESET state
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• Software selectable 2.5 V/3.75 V VREFOUT
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• Default 6 VREFOUTs are supported, additional 4 VREFOUTs are capable by sharing un-used analog I/O pins
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• 2 jack detection pins each supports up to 4 jacks plugging can be detected
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• 16/20/24-bit S/PDIF-OUT supports 44.1/48/96 KHz sample rate
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• 16/20/24-bit S/PDIF-IN supports 44.1/48/96 KHz sample rate
• Optional EPAD (External Amplifier Power Down) is supported
• Power support digital 3.3 V, analog 3.3 V/5.0 V
• Power management and enhanced power saving features

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• 48-pin LQFP package is compatible with AC’97
• Reserve analog mixer architecture is backward compatible with AC’97
• –64 dB ~ +30 dB with 1dB resolution of mixer gain to achieve finer volume control
• Impedance sensing capability for each re-tasking jack support power off CD function
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• All analog jacks are stereo input and output re-tasking for analog plug & play
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• Built in headphone amplifier for each re-tasking jack
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• Support external volume knob control
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• Support 2 GPIO (General Purpose Input/Output) for customized application
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• Hardware content protection for DVD-Audio supporting
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1.2.6 MDC: Azalia MDC Modem
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Feathers:
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• AC’97/MC’97 2.2 compliant
• MDC Modem support current sense, whenever the current on the line exceeds approximately 150 mA and
should immediately go back on hook
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• ITU-T V.92 PCM Upstream and V.90 data rates with auto0fallback to V.34, V.32ter V.32 bis and fallbacks
• Virtual com port with a through put of up to 460.8 Kbps
• V.42 bis/MNP 5 data compression
• FAX send and receive rates up to 14.4kbps, V.17, V.29, V.27ter
• Hayes AT command set

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• Supports V.42 error correction and V.44, V.42bis/MNP5 data compression
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• FAX capabilities: ITU-T V.17, V.29, V.27ter, V.21 Ch2 and TIA/EIA 578 Class1 FAX
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• Modem support wake up on ring
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1.2.7 System Flash Memory (BIOS)
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• Firmware hub for Intel® 810, 810E, 815, 815E, 815EP, 820, 840, 850 chipsets
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• Flexible erase capability
- Uniform 4 KBytes sectors

- Uniform 16 KBytes overlay blocks for SST49LF002A
- Uniform 64 KBytes overlay blocks for SST49LF004A
- Top boot block protection
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- 16 KBytes for SST49LF002A
- 64 KBytes for SST49LF004A

- Chip-Erase for PP mode
• Single 3.0-3.6 V read and write operations
• Superior reliability
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• Firmware hub hardware interface mode
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- 5-signal communication interface supporting byte read and write
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- 33 MHz clock frequency operation
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- WP# and TBL# pins provide hardware write protect for entire chip and/or top boot block
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- Block locking register for all blocks
- Standard SDP command set
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- Data# Polling and Toggle Bit for End-of-Write detection
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- 5 GPI pins for system design flexibility
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- 4 ID pins for multi-chip selection
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1.2.8 Memory System
128 MB, 256 MB, 512 MB, 1 GB (x64) 200-Pin DDR2 SDRAM SODIMMs
• JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)
• VDD=+1.8 V±0.1 V, VDDQ=+1.8 V±0.1 V
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• JEDEC standard 1.8 V I/O (SSTL_18-compatible)
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• Differential data strobe (DQS,DQS#) option
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• Four-bit prefetch architecture
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• Differential clock input (CK, CK#)
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• Command entered on each rising CK edge
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• DQS edge-aligned with data for reads
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• DQS center-aligned with data for writes
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• Duplicate output strobe (RDQS) option for x8 configuration
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data Mask (DM) for masking write data

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• Programmable CAS Latency (CL): 2, 3, 4 and 5
• Posted CAS additive latency (AL): 0, 1, 2, 3 and 4
• Write latency = read latency – 1tCK
• Programmable burst lengths : 4 or 8
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• Read burst interrupt supported by another read
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• Write burst interrupt supported by another write
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• Adjustable data – output drive strength
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• Concurrent auto precharge option is supported
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• Auto Refresh (CBS) and self refresh mode
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• 64 ms, 8, 192-cycle refresh
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• Off-Chip Drive (OCD) impedance calibration
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• On-die termination (ODT)
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1.2.9 LAN
The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip fast Ethernet controller that provides
32-bit performance, PCI bus master capability and full compliance with IEEE 802.3u 100Base-T specifications
and IEEE 802.3x full duplex flow control. It also supports the Advanced Configuration Power management
Interface (ACPI), PCI power management for modern operating systems that are capable of Operating System
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Directed Power Management (OSPM) to achieve the most efficient power management possible. The RTL8100C
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(L) does not support CardBus mode as the RTL8139C does. In addition to the ACPI feature, the RTL8100C(L)
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also supports remote wake-up (including AMD Magic Packet, LinkChg, and Microsoft® wake-up frame) in both
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ACPI and APM environments. The RTL8100C(L) is capable of performing an internal reset through the
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application of auxiliary power. When auxiliary power is applied and the main power remains off, the
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RTL8100C(L) is ready and waiting for the magic packet or link change to wake the system up. Also, the LWAKE
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pin provides 4 different output signals including active high, active low, positive pulse and negative pulse. The
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versatility of the RTL8100C(L) LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality.
The RTL8100C(L) also supports analog Auto-Power-down, that is, the analog part of the RTL8100C(L) can be
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shut down temporarily according to user requirements or when the RTL8100C(L) is in a power down state with
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the wakeup function disabled. In addition, when the analog part is shut down and the isolate B pin is low (i.e. the
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main power is off), then both the analog and digital parts stop functioning and the power consumption of the
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RTL8100C(L) will be negligible. The RTL8100C(L) also supports an auxiliary power auto-detect function and
will auto-configure related bits of their own PCI power management registers in PCI configuration space.
• 128-pin QFP/LQFP
• Integrated fast Ethernet MAC, physical chip and transceiver in one chip
• 10 Mb/s and 100 Mb/s operation

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• Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation
• PCI local bus single-chip fast Ethernet controller
- Compliant to PCI revision 2.2

- Supports PCI clock 16.75 MHz-40 MHz
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- Supports PCI target fast back-to-back transaction
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- Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of
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RTL8100C(L)'s operational registers
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- Supports PCI VPD (Vital Product Data)
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- Supports ACPI, PCI power management
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• Supports 25 MHz crystal or 25 MHz OSC as the internal clock source. The frequency deviation of either
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crystal or OSC must be within 50 PPM
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• Compliant to PC99/PC2001 standard
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• Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-up
frame)
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• Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse and negative pulse)
• Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off
• Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI
26
configuration space
• Includes a programmable, PCI burst size and early Tx/Rx threshold
• Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timer-
interrupt
t nt
• Contains two large (2 KBytes) independent receive and transmit FIFOs
r e e
• Advanced power saving mode when LAN function or wakeup function is not used
e c m
S u
• Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter and VPD data
c
a c Do
• Supports LED pins for various network activity indications
iT ial
M t
• Supports loopback capability, Half/Full duplex capability
en
• Supports full duplex flow control (IEEE 802.3x)
f id
o n
1.2.10 Keyboard System: Winbond W83L951DG
C
The Winbond mobile keyboard and embedded controller W83L951D/F architecture consists of a Turbo-8051 core
logic controller and surrounded by various components, 2 K+256 bytes of RAM, 64 K on-chip flash, LPC host
interface, 13 general purpose I/O port with 24 external interrupt source, 4 timers, 1 serial port, 2 SMBus interface
for master mode, 3 PS/2 port, two 8-bit and two 16-bit PWM channels, 2 D-A and 8 A-D converters, 1 Consumer
Infrared communications receiver, 2 fan tachometer, 1 real time clock generator and matrix interface. The part
number with an affix of “G” is the Lead-free package product.
27
128-pin QFP/LQFP
• 8-bit Turbo 8052 Microprocessor code based, speed up to 24 MHz
• 256 bytes internal RAM
• 64 K bytes embedded programmable flash memory
t nt
e e
• 2 K bytes external SRAM
r
c m
e
Host interface
S cu
c Do
• Software optional with LPC interface
a
iT ial
• Primary programmable I/O address communication port in LPC mode
M t
n
• Support SERIRQ in LPC interface
e
id
• Support hardware fast Gate A20 and KBRST
nf
o
• Support port 92 h
SMBus C
• Support 2 SMBus interface support master mode
Timers
28
• Support four timer signal with three pre-scalars
• Timer 1 and 2 Shard the Same Pre-scalar and are Free-Running Only
• Timer X and Y Have Individual Pre-scalar and Support up to Four Control Modes, Free Running, Pulse
Output, Event Counter and Pulse Width Measurement
PWM
t nt
re e
c m
• Support four PWM Channels
Se u
c
• PWM 0 and 1 are 8-bit and programmable frequency from 62 Hz to 7.5 KHz
ac Do
iT ial
• PWM 2 and 3 are 16-bit and programmable frequency from 6 Hz to 3 MHz
Fan Tachometer
M t
en
id
• Support two fan tachometer inputs
A/D Converter
nf
Co
• Firmware programmable optional with 10-bit or 8-bit resolution, support eight channels
D/A Converter
• 8-bit Resolution, support two channels
29
PS2
• Support three hardware PS2 channels
• Optional PS2 clock inhibit by hardware or firmware
Keyboard Controller
t nt
e e
• Support 16*8 keyboard Matrix-scan, expanding to 18*8 and 20*8
r
ec m
u
GPIO
S
c Do c
a
• Support 104 useful GPIO pins totally and Bit–addressable to facility firmware coding
Flash iT ial
M t
en
• Support external On-Board 64 K flash via matrix interface (GP0, 1, 3)
CIR
fid
on
C
• Support decoding for the NEC consumer IR remote control format
RTC
• Real time clock generator with 32.768 KHz input
ACPI
30
• Support ACPI appliance secondary programmable I/O address communication port in LPC mode
Package
• 128-pin QFP and 128-pin LQFP package options
1.2.11 Hard Disk Drive

t nt
re e
c m
8258I can support SATA HDD by equipped different HDD transition board.
e
S cu
c Do
SATA HDD: The SATA function in the ICH7 has dual modes of operation to support different operating system
a
conditions. In the case of native IDE enabled operating systems, the ICH7 has separate PCI functions for
iT ial
serial and parallel ATA (enhanced mode). To support legacy operating systems, there is only one PCI
M t
function for both the serial and parallel ATA ports if functionality from both SATA and PATA devices is
n
desired (combined mode). SATA interface transfer rates are independent of UDMA mode settings. SATA
e
interface transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by
fid
the SATA device or the system BIOS.
on
• Up-to 150 MB/sec bus speed (Serial ATA generation 1)
C
• Compliant with Serial ATA 1.0a specification and Serial ATA 2 extensions 1.0
• Supports 48-bit LBA addressing
• Supports native DMA queued command (first party DMA queued)
31
• Supports legacy DMA queued command
• Supports staggered spin-up function
• Supports Hot-Plug features
• Supports Serial ATA power management (host initiated partial/slumber)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
C
32
1.3 Other Functions
1.3.1 Hot Key Function
Keys Combination Feature Meaning

Fn + F1
t
Wireless LAN ON/OFF
nt Wireless LAN ON/OFF
e e
Fn + F2 Bluetooth ON/OFF
Fn + F3 Volume Down
r
c m
e
Fn + F4 Volume Up
Fn + F5
S cu
LCD/external CRT switching Rotate display mode in LCD only, CRT only, and simultaneously
Fn + F6
c Do
Brightness down
a
Decreases the LCD brightness
iT ial
Fn + F7 Brightness up Increases the LCD brightness
Fn + F10 Mute Audio Mute
M t
Fn + F11 Display Off/On Toggle Display on/off
n
Force the computer into either Suspend to HDD or Suspend to
e
Fn + F12 Suspend to DRAM / HDD DRAM mode depending on BIOS Setup.
fid
o n
1.3.2 Power on/off/suspend/resume button
APM Mode
C
• At APM mode, power button is on/off system power
ACPI Mode
33
• At ACPI mode, windows power management control panel set power button behavior. You could set “standby”,
“power off” or “hibernate” (must enable hibernate function in power management) to power button function.
Continue pushing power button over 4 seconds will force system off at ACPI mode.
1.3.3 Cover Switch
t nt
System automatically provides power saving by monitoring cover switch. It will save battery power and prolong
re e
the usage time when user closes the notebook cover.
ec m
S u
At ACPI mode there are four functions to be chosen at windows power management control panel.
c Do c
a
1. None
2. Standby
iT ial
M t
n
3. Off
e
id
4. Hibernate (must enable hibernate function in power management)
nf
C o
1.3.4 LED Indicators
Six LED indicators
From left to right that indicates Power, Battery Status, HDD/ODD, NUM LOCK, CAP LOCK, WLAN.
Power: This LED lights blue when the notebook was powered by AC or battery power line, flashes (on 1 second,
34
off 1 second) when entered suspend to RAM state. The LED is off when the notebook is in power off state.
Battery status: With battery operation, this LED stays off. When the battery charge drops to 10% of capacity, the
LED lights red, flashes per 1 second and beeps per 2 seconds. When AC is connected, this indicator stays
off if the battery pack is fully charged or red if the battery is being charged.
System has four status LED indicators at front side which to display system activity: HDD/ODD, NUM LOCK,
CAPS LOCK and WLAN.
t nt
re e
ec m
u
1.3.5 Battery Status
S
c Do c
a
iT ial
1.3.5.1 Battery Warning
M t
• System also provides Battery capacity monitoring and gives users a warning signal to alarm they to store data
en
before battery dead. This function also protects system from mal-function while battery capacity is low
fid
• Battery Warning: Capacity below 10%, Battery Status LED flashes per second, system beeps per 2 seconds
o n
C
• System will suspend to HDD after 2 Minutes to protect users data
1.3.5.2 Battery Low State
After battery warning state, and battery capacity is below 5%, system will generate beep sound for twice per
second.
35
1.3.5.3 Battery Dead State
When the battery voltage level reaches 8.56 volts, system will shut down automatically in order to extend the
battery packs' life.
1.3.6 Fan power on/off management

t nt
re e
Fan is controlled by W83L951DG embedded controller-using ADM1032 to sense CPU temperature and PWM
ec m
control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster fan speed.
S cu
1.3.7 CMOS Battery
ac Do
iT ial
M t
CR2032 3 V 220 mAh lithium battery, when AC in or system main battery inside, CMOS battery will consume
no power.
en
id
AC or main battery not exists, CMOS battery life at less (220 mAh/5.8 uA) 4 years
nf
1.3.8 I/O Ports
Co
• One Power Supply Jack
• One External CRT Connector For CRT Display
• Supports four USB port for all USB devices

36
• One modem RJ-11 phone jack for PSTN line
• One RJ-45 for LAN
• One SPDIF jack
• One Microphone input jack
• One S-Video (PAL/NTSC) connector

t nt
re e
• One Express card jack
ec m
S cu
c Do
• One Mini PCI-E jack for WLAN card
a
T Learning
l
1.3.9 Battery Current Limit i a
M ti
and
en
Implanted H/W current limit and battery learning circuit to enhance protection of battery.
fid
o n
C
37
1.4 Power Management

The 8258I system has built in several power saving modes to prolong the battery usage for mobile purpose. User can
enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2
key). Following are the descriptions of the power management modes supported
1.4.1 System Management Mode

t nt
re e
Full on mode
ec m
S cu
c Do
In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.
a
Doze mode
iT ial
M t
n
In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling.
e
id
This can save battery power without loosing much computing capability. The CPU power consumption and
f
temperature is lower in this mode.
Standby mode
on
C
For more power saving, it turns of the peripheral components. In this mode, the following is the status of each
device:
- CPU: Stop grant
- LCD: Backlight off
38
- HDD: Spin down
Suspend to DRAM/HDD
The most chipset of the system is entering power down mode for more power saving. In this mode, the following is
the status of each device:
• Suspend to DRAM
t nt
re e
c m
- CPU: Off
- Intel 945GM: Partial off
Se u
c Do c
a
- VGA: Suspend
- Audio: Off
iT ial
- SDRAM: Self refresh
M t
en
id
• Suspend to HDD
nf
- All devices are stopped clock and power-down
Co
- System status is saved in HDD
- All system status will be restored when powered on again
39
1.4.2 Other Power Management Functions
HDD & Video access
System has the ability to monitor video and hard disk activity. User can enable monitoring function for video
and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state
t
depending on the application. When the VGA activity monitoring is enabled, the performance of the system will
have some impact.
t
e e n
r
c m
Se u
c Do c
a
iT ial
M t
en
fid
on
C
40
1.5 Appendix 1: Intel ICH7-M GPIO Definitions-1
Default
Pin name Current Define Input/output Function Power Well
GPIO0 PM_BMBUSY# I Bus Master busy CORE
t
GPIO1 PCI_REQ5# I X CORE
t n
GPIO2 PCI_INTE# I PCI interrupt for CORE
re e LAN
c m
GPIO3 PCI_INTF# I X CORE
GPIO4
Se
PCI_INTG#
u
I X CORE
c
GPIO5 PCI_INTH# I X CORE
GPIO6
ac Do
SMB_SEL I ECO Function CORE
iT ial
GPIO7 SCI# I System Control CORE
Interrupt
M t
GPIO8 EXTSMI# I SMI signal for RESUME
n
chipset
e
GPIO9 X I X RESUME
id
GPIO10 X I X RESUME
GPIO11
nf SMBALERT# Native SMBus alert RESUME
o
GPIO12 X I X RESUME
C
GPIO13 X I X RESUME
GPIO14 X I X RESUME
GPIO15 X I X RESUME
GPIO16 DPRSLPVR O Lower power in CORE
deeper sleep
GPIO17 X O X CORE
GPIO18 STOP_PCI# O PCI stop CORE
41
1.5 Appendix 1: Intel ICH7-M GPIO Definitions-2
Continue to the previous page

Default
Pin name Current Define Input/output Function Power Well
GPIO19 PANEL_ID1 I X CORE
t
GPIO20 STOP_CPU# O CPU stop CORE
t n
GPIO22
re e
PCI_REQ4# Native X CORE
c m
GPIO23 X Native X CORE
GPIO24
Se
X
u
O X RESUME
c
GPIO25 X O X RESUME
GPIO26
ac Do
PWM_PWR_ON O ECO Switch RESUME
iT ial
GPIO27 SPK_OFF O Speaker turns off RESUME
GPIO28 X O X RESUME
M t
GPIO29 X Native X RESUME
n
e
id
GPIO32 PCLKRUN# O Clock run CORE
GPIO33
nf WIRELESS_PD# O X CORE
o
GPIO34 X O X CORE
C
GPIO35 X O X CORE
GPIO37 X I X CORE
GPIO38 MB_ID0 I Mother Board ID CORE
GPIO39 MB_ID1 I Mother Board ID CORE
GPIO48 X Native X CORE
GPIO49 HPWRGD Native CPU power good V_CPU_IO
42
1.6 Appendix W83L951DG KBC GPIO Pins Definitions-1
Pin Name Pin 951 Pin Definitions I/O Function 8258I

RESET# 50 RESET# I 951 Chip Reset
TEST# 124 TEST# I Normal operation by direct external rom
XIN 122 System Clock I Crystal use 24 MHZ
t
XOUT 123 System Clock I Crystal use 24 MHZ
t n
XCIN 125 RTC Clock I Crystal use 32.768 KHZ
e e
XCOUT 126 RTC Clock I Crystal use 32.768 KHZ
VCC1 23
r
c m
I +3.3 V
e
GND 32 I Ground
VCC2 60
S cu I Please connect it to +3.3 V from LPC interface
c Do
VCC1 49 I +3.3 V
a
GND 55 I Ground
iT ial
VCC1 78 I +3.3 V
GND 69 I Ground
AVCC 112
M t I Analog Power
n
AVref 103 I Analog reference voltage
AGND 115
e I Analog Ground
id
LPC Interface
LAD3 59
f
LPC_AD3
n
I/O LPC Address/Data I/O 3
o
LAD2 58 LPC_AD2 I/O LPC Address/Data I/O 2
C
SERIRQ 54 SERIRQ Serial Host Interrupt
LRESET# 53 LPC_RESET# LPC Reset
LFRAME# 52 LPC_FRAME# LPC Frame
LCKL 51 PCICLK LPC Clock
Port 0
GP00 94 KB OUT 0 O Key matrix scan output 0
43

t
t n
e e
Port 1
r
c m
e
GP11 85 KB OUT 9
S cu O Key matrix scan output 9
c Do
a
iT ial
GP16 80
M t
KB OUT 14 O Key matrix scan output 14
n
Port 2
e
id
GP20 77 Key Type0 I Keyboard Languag select KBD_US/JP#
GP21 76
nf
Key Type1 I Keyboard Languag select PWRGD
o
GP22 75 M/B ID0 I Reserve for M/B version CRT_DT#
C
GP23 74 M/B ID1 I Reserve for M/B version BATTERY_TYPE
GP24/PWM0 73 +3/5V_GD
GP25/PWM1 72 KBC_BEEP
GP26/PWM2 71 FAN0_ON# O Fan0 power PWM control FANON
GP27/PWM3 70 FAN1_ON# O Fan1 power PWM control
Port 3
GP30 102 KEY IN 0 I Key matrix input 0
44

t
t n
e e
Port 4
r
c m
e
GP40/FAN_TACH0 68 Fan0_SPD I Fan0 speed input FAN_SPEED
GP41/FAN_TACH1 67 Fan1_SPD
S cu I Fan1 speed input
c Do
GP42/RXD 66 RXD I For Firmware debug KBC_RX
a
GP43/TXD 65 TXD O For Firmware debug KBC_TX
iT ial
GP44/KBRST# 64 KBC_HRCIN# O CPU Reset HRCIN#
GP45/GATE_A20 63 A20_GATE O System A20 Gate A20GATE
GP46/CLKRUN# 62
M t
PM_CLKRUN# LPC Clock Run PCLKRUN#
n
GP47/LPCPD# 61 PM_SUS_START LPC Power-Down LPCPD
Port 5
e
id
GP50 121 LSMI# O External SMI# EXTSMI
GP51 120
nf
LSCI O Need invert to SCI# sending to SouthBridge H8_SCI
o
GP52 119 KBC_WAKE# O Wake-up SouthBridge at ACPI mode H8_WAKE_UP#
C
GP53 118 KBC_THRM# O Thermal throttling control to SouthBridge H8_THRM#
GP54 117 WIRE_EN
GP55 116 BLT_DT
GP56/DA0 114 BLADJ O Backlight inverter brightness adjust BLADJ
GP51/DA1 113 I-CTRL O Charging current adjust I_CTRL
Port 6
GP60/AD0 111 BATT_VOLT I Battery voltage meansure BAT_VOLT
GP61/AD1 110 I-Limit I I-Limit function I_LIMIT
45

GP62/AD2 109 3V/PWROK I Monitor system on/off state
GP63/AD3 108 Vtt I System Vtt voltage KBC_VCCP
GP64/AD4 107 BATT_TEMP I Battery thermister temperature BAT_TEMP
t
GP65/AD5 106 V_Core I CPU Vcore voltage KBC_CPUCORE
t n
GP66/AD6 105 I_Charge I Reserve for Internal Gauge
e e
GP67/AD7 104 I_Discharge I Reserve for Internal Gauge
Port 7
r
c m
e
GP70/PS2_1CLK 48 T_CLK I/O TouchPAD Clock T_CLK
GP71/PS2_1DAT 47 T_DATA
S cu I/O TouchPAD Data T_DATA
c Do
GP72/PS2_2CLK 46 T_CLK2 Option for second PS2 interface BLT_EN#
a
GP73/PS2_2DAT 45 T_DATA2 Option for second PS2 interface POWEROK
iT ial
GP74/PS2_3CLK 44 ECOBTN_SW#
GP75/PS2_3DAT 43 PWM_PWR
GP76/SDA0 42
M t
BATT_DATA I/O SMBus Data BAT_DATA
n
GP77/SCL0 41 BATT_CLK I/O SMBus Clock BAT_CLK
Port 8
e
id
GP80/SDA1 40 SMB_DATA1 Reserve for SMBus Data 1 H8_THRM_DATA
GP81/SCL1 39
f
SMB_CLK1
n
Reserve for SMBus Clock 1 H8_THRM_CLK
o
GP82/CNTR0 38 Reserve for Fan0 Speed detect FAN_SPEED_C
C
GP83/CNTR1 37 Prochot# O Indicate Intel CPU to do throttle function
GP84/CIR_RX 36 CIR Receiver
GP85 35 LEARNING# O Auto-Learning LEARNING
GP86 34 CHARGING O Battery charge control CHARGING
GP87 33 KBC_ENABKL O Enable Backlight H8_ENABKL
Port9
GP90 31 KBC_PWRON_VDD3S O Turn on VDD3.3 and VDD1.5 KBC_PWRON_VDD3S
GP91 30 KBC_RSMRST O SouthBridge RSMRST#
46

GP92 29 SB_PWRBTN# O SouthBridge power button
GP93 28 PWRON_1.35V_1.5V O System power on SUSB1.5V
GP94 27 SW_VDD3 O VDD3 power source switch SUSC1.8V
t
GP95 26 PWROK O Reserve for other power sequence pin SW_VDD3
t n
GP96 25 PWRON_VCORE O Reserve for other power sequence pin SUSB_VCC_CORE
e e
GP97 24 PWRON_1.8V_1.25V O Reserve for other power sequence pin SUSB0.9V
Port A
r
c m
e
GPA0/EXTINT10 22 PWRON_5V O Reserve for other power sequence pin OCO5V
GPA1/EXTINT11 21 PWRON_3V
S cu O Reserve for other power sequence pin OCO3V
c Do
GPA2/EXTINT12 20 PWRON_2.5V O Reserve for other power sequence pin SUSB2.5V
a
GPA3/EXTINT13 19 PWRON_1.05V O Reserve for other power sequence pin SUSB_VCCP
iT ial
GPA4/EXTINT14 18 PWRON_+3V_+5V O Reserve for other power sequence pin SUSB3V
GPA5/EXTINT15 17 Reserve for other power sequence pin SUSB5V
GPA6/EXTINT16 16
M t Reserve for other power sequence pin ICH_PWRBTN#
n
GPA7/EXTINT17 15 Reserve for other power sequence pin KBC_RSMRST
Port B
e
id
GPB0/EXTINT20 14 LED_CAP# O Capitals Lock LED indicator CAP#
GPB1/EXTINT21 13
nf
LED_NUM# O Numeral Lock LED indicator NUM#
o
GPB2/EXTINT22 12 LED_SCR# O Scroll Lock LED indicator SCROLL#
C
GPB3/EXTINT23 11 LED_BATT_R# O Battery Charger Red LED indicator BATT_R#
GPB4/EXTINT24 10 LED_BATT_G# O Battery Charger Green LED indicator BATT_G#
GPB5/EXTINT25 9 LED_AC_PWR# O AC Power LED indicator AC_LED#
GPB6/EXTINT26 8 LED_BATT_PWR# O Battery Power LED indicator AC_BAT_POWER#
GPB7/EXTINT27 7 Reserve for other LED indicator ECOBTN_LED#
Port C
GPC0/EXTINT30 6 PWRBTN# I Power Button PWRBTN
47

Invert from SUSA# to wake up KBC when
system resumed by MDC modem and internal
GPC1/EXTINT31 5 KBC_SUSB I LAN. Inform system power management status. KBC_SUSB#
GPC2/EXTINT32 4 KBC_SUSC# I System to S4 (soft off) or S5 SUSC#
GPC3/EXTINT33 3 KBC_ADEN#
t nt I AC adaptor in detect ADEN#
e e
GPC4/EXTINT34 2 BATT_DEAD# I Battery low detect BATT_DEAD#
r
GPC5/EXTINT35 1 COVER_SW# I Cover switch LIDSW#
GPC6/EXTINT36 128
ec m Reserve for other Interrupt pin
S u
GPC7/EXTINT37 127 Reserve for other Interrupt pin
c Do c
a
iT ial
M t
en
fid
on
C
48
2. System View and Disassembly
2.1 System View
2.1.1 Front View

t nt
re e
Top Cover Latch
ec m
External MIC In Connector
S cu
Line In Connector
ac Do

iT ial
Line Out/SPDIF Connector
M t
en
id
2.1.2 Left-side View
CRT Connector
nf
C o
Ventilation Openings

RJ11 Connector
RJ45 Connector
Express Card Socket
49
2.1.3 Right-side View
ODD
USB Ports*2

t nt
re e
ec m
S cu
ac Do
2.1.4 Rear View iT ial
M t
Power Connector
en
S-Video Port
fid
n
USB Ports*2
o

C
Kensington Lock
50
2.1.5 Bottom View

Subwoofer Speaker
Hard Disk Drive
CPU & DDR2 SO-DIMM & Modem
Battery Park
t nt
re e
ec m
S cu
ac Do
2.1.6 Top-open View iT ial
M t
LCD Screen
en
id

Stereo Speaker Set
Internal MIC
nf
C o
Device LED Indicators
Touch Pad

Keyboard
○
Power Button
ECO Button

51
2.2 Tools Introduction
1. Minus screw driver for notebook assembly & disassembly.
t
2 mm
t
e e n
r
c m
Se u
2 mm
c Do c
a
iT ial
M t
2. Auto screw driver for notebook assembly & disassembly.
en
fid
n
Bit Size
Co #0
Screw Size Tooling Tor. Bit Size

1. M2.0 Auto-Screw driver 2.0-2.5 kg/cm2 #0
52
2.3 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations.Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
t nt
notebook is not turned on or connected to AC power.
re e
ec m 2.3.1 Battery Pack
S cu
c Do
2.3.2 Keyboard
a
iT ial
2.3.3 CPU
Modular Components
M t
2.3.4 HDD Module
en 2.3.5 ODD
id
2.3.6 DDR2-SDRAM
nf 2.3.7 LCD Assembly

NOTEBOOK
Co LCD Assembly Components 2.3.8 LCD Panel
2.3.9 Inverter Board
2.3.10 Daughter Board
Base Unit Components 2.3.11 System Board
2.3.12 Modem Card
53
2.3.1 Battery Pack

Disassembly
1. Carefully put the notebook upside down.
2. Slide two release lever outwards to the “unlock” ( ) position (), while take the battery pack out of the
compartment (). (Figure 2-1)
t nt
re e
c m

Se u
c

ac Do
iT ial
M t
en
fid Figure 2-1 Remove the battery pack
on
Reassembly C
1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a
clicking sound.
2. Slide the release lever to the “lock” ( ) position.
54
2.3.2 Keyboard
Disassembly
1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Push firmly to slide the easy start buttons cover to the right (). Then lift the easy start buttons cover up ().
(Figure 2-2)
t
3. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-3)
t
e e n

r
c m
Se u

c Do c
a
iT ial
M t
en
fid
Figure 2-2 Remove the keyboard cover Figure 2-3 Remove the keyboard
on
Reassembly C
1. Reconnect the keyboard cable and fit the keyboard back into place.
2. Replace the easy start buttons cover.
3. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
55
2.3.3 CPU
Disassembly
1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove eight screws fastening the CPU cover. (Figure 2-4)
3. Remove four spring screws that secure the heatsink upon the CPU and disconnect the fan’s power cord from
t
system board. (Figure 2-5)
t
e e n
r
c m
Se u
c Do c
a
iT ial
M t
en
fid
on
Figure 2-4 Remove eight screws Figure 2-5 Free the heatsink
56
4. To remove the existing CPU, loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU.
(Figure 2-6)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
Figure 2-6 Remove the CPU
en
fid
Reassembly
on
C
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into
the holes. Tighten the screw by a flat screwdriver to locking the CPU.
2. Connect the fan’s power cord to the system board, fit the heatsink upon the CPU and secure with seven spring
screws.
3. Replace the CPU cover and secure with eight screws.
57
2.3.4 HDD Module

Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove two screws fastening the HDD compartment cover. (Figure 2-7)
3. Remove one screw fastening the HDD module. Slide the HDD module out of the compartment. (Figure 2-8)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
n
Figure 2-7 Remove the HDD
o
compartment cover
Figure 2-8 Remove HDD module
58
4. Remove four screws to separate the hard disk drive from the bracket, remove the hard disk drive. (Figure 2-9)
t nt
re e
ec m
S cu
ac Do
iT ial Figure 2-9 Remove hard disk drive
M t
en
Reassembly
fid
on
1. Attach the bracket to hard disk drive and secure with four screws.
C
2. Slide the HDD module into the compartment and secure with one screw.
3. Place the HDD compartment cover and secure with two screws.
59
2.3.5 ODD
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove one screw fastening the ODD. (Figure 2-10)
3. Insert a small rod, such as a straightened paper clip, into ODD’s manual eject hole () and push firmly to
t nt
release the tray. Then gently pull out the ODD by holding the tray that pops out (). (Figure 2-10)
re e
ec m
S cu
ac Do
iT ial
M t
en
id

nf
o
Figure 2-10 Remove the ODD
C
Reassembly
1. Push the ODD into the compartment and secure with one screw.
60
2.3.6 DDR2-SDRAM
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (See section 2.3.1 Disassembly)
2. Remove eight screws fastening the CPU cover. (Refer to step 2 of section 2.3.3 Disassembly)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en Figure 2-11 Remove the SO-DIMM
fid
n
3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-11)
Reassembly
Co
1. To install the DDR2, match the DDR2's notched part with the socket's projected part and firmly insert the
SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR2 into
position.
2. Replace the CPU cover and secure with eight screws. (Refer to step 3 of section 2.3.3 Reassembly)
3. Replace the battery pack. (See section 2.3.1 Reassembly)
61
2.3.7 LCD Assembly

Disassembly
1. Remove the battery pack and keyboard. (See sections 2.3.1 and 2.3.2 Disassembly)
2. Remove eight screws fastening the CPU cover. (Refer to step 2 of section 2.3.3 Disassembly)
3. Separate the antenna from the system board. (Figure 2-12)
t nt
4. Remove two hinge covers, disconnect two cables from the system board then carefully pull the antenna wires out.
e e
(Figure 2-13)
r
c m
Se u
c Do c
a
iT ial
M t
en
fid
on
C
Figure 2-12 Separate the antenna Figure 2-13 Remove two hinge covers
and disconnect two cables
62
5. Remove four screws, then free the LCD assembly. (Figure 2-14)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
Figure 2-14 Free the LCD assembly
en
fid
Reassembly
on
C
1. Attach the LCD assembly to the base unit and secure with four screws.
2. Replace the antenna wires back.
3. Reconnect two cables to the system board. Then replace two hinge covers.
4. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)
63
2.3.8 LCD Panel

Disassembly
1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.3.1, 2.3.2 and 2.3.7 Disassembly)
2. Remove two screws on the corners of the panel. (Figure 2-15)
3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process
t
until the cover is completely separated from the housing.
t n
4. Remove six screws and disconnect the cable. (Figure 2-16)
e e
r
c m
Se u
c Do c
a
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M t
en
fid
on
C
Figure 2-15 Remove LCD cover Figure 2-16 Remove six screws and
disconnect the cable
64
5. Remove eight screws that secure the LCD brackets. (Figure 2-17)
6. Disconnect the cable to free the LCD panel. (Figure 2-18)
t nt
re e
ec m
S cu
ac Do
iT ial
Figure 2-17 Remove eight screws Figure 2-18 Free the LCD panel
M t
en
fid
n
Reassembly
Co
1. Replace the cable to the LCD panel.
2. Attach the LCD panel’s brackets back to LCD panel and secure with eight screws.
3. Replace the LCD panel into LCD housing and secure with six screws.
4. Reconnect one cable to inverter board.
5. Fit the LCD cover and secure with two screws and rubber pads.
6. Replace the LCD assembly, keyboard and battery pack. (See sections 2.3.7, 2.3.2 and 2.3.1 Reassembly)
65
2.3.9 Inverter Board

Disassembly
1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.3.1, 2.3.2 and 2.3.7 Disassembly)
2. Remove the LCD cover and LCD panel. (Refer to the steps 1-4 of section 2.3.8 Disassembly )
3. Remove three screws fastening the inverter board to free it. (Figure 2-19)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
id
Figure 2-19 Free the inverter board
nf
Reassembly Co
1. Fit the inverter board back into place and secure with three screws.
2. Replace the LCD panel and LCD cover. (Refer to section 2.3.8 Reassembly)
3. Replace the LCD assembly. (Refer to section 2.3.7 Reassembly)
4. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)
66
2.3.10 Daughter Board

Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, ODD, DDR2 and LCD assembly. (Refer to sections 2.3.1,
2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6 and 2.3.7 Disassembly)
2. Remove fifteen screws. (Figure 2-20)
t
3. Disconnect two speakers’ cables and touch pad cable from the system board and remove four screws. (Figure 2-21)
t
e e n
r
c m
Se u
c Do c
a
iT ial
M t
en
fid
on
Figure 2-20 Remove fifteen Screws Figure 2-21 Disconnect two cables and
C remove four screws
67
4. Remove two screws fixing the system board. Then free the cover assembly. (Figure 2-22)
5. Remove one screw fixing the daughter board. (Figure 2-23)
t nt
re e
ec m
S cu Figure 2-23 Free the system board
c Do
Figure 2-22 Remove two hex nuts
a
iT ial
M t
6. Disconnect two daughter board cables. Then free the daughter board. (Figure 2-24)
en
fid
on
C
Figure 2-24 Disconnect two cables
68
Reassembly
1. Replace the daughter board and reconnect two cables.
2. Secure with one screw.
3. Replace the cover assembly and secure with four screws. Reconnect two speakers’ cables and touch pad cable.
4. Turn over the base unit. Secure with fifteen screws and reconnect two hex nuts.
5. Replace the LCD assembly, DDR2, ODD, hard disk drive, CPU, keyboard and battery pack. (Refer to previous
section reassembly)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
C
69
2.3.11 System Board

Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, ODD, DDR2 and LCD assembly. (Refer to sections 2.3.1,
2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6 and 2.3.7 Disassembly)
2. Remove three screws, then free the mother board. (Figure 2-25)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
id
Figure 2-25 Remove three screws
nf
Reassembly
Co
1. Replace the system board and reconnect three screws.
2. Replace the cover assembly and secure with four screws to fix the system board. Reconnect two speakers’ cables
and touch pad cable.
3. Turn over the base unit. Secure with fifteen screws and reconnect two hex nuts.
5. Replace the LCD assembly, DDR2, ODD, hard disk drive, CPU, keyboard and battery pack. (Refer to previous
section reassembly)
70
2.3.12 Modem Card

Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, ODD, DDR2, LCD assembly and system board. (Refer to
sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.7 and 2.3.11 Disassembly)
2. Disconnect the cable and remove two screws, then free the modem card. (Figure 2-26)
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
id
Figure 2-26 Remove the modem card
nf
Reassembly Co
1. Replace the modem card back into the system board and secure with two screws, then reconnect the cable.
2. Replace the system board, LCD assembly, DDR2, ODD, hard disk drive, CPU, keyboard and battery pack.
(Refer to previous section reassembly)
71
3. Definition & Location of Connectors/Switches
3.1 Mother Board (Side A)
t
J505
nt J511
J501: CRT Connector
J501 J504
re e
c m
PJ501: Battery Connector
e
J502
S cu J502: Fan Connector
ac Do J507 PJ502, J503: MB to DB Connector
iT ial
J504: MDC Jump Wire Connector
M t
J505: RJ11/RJ45 Connector
en J506: ODD Connector
id
J507: MDC Connector
nf J508, J509: DDR2 SO-DIMM Socket

PJ501
Co
J503
J508 J509 J512
J513
J510: HDD Connector
J511: Mini PCI-E Connector

PJ502 J514
J512: External MIC In Connector
J506
J510 J513: Line In Connector
J514: Line Out Connector
72
3.1 Mother Board (Side B)
t nt J1: LCD Connector

MIC1
re e
c m
J8 J2: Left Audio Channel Connector
Se u J3: LCD Inverter Board Connector
c
J1
c Do
J2
J4: Internal Keyboard Connector
a
iT ial
J6: Touch Pad Connector
J9 J3
M t
J7: Blue Tooth Connector
SW1
en J8: Express Card Socket
id
J9: CMOS Battery Connector
nf J10: X10 Connector
SW2
Co
J6
J4
SW1: Touch Pad Left Button
J10 J7
SW2: Touch Pad Right Button
73
3.2 Daughter Board (Side A)
t nt AKPJ501: Power Jack

AKPJ501
re e
c m
AKPJ502, AKJ503: DB to MB Connector
e
AKJ501
S cu AKJ502 AKJ501: S-Video Port
AKJ504
ac Do
AKJ503
AKJ502, AKJ504: USB Port
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M t
AKPJ502
en
fid
on
C
74
3.2 Daughter Board (Side B)
t nt AKJ1: Right Audio Channel Connector
re e
c m
AKSW1
e
AKSW2 AKJ1
S cu AKSW1: LID Switch
AKSW3
ac Do AKSW2: ECO Button
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AKSW3: Power Switch Button
M t
en
fid
on
C
75
4. Definition & Location of Major Components
4.1 Mother Board (Side A)
t nt U503 : Intel Yonah Processor
re e
c m
U512 U506 : Intel 945GM North Bridge
e
U510
S u
U510: MDC
c Do c U514
U512: TPS2231 New Card
a
iT ial
U513 : W83L951D Keyboard Controller
M t
U514 : RTL8100CL LAN Controller
U503 U506 U515
en U515 : Intel ICH7-M South Bridge
id
U518 : Audio Codec ALC883
nf
Co U513
U518
76
4. Definition & Location of Major Components
4.2 Mother Board (Side B)
t nt U6 : System BIOS
re e
ec m
S cu
ac Do
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U6
M t
en
fid
on
C
77
5. Pin Descriptions of Major Components
5.1 Intel Yonah Processor CPU (1)

CPU Pin Description CPU Pin Description (Continued)
Signal Name
A[31:3]#
Type
I/O
Description
t nt
A[31:]#(Address) define a 2*32- byte physical memory address
Signal Name Type
I/O
Description
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
e e
BPM[2:1]#
space. In sub-phase 1 of the address phase, these pins transmit the BPM[3,0]# monitor signals. They are outputs from the processor that indicate the
r
address of a transaction. Must connect the appropriate pins of both status of breakpoints and programmable counters used for monitoring
c m
agents on the Intel Core TM Duo processor and the Intel Core TM processor performance. BPM[3:0]# should connect the appropriate
e
Solo processor FSB. A[31:3]# are source synchronous signals and are pins of all Intel Pentium M processor system bus agents. This
S u
latched into the receiving buffers by ADSTB[1:0]#. Address signals includes debug or performance monitoring tools.
c
are used as straps which are sampled before RESET# is deasserted. BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
c Do
A20M# I If A20M#(Address-20 Mask) is asserted, the processor masks processor system bus. It must connect the appropriate pins of both
a
physical address bit 20(A20#) before looking up a line in any internal processor system bus agents. Observing BPRI# active (as asserted by
cache and before driving a read/write transaction on the bus. the priority agent) causes the other agent to stop issuing new requests,
iT ial
Asserting A20M# emulates the 8086 processor’s address wrap-around unless such requests are part of an ongoing locked operation. The
at the 1-Mbyte boundary. Assertion of A20M# is only supported in priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting BPRI#.
M t
real mode.
A20M# is an asynchronous signal. However, to ensure recognition of BR0# I/O BR0# is used by the processor to request the bus. The arbitration is
done between the Intel Pentium M processor (Symmetric Agent) and
n
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding the Mobile Intel 945 Express chipset family (High Priority Agent).
e
Input/Output Write bus transaction. BSEL[2:0] O BSEL[2:0] (Bus SELECT) are used to select the processor input
id
ADS# I/O ADS#(Address Strobe) is asserted to indicate the validity of the clock frequency. The table defines the possible combinations of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus signals and the frequency associated with each combination. The
f
agents observe the ADS# activation to begin parity checking, protocol required frequency is determined by the processor, chipset and clock
n
checking, address decode, internal snoop, or deferred reply ID match synthesizer. All agents must operate at the same frequency. The
processor operates at 667 MHz or 533 MHz system bus frequency
o
operations associated with the new transaction.
ADSTB# I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their (166MHz or 133MHz BCLK[1:0] frequency, respectively).
C
rising and falling edges. Strobes are associated with signals as shown BSE[2:0] Encoding for BCLK Frequency
below. BCLK
BSEL[2] BSEL[1] BSE[0]
Signals Associated Strobe Frequency
REQ[4:0]#, A[16:3]# ADSTB[0]# L L L Reserved
A[31:17]# ADSTB[1]# L L H 133MHz
BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the system bus L H L Reserved
frequency. All processor system bus agents must receive these signals L H H 166MHz
to drive their outputs and latch their inputs. COMPP3:0] Analog COMP[3:0] must be terminated on the system board using precision
BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus (1% tolerance) resistors. Refer to the platform design guides for more
agent that is unable to accept new bus transactions. During a bus stall, implementation details.
the current bus owner cannot issue any new transactions.
78

CPU Pin Description (Continued) CPU Pin Description (Continued)
Signal Name Type Description Signal Name Type Description
D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit DINV[3:0]# I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and
data path between the processor system bus agents, and must connect indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals
the appropriate pins on both agents. The data driver asserts DRDY# are activated when the data on the data bus is inverted. The bus agent
to indicate a valid data transfer. will invert the data bus signals if more than half the bits, within the
D[63:0]# are quad-pumped signals and will thus be driven four covered group, would change level in the next cycle.
t
times in a common clock period. D[63:0]# are latched off the falling DINV[3:0]# Assignment To Data Bus
t
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 Bus Signal Data Bus Signals
n
data signals correspond to a pair of one DSTBP# and one DSTBN#. DINV[3]# D[63:48]#
e e
The following table shows the grouping of data signals to data DINV[2]# D[47:32]#
r
strobes and DINV#. DINV[1]# D[31:16]#
c m
Quad-Pumped Signal Groups DINV[0]# D[15:0]#
e
Data Group DSTBN#/DSTBP# DINV# DPRSTP# I DPRSTP# when asserted on the platform causes the processor to
S u
D[15:0]# 0 0 transition from the Deep Sleep State to the Deeper Sleep Stated. In
c
D[31:16]# 1 1 order to return to the Deep Sleep State, DPRSTP# must be deasserted.
c Do
D[47:32]# 2 2 DPRSTP# is driven by the Intel ICH7M chipset.
a
D[63:48]# 3 3 DPSLP# I DPSLP# when asserted on the platform causes the processor to
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Furthermore, the DINV# pins determine the polarity of the data transition from the Sleep state to the Deep Sleep state. In order to
signals. Each group of 16 data signals corresponds to one DINV# return to the Sleep state, DPSLP# must be deasserted. DPSLP# is
signal. When the DINV# signal is active, the corresponding data driven by the ICH7M chipset.
M t
group is inverted and therefore sampled active high. DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data
DBR# O DBR# (Data Bus Reset) is used only in processor systems where no transfer, indicating valid data on the data bus. In a multi-common
n
debug port is implemented on the system board. DBR# is used by a clock data transfer, DRDY# may be deasserted to insert idle clocks.
e
debug port interposer so that an in-target probe can drive system This signal must connect the appropriate pins of both processor
reset. If a debug port is implemented in the system, DBR# is a no system bus agents.
id
connect. DBR# is not a processor signal. DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#.
f
DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for Signals Associated Strobe
driving data on the processor system bus to indicate that the data bus D[15:0]#, DINV[0]# DSTBN[0]#
n
is in use. The data bus is released after DBSY# is deasserted. This D[31:16]#, DINV[1]# DSTBN[1]#
o
signal must connect the appropriate pins on both processor system D[47:32]#, DINV[2]# DSTBN[2]#
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bus agents. D[63:48]#, DINV[3]# DSTBN[3]#
DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot
be guaranteed in-order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or Input/Output agent.
This signal must connect the appropriate pins of both processor
system bus agents.
79

DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to
Signals Associated Strobe ignore a numeric error and continue to execute noncontrol
D[15:0]#, DINV[0]# DSTBP[0]# floating-point instructions. If IGNNE# is deasserted, the processor
D[31:16]#, DINV[1]# DSTBP[1]# generates an exception on a noncontrol floating-point instruction if a
D[47:32]#, DINV[2]# DSTBP[2]# previous floating-point instruction caused an error. IGNNE# has no
t
D[63:48]#, DINV[3]# DSTBP[3]# effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
t n
FERR#/PBE# O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a
of this signal following an Input/Output write instruction, it must be
e e
multiplexed signal and its meaning is qualified by STPCLK#. When
valid along with the TRDY# assertion of the corresponding
r
STPCLK# is not asserted, FERR#/PBE# indicates a floating point
Input/Output Write bus transaction.
when the processor detects an unmasked floating-point error. FERR#
c m
is similar to the ERROR# signal on the Intel 80387 coprocessor, and INIT# I INIT#(Initialization), when asserted, resets integer registers inside the
e
is included for compatibility with systems using MS-DOS* type processor without affecting its internal caches or floating-point
S u
floating-point error reporting. When STPCLK# is asserted, an registers, The processor then begins execution at the power-on Reset
c
assertion of FERR#/PBE# indicates that the processor has a pending vector configured during power-on configuration. The processor
c Do
break event waiting for service. The assertion of FERR#/PBE# continues to handle snoop requests during INIT# assertion. INIT# is
an asynchronous signal. However, to ensure recognition of this signal
a
indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will following an Input/Output Write Instruction, it must be valid along
iT ial
with the TRDY# assertion of the corresponding Input/Output Write
remain asserted until STPCLK# is deasserted. Assertion of PREQ#
when STPCLK# is active will also cause an FERR# break event. bus transaction, INIT# must connect the appropriate pins of both FSB
agents.
M t
For additional information on the pending break event functionality,
If INIT# is sampled active on the active to inactive transition of
including identification of support of the feature and enable/disable
RESET#, then the processor executes its Built-in Selt-Test(BIST).
n
information, refer to Volume 3 of the Intel Architecture Software
Developer’s Manual and AP-485, For termination requirements LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
e
please contact your Intel representative. of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
id
GTLREF I GTLREF determines the signal reference level for AGTL+ input pins.
becomes NMI, a nonmaskable interrupt. INTR and NMI are
GTLREF should be set at 2/3 VCCP . GTLREF is used by the
f
backward compatible with the signals of those names on the Pentium
AGTL+ receivers to determine if a signal is a logical 0 or logical
processor. Both signals are asynchronous.
n
1.Plese contact your Intel representative for more information
Both of these signals must be software configured using BIOS
o
regarding GTLREF implementation.
programming of the APIC register space and used either as
HIT# I/O HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
C
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default
HITM# I/O snoop operation results. Either system bus agent may assert both
after Reset, operation of these pins as LINT[1:0] is the default
HIT# and HITM# together to indicate that it requires a snoop stall,
configuration.
which can be continued by reasserting HIT# and HITM# together.
LOCK# I/O LOCK# indicates to the system that a transaction must occur
IERR# O IERR# (Internal Error) is asserted by a processor as the result of an
atomically. This signal must connect the appropriate pins of both
internal error. Assertion of IERR# is usually accompanied by a processor system bus agents. For a locked sequence of transactions,
SHUTDOWN transaction on the processor system bus. This LOCK# is asserted from the beginning of the first transaction to the
transaction may optionally be converted to an external error signal end of the last transaction.
(e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#, BINIT#, or INIT#.
80

LOCK# I/O When the priority agent asserts BPRI# to arbitrate for ownership of RESET# I On observing active RESET#, both system bus agents will deassert
the processor system bus, it will wait until it observes LOCK# their outputs within two clocks. All processor straps must be valid
deasserted. This enables symmetric agents to retain ownership of the within the specified setup time before RESET# is deasserted.
processor system bus throughout the bus locked operation and ensure There is a 55 (normal) on die pull up resistor on this signal.
the atomicity of lock. RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the
t
PRDY# O Probe Ready signal used by debug tools to determine processor debug agent
t
readiness. responsible for completion of the current transaction), and must
n
PREQ# I Probe Request signal used by debug tools to request debug operation connect the appropriate pins of both processor system bus agents.
e e
of the processor. RSVD Reserved/ These pins are RESERVED and must be left unconnected on the
r
PROCHOT# I/O As an output, PROCHOT# (Processor Hot) will go active when the No Connect board.
c m
processor temperature monitoring sensor detects that the processor However, it is recommended that routing channels to these pins on
e
has reached its maximum safe operating temperature. This indicates the board be kept open for possible future use. Please refer to the
S u
that the processor Thermal Control Circuit has been activated, if platform design guides for more details.
c
enabled. As an input, assertion of PROCHOT# by the system will SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor
c Do
activate the TCC, if enabled. TCC will remain active until the system to enter the Sleep state. During Sleep state, the processor stops
a
deasserts PRCCHOT#. providing internal clock signals to all units, leaving only the
By default PROCHOT# is configured as an output only. Bidirectional Phase-Locked Loop (PLL) still operating. Processors in this state will
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PROCHOT# must be enabled via the BIOS. not recognize snoops or interrupts. The processor will recognize only
This signal may require voltage translation on the motherboard. assertion of the RESET# signal, deassertion of SLP#, and removal of
PSI# O Processor Power Status Indicator signal. This signal is asserted when the BCLK input while in Sleep state. If SLP# is deasserted, the
M t
the processor is in a lower state (HFM and LFM) and lower state processor exits Sleep state and returns to Stop-Grant state, restarting
(Deep Sleep and Deeper Sleep). its internal clock signals to the bus and processor core units. If
n
PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor DPSLP# is asserted while in the Sleep state, the processor will exit
e
requires this signal as a clean indication that the clocks and power the Sleep state and transition to the Deep Sleep state.
id
supplies are stable and within their specifications. ‘Clean’ implies that SMI# I SMI# (System Management Interrupt) is asserted asynchronously by
the signal will remain low (capable of sinking leakage current), system logic. On accepting a System Management Interrupt, the
f
without glitches, from the time that the power supplies are turned on processor saves the current state and enter System Management Mode
n
until they come within specification. The signal must then transition (SMM). An SMI Acknowledge transaction is issued, and the
monotonically to a high state. processor begins program execution from the SMM handler.
o
The PWRGOOD signal must be supplied to the processor; it is used If SMI# is asserted during the deassertion of RESET# the processor
C
to protect internal circuits against voltage sequencing issues. It should will tristate its outputs.
be driven high throughout the boundary scan operation. STPCLK# I STPCLK# (Stop Clock), when asserted, causes the processor to enter
REQ[4:0] I/O REQ[4:0]#(Request Command) must connect the appropriate pins of a low power Stop-Grant state. The processor issues a Stop-Grant
both FSB agents. They are asserted by the current bus owner to the Acknowledge transaction, and stops providing internal clock signals
currently active transaction type. These signals are source to all processor core units except the system bus and APIC units. The
synchronous to ADSTB[0]#. processor continues to snoop bus transactions and service interrupts
RESET# I Asserting the RESET# signal resets the processor to a known state while in Stop-Grant state. When STPCLK# is deasserted, the
and invalidates its internal caches without writing back any of their processor restarts its internal clock to all units and resumes execution.
contents. For a power-on Reset, RESET# must stay active for at least The assertion of STPCLK# has no effect on the bus clock; STPCLK#
two milliseconds after VCC and BCLK have reached their proper is an asynchronous input.
specifications.
81

TCK I TCK (Test Clock) provides the clock input for the processor Test Bus Vsssense O Vsssense together with Vccsense are voltage feedback signals to
(also known as the Test Access Port). IMVP6 that control the 2.1m loadline at the processor die. It should
TDI I TDI (Test Data In) transfers serial test data into the processor. TDI be used to sense ground near the silicon with little noise.
provides the serial input needed for JTAG specification support.
TDO O TDO (Test Data Out) transfers serial test data out of the processor.
t
TDO
t
provides the serial output needed for JTAG specification support.
TEST1, I
e e n
TEST1 must have a stuffing option of separate pull down resistor to
r
Vss.
TEST2 I TEST2 must have a 51±5% pull down resistor to Vss.
THERMDA Other Thermal Diode Anode.
ec m
S u
THERMDC Other Thermal Diode Cathode.
c
THERMTRIP# O The processor protects itself from catastrophic overheating by use of
c Do
an internal thermal sensor. This sensor is set well above the normal
a
operating temperature to ensure that there are no false trips. The
iT ial
processor will stop all execution when the junction temperature
exceeds approximately 125°C. This is signalled to the system by the
THERMTRIP# (Thermal Trip) pin.
M t
TMS I TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
n
TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is
e
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
id
TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
f
must be driven low during power on Reset.
Vcc I Processor core power supply.
Vcca
Vccp
I
I n
Vcca provides isolated power for the internal processor core PLL’s.
o
Processor I/O Power Supply.
VID[6:0] O
C
VID[6:0] (Voltage ID) pins are used to support automatic selection of
power supply voltages (Vcc). Unlike some previous generations of
processors, these are CMOS signals that are driven by the Intel
Pentium M processor. The voltage supply for these pins must be valid
before the VR can supply Vcc to the processor. Conversely, the VR
output must be disabled until the voltage supply for the VID pins
becomes valid. The VID pins are needed to support the processor
voltage specification variations. The VR must supply the voltage that
is requested by the pins, or disable itself.
82
5.2 Intel 945GM North Bridge (1)

Host Interface Signals Host Interface Signals (Continued)
HADS# I/O Address Strobe: HDRDY# I/O Data Ready:
GTL+ The processor bus owner asserts HADS# to indicate the first of two GTL+ This signal is asserted for each cycle that data is transferred.
cycles of a request phase. The (G)MCH can assert this signal for HEDRDY# O Early Data Ready:
snoop cycles and interrupt messages. GTL+ This signal indicates that the data phase of a read transaction will start
HBNR# I/O Block Next Request: on the bus exactly one common clock after assertion.
t
GTL+ HBNR# is used to block the current request bus owner from issuing HDINV[3:0]# I/O Dynamic Bus Inversion:
t
new requests. This signal is used to dynamically control the processor GTL+ These signals are driven along with the HD[63:0] signals. They
n
bus pipeline depth. indicate if the associated signals are inverted or not.
e e
HBPRI# O Priority Agent Bus Request: HDINV[3:0]# are asserted such that the number of data bits driven
r
GTL+ The (G)MCH is the only Priority Agent on the processor bus. It electrically low (low voltage) within the corresponding 16 bit group
c m
asserts this signal to obtain the ownership of the address bus. This never exceeds 8..
e
signal has priority over symmetric bus requests and will cause the HDINV[x]# Data Bits
S u
current symmetric owner to stop issuing new transactions unless the HDINV3# HD[63:48]
c
HLOCK# signal was asserted. HDINV2# HD[47:32]
c Do
HBREQ0# I/O Bus Request 0: HDINV1# HD[31:16]
a
GTL+ The (G)MCH pulls the processor’s bus HBREQ0# signal low during HDINV0# HD[15:0]
HCPURST#. The processor samples this signal on the HA[31:3]# I/O Host Address Bus:
iT ial
active-toinactive transition of HCPURST#. The minimum setup time GTL+ HA[31:3]# connect to the processor address bus.
for this signal is 4 HCLKs. The minimum hold time is 2 HCLKs and During processor cycles, the HA[31:3]# are inputs. The (G)MCH
M t
the maximum hold time is 20 HCLKs. HBREQ0# should be tristated drives HA[31:3]# during snoop cycles on behalf of DMI and PCI
after the hold time requirement has been satisfied. Express* initiators.
n
HCPURST# O CPU Reset: HA[31:3]# are transferred at 2x rate.
e
GTL+ The HCPURST# pin is an output from the (G)MCH. The (G)MCH HADSTB[1:0]# I/O Host Address Strobe:
asserts HCPURST# while RSTIN# is asserted and for approximately GTL+ These signals are the source synchronous strobes used to transfer
id
1 ms after RSTIN# is de-asserted. The HCPURST# allows the HA[31:3]# and HREQ[4:0] at the 2x transfer rate.
f
processors to begin execution in a known state. HD[63:0]# I/O Host Data:
Note that the Intel® ICH7 must provide processor frequency select GTL+ These signals are connected to the processor data bus. Data on
n
strap setup and hold times around HCPURST#. This requires strict HD[63:0] is transferred at 4x rate. Note that the data signals may be
o
synchronization between (G)MCH HCPURST# de-assertion and the inverted on the processor bus, depending on the HDINV[3:0]#
ICH7 driving the straps.
C
signals.
HDBSY# I/O Data Bus Busy: HHIT# I/O Hit:
GTL+ This signal is used by the data bus owner to hold the data bus for GTL+ This signal indicates that a caching agent holds an unmodified version
transfers requiring more than one cycle. of the requested line. In addition, HHIT# is driven in conjunction with
HDEFER# O Defer: HHITM# by the target to extend the snoop window.
GTL+ HDEFER# indicates that the (G)MCH will terminate the transaction
currently being snooped with either a deferred response or with a
retry response.
83

Host Interface Signals (Continued) Host Interface Signals (Continued)
HDSTBP[3:0]# I/O Differential Host Data Strobes: HTRDY# O Host Target Ready:
HDSTBN[3:0]# GTL+ These signals are the differential source synchronous strobes used to GTL+ This signal indicates that the target of the processor transaction is able
transfer HD[63:0]# and HDINV[3:0]# at 4x transfer rate. to enter the data transfer phase.
These signals are named this way because they are not level sensitive. HRS[2:0]# O Host Response Status:
Data is captured on the falling edge of both strobes. Hence they are GTL+ These signals indicate the type of response as shown below:
t
pseudo-differential, and not true differential. 000 = Idle state
t
Strobe Data Bits 001 = Retry response
n
HDSTBP3#, HDSTBN3# HD[63:48] HDINV3# 010 = Deferred response
e e
HDSTBP2#, HDSTBN2# HD[47:32] HDINV2# 011 = Reserved (not driven by (G)MCH)
r
HDSTBP1#, HDSTBN1# HD[31:16] HDINV1# 100 = Hard Failure (not driven by (G)MCH)
c m
HDSTBP0#, HDSTBN0# HD[15:00] HDINV0# 101 = No data response
e
HHITM# I/O Hit Modified: 110 = Implicit Write back
S u
GTL+ This signal indicates that a caching agent holds a modified version of 111 = Normal data response
c
the requested line and that this agent assumes responsibility for BSEL[2:0] I Bus Speed Select:
c Do
providing the line. In addition, HHITM# is driven in conjunction with COMS At the de-assertion of RSTIN#, the value sampled on these pins
a
HHIT# to extend the snoop window. determines the expected frequency of the bus.
HLOCK# I/O Host Lock: HRCOMP I/O Host RCOMP:
iT ial
GTL+ All processor bus cycles sampled with the assertion of HLOCK# COMS This signal is used to calibrate the Host GTL+ I/O buffers.
and HADS#, until the negation of HLOCK# must be atomic (i.e., no This signal is powered by the Host Interface termination rail (VTT).
M t
DMI or PCI Express accesses to DRAM are allowed when HLOCK# HSCOMP I/O Slew Rate Compensation:
is asserted by the processor). COMS This is the compensation signal for the Host Interface.
n
HPCREQ# I Precharge Request: HSWING I Host Voltage Swing:
e
GTL+ The processor provides a “hint” to the (G)MCH that it is OK to close A This signal provides the reference voltage used by FSB RCOMP
2X the DRAM page of the memory read request with which the hint is circuits. HSWING is used for the signals handled by HRCOMP.
id
associated. The (G)MCH uses this information to schedule the read HDVREF I Host Reference Voltage:
f
request to memory using the special “AutoPrecharge” attribute. This A Voltage input for the data, address, and common clock signals of the
causes the DRAM to immediately close (Precharge) the page after the Host GTL interface.
n
read data has been returned. This allows subsequent processor HACCVREF I Host Reference Voltage:
o
requests to more quickly access information on other DRAM pages, A Reference voltage input for the Address, and Common clock signals
since it will no longer be necessary to close an open page prior to
C
of the Host GTL interface.
opening the proper page. Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
HPCREQ# is asserted by the requesting agent during both halves of voltage of the Host Bus (VTT).
Request Phase. The same information is provided in both halves of
the request phase.
HREQ[4:0]# I/O Host Request Command:
GTL+ These signals define the attributes of the request. HREQ[4:0]# are
2X transferred at 2x rate. They are asserted by the requesting agent
during both halves of Request Phase. In the first half, the
signals define the transaction type to a level of detail that is sufficient
to begin a snoop request. In the second half, the signals carry
additional information to define the complete transaction type.
84

DDR2 DRAM Channel A Interface DDR2 DRAM Channel A Interface (Continued)
SCLK_A[5:0] O SDRAM Differential Clock: SDQS_A[7:0]# I/O Data Strobe Complements:
SSTL-1.8 (3 per DIMM). SCLK_Ax and its complement SCLK_Ax# signal SSTL-1.8 These are the complementary DDR2 strobe signals.
make a differential clock pair output. The crossing of the positive 2X
edge of SCLK_Ax and the negative edge of its complement SCKE_A[3:0] O Clock Enable:
SCLK_Ax# are used to sample the command and control signals on SSTL-1.8 (1 per Rank). SCKE_Ax is used to initialize the SDRAMs during
t
the SDRAM. power-up, to power-down SDRAM ranks, and to place all SDRAM
t
SCLK_A[5:0]# O SDRAM Complementary Differential Clock: ranks into and out of self-refresh during Suspend-to-RAM.
n
SSTL-1.8 (3 per DIMM). These are the complementary Differential DDR2
e e
SODT_A[3:0] O On Die Termination:
Clock signals. SSTL-1.8 Active On-die Termination Control signals for DDR2 devices.
r
SCS_A[3:0]# O Chip Select:
c m
SSTL-1.8 (1 per Rank). These signals select particular SDRAM components
e
during the active state. There is one chip select for each SDRAM
S u
rank.
c
SMA_A[13:0] O Memory Address:
DDR2 DRAM Channel B Interface
c Do
SSTL-1.8 These signals are used to provide the multiplexed row and column Signal Name Type Description
a
address to the SDRAM. SCLK_B[5:0] O SDRAM Differential Clock:
SSTL-1.8 (3 per DIMM). SCLK_Bx and its complement SCLK_Bx# signal
iT ial
SBS_A[2:0] O Bank Select:
SSTL-1.8 These signals define which banks are selected within each SDRAM make a differential clock pair output. The crossing of the positive
rank. edge of SCLK_Bx and the negative edge of its complement
M t
DDR2: 1-Gb technology is 8 banks. SCLK_Bx# are used to sample the command and control signals on
SRAS_A# O Row Address Strobe: the SDRAM.
n
SSTL-1.8 This signal is used with SCAS_A# and SWE_A# (along with SCLK_B[5:0]# O SDRAM Complementary Differential Clock:
e
SCS_A#) to define the SDRAM commands. SSTL-1.8 (3 per DIMM). These are the complementary Differential DDR2
SCAS_A# O Column Address Strobe: Clock signals.
id
SSTL-1.8 This signal is used with SRAS_A# and SWE_A# (along with SCS_B[3:0]# O Chip Select:
f
SCS_A#) to define the SDRAM commands. SSTL-1.8 (1 per Rank). These signals select particular SDRAM components
SWE_A# O Write Enable: during the active state. There is one chip select for each SDRAM
n
SSTL-1.8 This signal is used with SCAS_A# and SRAS_A# (along with rank.
o
SCS_A#) to define the SDRAM commands. SMA_B[13:0] O Memory Address:
C
SDQ_A[63:0] I/O Data Lines: SSTL-1.8 These signals are used to provide the multiplexed row and column
SSTL-1.8 The SDQ_A[63:0] signals interface to the SDRAM data bus. address to the SDRAM.
2X SBS_B[2:0] O Bank Select:
SDM_A[7:0] O Data Mask: SSTL-1.8 These signals define which banks are selected within each SDRAM
SSTL-1.8 When activated during writes, the corresponding data groups in rank.
2X the SDRAM are masked. There is one SDM_Ax bit for every data DDR2: 1-Gb technology is 8 banks.
byte lane. SRAS_B# O Row Address Strobe:
SDQS_A[7:0] I/O Data Strobes: SSTL-1.8 This signal is used with SCAS_B# and SWE_B# (along with
SSTL-1.8 For DDR2, SDQS_Ax and its complement SDQS_Ax# signal SCS_B#) to define the SDRAM commands.
2X make up a differential strobe pair. The data is captured at the crossing
point of SDQS_Ax and its complement SDQS_Ax# during read and
write transactions.
85

DDR2 DRAM Channel B Interface (Continued) Analog Display Signals (Intel® 82945G GMCH Only)
SCAS_B# O Column Address Strobe: RED O RED Analog Video Output:
SSTL-1.8 This signal is used with SRAS_B# and SWE_B# (along with A This signal is a CRT Analog video output from the internal color
SCS_B#) to define the SDRAM commands. palette DAC. The DAC is designed for a 37.5 Ω routing impedance;
SWE_B# O Write Enable: however, the terminating resistor to ground will be 75 Ω (e.g., 75
SSTL-1.8 This signal is used with SCAS_B# and SRAS_B# (along with
Ω resistor on the board, in parallel with a 75 Ω CRT load).
t
SCS_B#) to define the SDRAM commands.
RED# O REDB Analog Output:
t
SDQ_B[63:0] I/O Data Lines:
n
A This signal is an analog video output from the internal color palette
e e
SSTL-1.8 The SDQ_B[63:0] signals interface to the SDRAM data bus.
DAC. It should be shorted to the ground plane.
2X
r
GREEN O GREEN Analog Video Output:
SDM_B[7:0] O Data Mask:
c m
A This signal is a CRT Analog video output from the internal color
SSTL-1.8 When activated during writes, the corresponding data groups in
e
2X the SDRAM are masked. There is one SDM_Bx bit for every data palette DAC. The DAC is designed for a 37.5 Ω routing impedance:
S u
byte lane. however, the terminating resistor to ground will be 75 Ω (e.g., 75
c
SDQS_B[7:0] I/O Data Strobes: Ω resistor on the board, in parallel with a 75 ΩCRT load).
c Do
SSTL-1.8 For DDR2, SDQS_Bx and its complement SDQS_Bx# signal GREEN# O GREENB Analog Output:
a
2X make up a differential strobe pair. The data is captured at the crossing A This signal is an analog video output from the internal color palette
iT ial
point of SDQS_Bx and its complement SDQS_Bx# during read and DAC. It should be shorted to the ground plane.
write transactions. BLUE O BLUE Analog Video Output:
SDQS_B[7:0]# I/O Data Strobe Complements: A This signal is a CRT Analog video output from the internal color
M t
SSTL-1.8 These are the complementary DDR2 strobe signals. palette DAC. The DAC is designed for a 37.5 Ω routing impedance;
2X however, the terminating resistor to ground will be 75 Ω (e.g., 75
n
SCKE_B[3:0] O Clock Enable:
Ω resistor on the board, in parallel with a 75 Ω CRT load).
e
SSTL-1.8 (1 per Rank). SCKE_Bx is used to initialize the SDRAMs during
power-up, to power-down SDRAM ranks, and to place all SDRAM BLUE# O BLUEB Analog Output:
id
ranks into and out of self-refresh during Suspend-to-RAM. A This signal is an analog video output from the internal color palette
DAC. It should be shorted to the ground plane.
f
SODT_B[3:0] O On Die Termination:
SSTL-1.8 Active On-die Termination Control signals for DDR2 devices. REFSET O Resistor Set:
n
A Set point resistor for the internal color palette DAC. A 255 Ω 1%
o
resistor is required between REFSET and motherboard ground.
HSYNC O
C
CRT Horizontal Synchronization:
PCI Express* Interface Signals 2.5V This signal is used as the horizontal sync (polarity is programmable)
Signal Name Type Description CMOS or “sync interval”. 2.5 V output.
EXP_RXN[15:0] I/O PCI Express* Receive Differential Pair VSYNC O CRT Vertical Synchronization:
EXP_RXP[15:0] PCIE 2.5V This signal is used as the vertical sync (polarity is programmable). 2.5
CMOS V output.
EXP_TXN[15:0] O PCI Express* Transmit Differential Pair
EXP_TXP[15:0] PCIE DDC_CLK I/O Monitor Control Clock:
2.5V This signal may be used as the DDC_CLK for a secondary
EXP_ICOMPO I PCI Express* Output Current and Resistance Compensation
CMOS multiplexed digital display connector.
A
DDC_DATA I/O Monitor Control Data:
EXP_COMPI I PCI Express* Input Current Compensation
2.5V This signal may be used as the DDC_Data for a secondary
A
CMOS multiplexed digital display connector.
Unless otherwise specified, PCI Express signals are AC coupled, so the only voltage specified is a
maximum 1.2 V differential swing.
86

Clock, Reset, and Miscellaneous Clock, Reset, and Miscellaneous (Continued)
HCLKP I Differential Host Clock In: XORTEST I/O XOR Test:
HCLKN HCSL These pins receive a differential host clock from the external clock GTL+ This signal is used for Bed of Nails testing by OEMs to execute XOR
synthesizer. This clock is used by all of the (G)MCH logic Chain test.
that is in the Host clock domain. Memory domain clocks are also LLLZTEST I/O All Z Test:
derived from this source. GTL+ As an input this signal is used for Bed of Nails testing by OEMs to
t
GCLKP I Differential PCI Express* Clock In: execute XOR Chain test. It is used as an output for XOR chain
t
GCLKN HCSL These pins receive a differential 100 MHz Serial Reference clock testing.
n
from the external clock synthesizer. This clock is used to generate the
e e
clocks necessary for the support of PCI Express.
r
DREFCLKN I Display PLL Differential Clock In
c m
DREFCLKP HCSL
e
RSTIN# I Reset In:
S u
HVIN When asserted, this signal will asynchronously reset the (G)MCH DDR2 DRAM Reference and Compensation
c
logic. This signal is connected to the PCIRST# output of the Intel® Signal Name Type Description
c Do
ICH7. All PCI Express graphics attach output signals will also
SRCOMP[1:0] I/O System Memory RCOMP
a
tri-state compliant to PCI Express* Specification, Revision 1.0a.
This input should have a Schmitt trigger to avoid spurious resets. SOCOMP[1:0] I/O DDR2 On-Die DRAM Over Current Detection (OCD) Driver
iT ial
This signal is required to be 3.3 V tolerant. A Compensation
PWROK I Power OK: SMVREF[1:0] I SDRAM Reference Voltage:
M t
HVIN When asserted, PWROK is an indication to the (G)MCH that core A These signals are reference voltage inputs for each SDQ_x, SDM_x,
power has been stable for at least 10 us. SDQS_x, and SDQS_x# input signals.
n
EXTTS# I External Thermal Sensor Input:
e
CMOS This signal may connect to a precision thermal sensor located on or
near the DIMMs. If the system temperature reaches a dangerously
id
high value, then this signal can be used to trigger the start of system
f
thermal management. This signal is activated when an increase in
temperature causes a voltage to cross some threshold in the sensor. Direct Media Interface (DMI)
n
EXP_EN I PCI Express SDVO Concurrent Select: Signal Name Type Description
o
CMOS 0 = Only SDVO or PCI Express operational DMI_RXP[3:0] I/O Direct Media Interface:
C
1 = SDVO and PCI Express operating simultaneously via PCI DMI_RXN[3:0] DMI These signals are receive differential pairs (Rx).
Express port DMI_TXP[3:0] O Direct Media Interface:
NOTES: For the 82945P MCH, this signal should be pulled low. DMI_TXN[3:0] DMI These signals are transmit differential pairs (Tx).
EXP_SLR I PCI Express* Lane Reversal/Form Factor Selection:
CMOS (G)MCH’s PCI Express lane numbers are reversed to differentiate
Balanced Technology Extended (BTX) or ATX form factors.
0 = (G)MCH’s PCI Express lane numbers are reversed (BTX
Platforms)
1 = Normal operation (ATX Platforms)
ICH_SYNC# O ICH Sync:
HVCMOS This signal is connected to the MCH_SYNCH# signal on the ICH7.
87

Intel® Serial DVO (SDVO) Interface (Intel® 82945G GMCH Only) Intel® Serial DVO (SDVO) Interface (Intel® 82945G GMCH Only)
Signal Name Type Description (Continued)
SDVOB_CLK- O Serial Digital Video Channel B Clock Complement: Signal Name Voltage Description
PCIE This signal is multiplexed with EXP_TXN12. SDVOB_INT+ I Serial Digital Video Input Interrupt:
SDVOB_CLK+ O Serial Digital Video Channel B Clock Clock: PCIE This signal is multiplexed with EXP_RXP14.
PCIE This signal is multiplexed with EXP_TXP12. SDVOC_INT- I Serial Digital Video Input Interrupt Complement:
SDVOB_RED- O Serial Digital Video Channel C Red Complement: PCIE This signal is multiplexed with EXP_RXN10.
t
PCIE This signal is multiplexed with EXP_TXN15. SDVOC_INT+ I Serial Digital Video Input Interrupt:
t
SDVOB_RED+ O
n
Serial Digital Video Channel C Red: PCIE This signal is multiplexed with EXP_RXP10.
e e
PCIE This signal is multiplexed with EXP_TXP15. SDVO_STALL- I Serial Digital Video Filed Stall Complement:
r
SDVOB_GREEN O Serial Digital Video Channel B Green Complement: PCIE This signal is multiplexed with EXP_RXN13.
- PCIE This signal is multiplexed with EXP_TXN14.
c m
SDVO_STALL+ I Serial Digital Video Filed Stall:
SDVOB_GREEN O Serial Digital Video Channel B Green:
e
PCIE This signal is multiplexed with EXP_RXP13.
+ PCIE This signal is multiplexed with EXP_TXP14.
u
SDVO_CTRLCL I/O Serial Digital Video Device Control Clock.
S
SDVOB_BLUE- O Serial Digital Video Channel B Blue Complement:
c
K COD
PCIE This signal is multiplexed with EXP_TXN13.
c Do
SDVO_CTRLDA I/O Serial Digital Video Device Control Data.
SDVOB_BLUE+ O Serial Digital Video Channel B Blue: TA COD
a
PCIE This signal is multiplexed with EXP_TXP13.
iT ial
SDVOC_RED-/ O Serial Digital Video Channel C Red Complement Channel B
SDVOB_ALPHA PCIE Alpha Complement:
- This signal is multiplexed with EXP_TXN11.
M t
SDVOC_RED+/ O Serial Digital Video Channel C Red Complement Channel B Power and Ground
SDVOB_ALPHA PCIE Alpha: Name Voltage Description
n
+ This signal is multiplexed with EXP_TXP11. VCC 1.5V Core Power
e
SDVOC_GREEN O Serial Digital Video Channel C Green Complement: VTT 1.2V Processor System Bus Power
- PCIE This signal is multiplexed with EXP_TXN10.
id
VCC_EXP 1.5V PCI Express* and DMI Power
SDVOC_GREEN O Serial Digital Video Channel C Green:
f
+ PCIE This signal is multiplexed with EXP_TXP10. VCCSM 1.8V System Memory Power
VCC2 2.5V 2.5V COMS Power
n
SDVOC_BLUE- O Serial Digital Video Channel C Blue Complement:
PCIE This signal is multiplexed with EXP_TXN9.
o
VCCA_EXPPL 1.5V PCI Express PLL Analog Power
SDVOC_BLUE+ O Serial Digital Video Channel C Blue: L
C
PCIE This signal is multiplexed with EXP_TXP9. VCCA_DPLLA 1.5V Display PLL A Analog Power
SDVOC_CLK- O Serial Digital Video Channel C Clock Complement: (GMCH
PCIE This signal is multiplexed with EXP_TXN8. ONLY)
SDVOC_CLK+ O Serial Digital Video Channel C Clock: VCCA_DPLLB 1.5V Display PLL B Analog Power
PCIE This signal is multiplexed with EXP_TXP8. (GMCH
SDVO_TVCLKI I Serial Digital Video TV-OUT Synchronization Clock ONLY)
N- PCIE Complement: VCCA_HPLL 1.5V Host PLL Analog Power
This signal is multiplexed with EXP_RXN15. VCCA_SMPLL 1.5V System Memory PLL Analog Power
SDVO_TVCLKI I Serial Digital Video TV-OUT Synchronization Clock: VCCA_DAC 2.5V Display DAC Analog Power
N+ PCIE This signal is multiplexed with EXP_RXP15.
VSS 0V Ground
SDVOB_INT- I Serial Digital Video Input Interrupt Complement:
PCIE This signal is multiplexed with EXP_RXN14. VSSA_DAC 0V Ground
88
5.3 Intel ICH7-M South Bridge (1)

PCI Interface Signals PCI Interface Signals (Continued)
Signal Name Type Description Name Type Description
IRDY# I/O Initiator Ready: AD[31:0] I/O PCI Address/Data:
IRDY# indicates the ICH7's ability, as an initiator, to complete the AD[31:0] is a multiplexed address and data bus. During the first clock
current data phase of the transaction. It is used in conjunction with of a transaction, AD[31:0] contain a physical address (32 bits).
TRDY#. A data phase is completed on any clock both IRDY# and During subsequent clocks, AD[31:0] contain data. The Intel® ICH7
TRDY# are sampled asserted. During a write, IRDY# indicates the will drive all 0s on AD[31:0] during the address phase of all PCI
t
ICH7 has valid data present on AD[31:0]. During a read, it indicates Special Cycles.
t
the ICH7 is prepared to latch data. IRDY# is an input to the ICH7 C/BE[3:0]# I/O Bus Command and Byte Enables:
n
when the ICH7 is the target and an output from the ICH7 when the The command and byte enable signals are multiplexed on the same
e e
ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until PCI pins. During the address phase of a transaction, C/BE[3:0]#
r
driven by an initiator. define the bus command. During the data phase C/BE[3:0]# define
c m
TRDY# I/O Target Ready: the Byte Enables.
e
TRDY# indicates the Intel® ICH7's ability as a target to complete the C/BE[3:0]# Command Type
S u
current data phase of the transaction. TRDY# is used in conjunction 0000b Interrupt Acknowledge
c
with IRDY#. A data phase is completed when both TRDY# and 0001b Special Cycle
c Do
IRDY# are sampled asserted. During a read, TRDY# indicates that 0010b I/O Read
a
the ICH7, as a target, has placed valid data on AD[31:0]. During a 0011b I/O Write
write, TRDY# indicates the ICH7, as a target is prepared to latch data. 0110b Memory Read
iT ial
TRDY# is an input to the ICH7 when the ICH7 is the initiator and an 0111b Memory Write
output from the ICH7 when the ICH7 is a target. TRDY# is tri-stated 1010b Configuration Read
M t
from the leading edge of PLTRST#. TRDY# remains tri-stated by the 1011b Configuration Write
ICH7 until driven by a target. 1100b Memory Read Multiple
n
STOP# I/O Stop: 1110b Memory Read Line
1111b Memory Write and Invalidate
e
STOP# indicates that the ICH7, as a target, is requesting the initiator
to stop the current transaction. STOP# causes the ICH7, as an All command encodings not shown are reserved. The ICH7 does not
id
initiator, to stop the current transaction. STOP# is an output when the decode reserved values, and therefore will not respond if a PCI master
generates a cycle using one of the reserved values.
f
ICH7 is a target and an input when the ICH7 is an initiator.
PAR I/O Calculated/Checked Parity: DEVSEL# I/O Device Select:
n
PAR uses “even” parity calculated on 36 bits, AD[31:0] plus The ICH7 asserts DEVSEL# to claim a PCI transaction. As an output,
o
C/BE[3:0]#. “Even” parity means that the ICH7 counts the number of the ICH7 asserts DEVSEL# when a PCI master peripheral attempts
one within the 36 bits plus PAR and the sum is always even. The an access to an internal ICH7 address or an address destined DMI
C
ICH7 always calculates PAR on 36 bits regardless of the valid byte (main memory or graphics). As an input, DEVSEL# indicates the
enables. The ICH7 generates PAR for address and data phases and response to an ICH7-initiated transaction on the PCI bus. DEVSEL#
only guarantees PAR to be valid one PCI clock after the is tri-stated from the leading edge of PLTRST#. DEVSEL# remains
corresponding address or data phase. The ICH7 drives and tristates tri-stated by the ICH7 until driven by a target device.
PAR identically to the AD[31:0] lines except that the ICH7 delays FRAME# I/O Cycle Frame:
PAR by exactly one PCI clock. PAR is an output during the address The current initiator drives FRAME# to indicate the beginning and
phase (delayed one clock) for all ICH7 initiated transactions. PAR is duration of a PCI transaction. While the initiator asserts FRAME#,
an output during the data phase (delayed one clock) when the ICH7 is data transfers continue. When the initiator negates FRAME#, the
the initiator of a PCI write transaction, and when it is the target of a transaction is in the final data phase. FRAME# is an input to the
read transaction. ICH7 checks parity when it is the target of a PCI ICH7 when the ICH7 is the target, and FRAME# is an output from
write transaction. If a parity error is detected, the ICH7 will set the the ICH7 when the ICH7 is the initiator. FRAME# remains tristated
appropriate internal status bits, and has the option to generate an by the ICH7 until driven by an initiator.
NMI# or SMI#.
89

PCI Interface Signals (Continued) Serial ATA Interface Signals
Signal Name Type Description Name Type Description
PERR# I/O Parity Error: SATA0TXP O Serial ATA 0 Differential Transmit Pair:
An external PCI device drives PERR# when it receives data that has a SATA0TXN These are outbound high-speed differential signals to Port 0.
parity error. The ICH7 drives PERR# when it detects a parity error. SATA0RXP I Serial ATA 0 Differential Receive Pair:
The ICH7 can either generate an NMI# or SMI# upon detecting a SATA0RXN These are inbound high-speed differential signals from Port 0.
parity error (either detected internally or reported via the PERR# SATA1TXP O Serial ATA 1 Differential Transmit Pair:
t
signal). SATA1TXN These are outbound high-speed differential signals to Port 1.
REQ[0:3]# I PCI Requests:
t
I
n
SATA1RXP Serial ATA 1 Differential Receive Pair:
REQ[4]#/ The ICH7 supports up to 6 masters on the PCI bus. The REQ[4]# and
e e
SATA1RXN These are inbound high-speed differential signals from Port 1.
GPIO22 REQ5# pins can instead be used as a GPIO.
r
SATA2TXP O Serial ATA 2 Differential Transmit Pair:
REQ[5]#/GPIO1
SATA2TXN These are outbound high-speed differential signals to Port 2.
c m
GNT[0:3]# O PCI Grants:
SATA2RXP I Serial ATA 2 Differential Receive Pair:
e
GNT[4]#/ The ICH7 supports up to 6 masters on the PCI bus. The GNT4# and
SATA2RXN These are inbound high-speed differential signals from Port 2.
S u
GPIO48 GNT5# pins can instead be used as a GPIO. Pull-up resistors are not
SATA3TXP O Serial ATA 3 Differential Transmit Pair:
c
GNT[5]#/ required on these signals. If pull-ups are used, they should be tied to
SATA3TXN These are outbound high-speed differential signals to Port 3.
c Do
GPIO17# the Vcc3_3 power rail. GNT5#/GPIO17 has an internal pull-up.
PCICLK I NOTE: PCI Clock: SATA3RXP I Serial ATA 3 Differential Receive Pair:
a
This is a 33 MHz clock. PCICLK provides timing for all transactions SATA3RXN These are inbound high-speed differential signals from Port 3.
iT ial
on the PCI Bus. SATARBIAS O Serial ATA Resistor Bias:
PCIRST# O PCI Reset: These are analog connection points for an external resistor to ground.
This is the Secondary PCI Bus reset signal. It is a logical OR of the SATARBIAS# I Serial ATA Resistor Bias Complement:
M t
primary interface PLTRST# signal and the state of the Secondary Bus These are analog connection points for an external resistor to ground.
Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). SATA0GP/ I Serial ATA 0 General Purpose:
n
PLOCK# I/O PCI Lock: GPIO21 This is an input pin which can be configured as an interlock switch
e
This signal indicates an exclusive bus operation and may require corresponding to SATA Port 0. When used as an interlock switch
multiple transactions to complete. The ICH7 asserts PLOCK# when it status indication, this signal should be drive to ‘0’ to indicate that the
id
performs non-exclusive transactions on the PCI bus. PLOCK# is switch is closed and to ‘1’ to indicate that the switch is open.
f
ignored when PCI masters are granted the bus in desktop If interlock switches are not required, this pin can be configured as
configurations. GPIO21.
n
SERR# I/OD System Error: SATA1GP/ I Serial ATA 1 General Purpose:
o
SERR# can be pulsed active by any PCI device that detects a system GPIO19 Same function as SATA0GP, except for SATA Port 1.
C
error condition. Upon sampling SERR# active, the ICH7 has the If interlock switches are not required, this pin can be configured as
ability to generate an NMI, SMI#, or interrupt. GPIO19.
PME# I/OD PCI Power Management Event: SATA2GP/ I Serial ATA 2 General Purpose:
PCI peripherals drive PME# to wake the system from low-power GPIO36 Same function as SATA0GP, except for SATA Port 2.
states S1–S5. PME# assertion can also be enabled to generate an SCI If interlock switches are not required, this pin can be configured as
from the S0 state. In some cases the ICH7 may drive PME# active GPIO36.
due to an internal wake event. The ICH7 will not drive PME# high,
but it will be pulled up to VccSus3_3 by an internal pull-up resistor.
90

Serial ATA Interface Signals (Continued) Platform LAN Connect Interface Signals
Name Type Description Name Type Description
SATA3GP/ I Serial ATA 3 General Purpose: LAN_CLK I LAN I/F Clock:
GPIO37 Same function as SATA0GP, except for SATA Port 3. This signal is driven by the Platform LAN Connect component. The
If interlock switches are not required, this pin can be configured as frequency range is 5 MHz to 50 MHz.
GPIO37. LAN_RXD[2:0] I Received Data:
SATALED# OC Serial ATA LED: The Platform LAN Connect component uses these signals to transfer
t
This is an open-collector output pin driven during SATA command data and control information to the integrated LAN controller. These
t
activity. It is to be connected to external circuitry that can provide the signals have integrated weak pull-up resistors.
n
current to drive a platform LED. When active, the LED is on. When
e e
LAN_TXD[2:0] O Transmit Data:
tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is The integrated LAN controller uses these signals to transfer data and
r
required. control information to the Platform LAN Connect component.
c m
NOTE: An internal pull-up is enabled only during PLTRST# LAN_RSTSYNC O LAN Reset/Sync:
e
assertion. The Platform LAN Connect component’s Reset and Sync signals are
S u
SATACLKREQ OD Serial ATA Clock Request: multiplexed onto this pin.
c
#/GPIO35 (Native)/ This is an open-drain output pin when configured as
c Do
I/O (GP) SATACLKREQ#. It is to connect to the system clock chip. When
a
active, request for SATA Clock running is asserted. When tri-stated,
it tells the Clock Chip that SATA Clock can be stopped. An external
iT ial
pull-up resistor is required.
Other Clock
M t
Name Type Description
CLK14 I Oscillator Clock:
n
This clock is used for 8254 timers. It runs at 14.31818 MHz. This
e
Serial Peripheral Interface (SPI) Signals clock is permitted to stop during S3 (or lower) states.
Name Type Description CLK48 I 48 MHz Clock:
id
This clock is used to run the USB controller. Runs at 48.000 MHz.
SPI_CS# I/O SPI Chip Select:
f
This clock is permitted to stop during S3 (or lower) states.
Also used as the SPI bus request signal.
SATA_CLKP I 100 MHz Differential Clock:
n
SPI_MISO I SPI Master IN Slave OUT:
SATA_CLKN These signals are used to run the SATA controller at 100 MHz. This
o
Data input pin for Intel® ICH7.
clock is permitted to stop during S3/S4/S5 states.
SPI_MOSI O SPI Master OUT Slave IN:
C
DMI_CLKP, I 100 MHz Differential Clock:
Data output pin for ICH7.
DMI_CLKN These signals are used to run the Direct Media Interface. Runs at 100
SPI _ARB I SPI Arbitration:
MHz.
SPI arbitration signal is used to arbitrate the SPI bus with Intel PRO
82573E Gigabit Ethernet Controller when Shared Flash is
implemented.
SPI_CLK O SPI Clock:
SPI clock signal, during idle the bus owner will drive the clock signal
low. 17.86 MHz.
91

IDE Interface Signals IDE Interface Signals (Continued)
DCS1# O IDE Device Chip Selects for 100 Range: DIOW#/ O Disk I/O Write (PIO and Non-Ultra DMA):
For ATA command register block. This output signal is connected to (DSTOP) This is the command to the IDE device that it may latch data from the
the corresponding signal on the IDE connector. DD lines. Data is latched by the IDE device on the deassertion edge
DCS3# O IDE Device Chip Select for 300 Range: of DIOW#. The IDE device is selected either by the ATA register file
For ATA control register block. This output signal is connected to the chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA
t
corresponding signal on the IDE connector. acknowledge (DDAK#).
t
DA[2:0] O IDE Device Address: Disk Stop (Ultra DMA): ICH7 asserts this signal to terminate a burst.
n
IORDY/ I I/O Channel Ready (PIO):
e e
These output signals are connected to the corresponding signals on
the IDE connector. They are used to indicate which byte in either the (DRSTB/ This signal will keep the strobe active (DIOR# on reads, DIOW# on
r
ATA command block or control block is being addressed. WDMARDY#) writes) longer than the minimum width. It adds wait-states to PIO
c m
DD[15:0] I/O IDE Device Data: transfers.
e
These signals directly drive the corresponding signals on the IDE Disk Read Strobe (Ultra DMA Reads from Disk): When reading from
S u
connector. There is a weak internal pull-down resistor on DD7. disk, ICH7 latches data on rising and falling edges of this signal from
c
DDREQ I IDE Device DMA Request: the disk.
c Do
This input signal is directly driven from the DRQ signal on the IDE Disk DMA Ready (Ultra DMA Writes to Disk): When writing to
a
connector. It is asserted by the IDE device to request a data transfer, disk, this is deasserted by the disk to pause burst data transfers.
iT ial
and used in conjunction with the PCI bus master IDE function and are
not associated with any AT compatible DMA channel. There is a
weak internal pulldown resistor on this signal.
M t
DDACK# O IDE Device DMA Acknowledge:
This signal directly drives the DAK# signal on the IDE connector. System Management Interface Signals
n
DDACK# is asserted by the Intel® ICH7 to indicate to IDE DMA
e
slave devices that a given data transfer cycle (assertion of DIOR# or
DIOW#) is a DMA data transfer cycle. This signal is used in INTRUDER# I Intruder Detect:
id
conjunction with the PCI bus master IDE function and are not This signal can be set to disable system if box detected open.
f
associated with any AT-compatible DMA channel. This signal’s status is readable, so it can be used like a GPIO if the
DIOR#/ O DIOR# /Disk I/O Read (PIO and Non-Ultra DMA): Intruder Detection is not needed.
n
(DWSTB/ This is the command to the IDE device that it may drive data onto the SMLINK[1:0] I/OD System Management Link:
o
RDMARDY#) DD lines. Data is latched by the ICH7 on the deassertion edge of SMBus link to optional external system management ASIC or LAN
controller. External pull-ups are required. Note that SMLINK0
C
DIOR#. The IDE device is selected either by the ATA register file
chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA corresponds to an SMBus Clock signal, and SMLINK1 corresponds
acknowledge (DDAK#). to an SMBus Data signal.
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write LINKALERT# I/OD SMLink Alert:
strobe for writes to disk. When writing to disk, ICH7 drives valid data Output of the integrated LAN and input to either the integrated ASF
on rising and falling edges of DWSTB. or an external management controller in order for the LAN’s
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA SMLINK slave to be serviced.
ready for reads from disk. When reading from disk, ICH7 deasserts
RDMARDY# to pause burst data transfers.
92

USB Interface Signals EEPROM Interface Signals
USBP0P, I/O Universal Serial Bus Port [1:0] Differential: EE_SHCLK O EEPROM Shift Clock:
USBP0N, These differential pairs are used to transmit Data/Address/Command Serial shift clock output to the EEPROM.
USBP1P, signals for ports 0 and 1. These ports can be routed to UHCI EE_DIN I EEPROM Data In:
USBP1N controller #1 or the EHCI controller. Transfers data from the EEPROM to the Intel® ICH7. This signal
NOTE: No external resistors are required on these signals. The Intel® has an integrated pull-up resistor.
t
ICH7 integrates 15 kΩ pull-downs and provides an output driver EE_DOUT O EEPROM Data Out:
t
impedance of 45 Ω which requires no external series resistor. Transfers data from the ICH7 to the EEPROM.
e e n
USBP2P, I/O Universal Serial Bus Port [3:2] Differential: EE_CS O EEPROM Chip Select:
r
USBP2N, These differential pairs are used to transmit data/address/command Chip select signal to the EEPROM.
c m
USBP3P, signals for ports 2 and 3. These ports can be routed to UHCI
USBP3N controller #2 or the EHCI controller.
e
NOTE: No external resistors are required on these signals. The ICH7
S u
integrates 15 KΩ ?pull-downs and provides an output driver
c
c Do
impedance of 45 Ω which requires no external series resistor. Interrupt Signals
USBP4P, I/O Universal Serial Bus Port [5:4] Differential:
a
USBP4N, These differential pairs are used to transmit Data/Address/Command
iT ial
USBP5P, signals for ports 4 and 5. These ports can be routed to UHCI SERIRQ I/O Serial Interrupt Request:
USBP5N controller #3 or the EHCI controller. This pin implements the serial interrupt protocol.
NOTE: No external resistors are required on these signals. The ICH7 PIRQ[D:A]# I/OD PCI Interrupt Requests:
M t
integrates 15 KΩ?pull-downs and provides an output driver In non-APIC mode the PIRQx# signals can be routed to interrupts 3,
impedance of 45 Ω which requires no external series resistor. 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering
n
section. Each PIRQx# line has a separate Route Control register.
USBP6P, I/O Universal Serial Bus Port [7:6] Differential:
e
In APIC mode, these signals are connected to the internal I/O APIC in
USBP6N, These differential pairs are used to transmit Data/Address/Command
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
id
USBP7P, signals for ports 6 and 7. These ports can be routed to UHCI
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
USBP7N controller #4 or the EHCI controller.
f
legacy interrupts.
NOTE: No external resistors are required on these signals. The ICH7
PIRQ[H:E]#/ I/OD PCI Interrupt Requests:
n
integrates 15 KΩ?pull-downs and provides an output driver
GPIO[5:2] In non-APIC mode the PIRQx# signals can be routed to interrupts 3,
o
impedance of 45 Ω which requires no external series resistor. 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering
OC[4:0]# I Overcurrent Indicators:
C
section. Each PIRQx# line has a separate Route Control register.
OC5#/GPIO29 These signals set corresponding bits in the USB controllers to indicate In APIC mode, these signals are connected to the internal I/O APIC in
OC6#/GPIO30 that an overcurrent condition has occurred. the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
OC7#/GPIO31 OC[7:4]# may optionally be used as GPIOs. IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
NOTE: OC[7:0]# are not 5 V tolerant. legacy interrupts. If not needed for interrupts,
USBRBIAS O USB Resistor Bias: these signals can be used as GPIO.
Analog connection point for an external resistor. Used to set transmit IDEIRQ I IDE Interrupt Request:
currents and internal load resistors. This interrupt input is connected to the IDE drive.
USBRBIAS# I USB Resistor Bias Complement:
Analog connection point for an external resistor. Used to set transmit
currents and internal load resistors.
93

Power Management Interface Signals Power Management Interface Signals (Continued)
PWRBTN# I Power Button: SUSCLK O Suspend Clock:
The Power Button will cause SMI# or SCI to indicate a system This clock is an output of the RTC generator circuit to use by other
request to go to a sleep state. If the system is already in a sleep state, chips for refresh clock.
this signal will cause a wake event. If PWRBTN# is pressed for more RSMRST# I Resume Well Reset:
than 4 seconds, this will cause an unconditional transition (power This signal is used for resetting the resume power plane logic.
t
button override) to the S5 state. Override will occur even if the VRMPWRGD I VRM Power Good:
t
system is in the S1-S4 states. This signal has an internal pullup This should be connected to be the processor’s VRM Power Good
n
resistor and has an internal 16 ms de-bounce on the input.
e e
signifying the VRM is stable. This signal is internally ANDed with
RI# I Ring Indicate: the PWROK input.
r
This signal is an input from a modem. It can be enabled as a wake PLTRST# O Platform Reset:
c m
event, and this is preserved across power failures. The Intel® ICH7 asserts PLTRST# to reset devices on the platform
e
SYS_RESET# I System Reset: (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The ICH7 asserts
S u
This pin forces an internal reset after being debounced. The ICH7 will PLTRST# during power-up and when S/W initiates a hard reset
c
reset immediately if the SMBus is idle; otherwise, it will wait up to sequence through the Reset Control register (I/O Register CF9h). The
c Do
25 ms ± 2 ms for the SMBus to idle before forcing a reset on the ICH7 drives PLTRST# inactive a minimum of 1 ms after both
a
system. PWROK and VRMPWRGD are driven high. The ICH7 drives
LAN_RST# I LAN Reset: PLTRST# active a minimum of 1 ms when initiated through the Reset
iT ial
When asserted, the internal LAN controller will be put into reset. This Control register (I/O Register CF9h).
signal must be asserted for at least 10 ms after the resume well power NOTE: PLTRST# is in the VccSus3_3 well.
M t
(VccSus3_3 and VccSus1_5) is valid. When de-asserted, this signal is SLP_S3# O S3 Sleep Control:
an indication that the resume well power is stable. SLP_S3# is for power plane control. This signal shuts off power to all
n
NOTE: LAN_RST# should be tied to RSMEST#. non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to
e
WAKE# I PCI Express* Wake Event: Disk), or S5 (Soft Off) states.
Sideband wake signal on PCI Express asserted by components SLP_S4# O S4 Sleep Control:
id
requesting wakeup. SLP_S4# is for power plane control. This signal shuts power to all
f
MCH_SYNC# I MCH SYNC: non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft
This input is internally ANDed with the PWROK input. Off) state.
n
Connected to the ICH_SYNC# output of (G)MCH. NOTE: This pin must be used to control the DRAM power to use the
o
THRM# I Thermal Alarm: ICH7’s DRAM power-cycling feature. Refer to Chapter 5.14.10.2 for
C
Active low signal generated by external hardware to generate an details.
SMI# or SCI. SLP_S5# O S5 Sleep Control:
THRMTRIP# I Thermal Trip: SLP_S5# is for power plane control. This signal is used to shut power
When low, this signal indicates that a thermal trip from the processor off to all non-critical systems when in the S5 (Soft Off) states.
occurred, and the ICH7 will immediately transition to a S5 state. The PWROK I Power OK:
ICH7 will not wait for the processor stop grant cycle since the When asserted, PWROK is an indication to the ICH7 that core power
processor has overheated. has been stable for 99 ms and that PCICLK has been stable for 1 ms.
SUS_STAT#/ O Suspend Status: An exception to this rule is if the system is in S3HOT, in which
LPCPD# This signal is asserted by the ICH7 to indicate that the system will be PWROK may or may not stay asserted even though PCICLK may be
entering a low power state soon. This can be monitored by devices inactive. PWROK can be driven asynchronously. When PWROK is
with memory that need to switch from normal refresh to suspend negated, the ICH7 asserts PLTRST#.
refresh mode. It can also be used by other peripherals as an indication NOTE: PWROK must deassert for a minimum of three RTC clock
that they should isolate their outputs that may be going to periods for the ICH7 to fully reset the power and properly generate
powered-off planes. This signal is called LPCPD# on the LPC I/F. the PLTRST# output.
94

Processor Interface Signals Processor Interface Signals (Continued)
A20M# O Mask A20: NMI O Non-Maskable Interrupt:
A20M# will go active based on either setting the appropriate bit in the NMI is used to force a non-Maskable interrupt to the processor. The
Port 92h register, or based on the A20GATE input being active. ICH7 can generate an NMI when either SERR# is asserted or
CPUSLP# O CPU Sleep: IOCHK# goes active via the SERIRQ# stream. The processor detects
This signal puts the processor into a state that saves substantial power an NMI when it detects a rising edge on NMI. NMI is reset by setting
t
compared to Stop-Grant state. However, during that time, no snoops the corresponding NMI source enable/disable bit in the NMI Status
t
occur. The Intel® ICH7 can optionally assert the CPUSLP# signal and Control register (I/O Register 61h).
n
when going to the S1 state. SMI# O System Management Interrupt:
e e
FERR# I Numeric Coprocessor Error: SMI# is an active low output synchronous to PCICLK. It is asserted
r
This signal is tied to the coprocessor error signal on the processor. by the ICH7 in response to one of many enabled hardware or software
c m
FERR# is only used if the ICH7 coprocessor error reporting function events.
e
is enabled in the OIC.CEN register (Chipset Config Registers:Offset STPCLK# O Stop Clock Request:
S u
31FFh: bit 1). If FERR# is asserted, the ICH7 generates an internal STPCLK# is an active low output synchronous to PCICLK. It is
c
IRQ13 to its interrupt controller unit. It is also used to gate the asserted by the ICH7 in response to one of many hardware or
c Do
IGNNE# signal to ensure that IGNNE# is not asserted to the software events. When the processor samples STPCLK# asserted, it
a
processor unless FERR# is active. FERR# requires an external weak responds by stopping its internal clock.
pull-up to ensure a high level when the coprocessor error function is RCIN# I Keyboard Controller Reset CPU:
iT ial
disabled. The keyboard controller can generate INIT# to the processor. This
NOTE: FERR# can be used in some states for notification by the saves the external OR gate with the ICH7’s other sources of INIT#.
M t
processor of pending interrupt events. This functionality is When the ICH7 detects the assertion of this signal, INIT# is generated
independent of the OIC register bit setting. for 16 PCI clocks.
n
IGNNE# O Ignore Numeric Error: NOTE: The ICH7 will ignore RCIN# assertion during transitions to
e
This signal is connected to the ignore error pin on the processor. the S3, S4, and S5 states.
IGNNE# is only used if the ICH7 coprocessor error reporting A20GATE I A20 Gate:
id
function is enabled in the OIC.CEN register (Chipset Config A20GATE is from the keyboard controller. The signal acts as an
f
Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a alternative method to force the A20M# signal active. It saves the
coprocessor error, a write to the Coprocessor Error register (I/O external OR gate needed with various other chipsets.
n
register F0h) causes the IGNNE# to be asserted. IGNNE# remains CPUPWRGD/ O CPU Power Good:
o
asserted until FERR# is negated. If FERR# is not asserted when the GPIO49 This signal should be connected to the processor’s PWRGOOD input
Coprocessor. Error register is written, the IGNNE# signal is not
C
to indicate when the CPU power is valid. This is an output signal that
asserted. represents a logical AND of the ICH7’s PWROK and VRMPWRGD
INIT# O Initialization: signals.
INIT# is asserted by the ICH7 for 16 PCI clocks to reset the This signal may optionally be configured as a GPIO.
processor.
ICH7 can be configured to support processor Built In Self Test
(BIST).
INIT3_3V# O Initialization 3.3 V: Firmware Hub Interface Signals
This is the identical 3.3 V copy of INIT# intended for Firmware Hub. Name Type Description
INTR O Processor Interrupt: FWH[3:0]/ I/O Firmware Hub Signals:
INTR is asserted by the ICH7 to signal the processor that an interrupt LAD[3:0] These signals are multiplexed with the LPC address signals.
request is pending and needs to be serviced. It is an asynchronous FWH4/ O Firmware Hub Signals:
output and normally driven low. LFRAME# This signal is multiplexed with the LPC LFRAME# signal.
95

General Purpose I/O Signals General Purpose I/O Signals (Continued)
Name Type Tolerance Power Well Description Name Type Tolerance Power Well Description
GPIO49 I/O V_CPU_IO V_CPU_IO Multiplexed with CPUPWRGD GPIO1 I/O 5V Core Multiplexed with REQ5#.
GPIO48 I/O 3.3 V Core Multiplexed with GNT4# GPIO0 I/O 3.3 V Core Unmultiplexed.
GPIO[47:40] N/A 3.3 V N/A Not implemented. NOTES:
GPIO[39:38] I/O 3.3 V Core Unmultiplexed. 1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an
t
SMI# or an SCI, but not both.
GPIO37 I/O 3.3 V Core Multiplexed with SATA3GP. 2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals
t n
GPIO36 I/O 3.3 V Core Multiplexed with SATA2GP. are not driven high into powered-down planes. Some ICH7 GPIOs may be connected to pins on
e e
GPIO35 I/O 3.3 V Core Multiplexed with SATACLKREQ#. devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core
r
power (PWROK low) or a Power Button Override event will result in the Intel ICH7 driving a pin
c m
GPIO34 I/O 3.3 V Core Unmultiplexed. to a logic 1 to another device that is powered down..
e
GPIO33 I/O 3.3 V Core Unmultiplexed.
S u
GPIO32 I/O 3.3 V Core Unmultiplexed.
c Do c
GPIO31 I/O 3.3 V Resume Multiplexed with OC7#
GPIO30 I/O 3.3 V Resume Multiplexed with OC6# PCI Express* Signals
a
GPIO29 I/O 3.3 V Resume Multiplexed with OC5#
iT ial
PETp[1:4], O PCI Express* Differential Transmit Pair 1:4
GPIO28 I/O 3.3 V Resume Unmultiplexed.
PETn[1:4]
GPIO27 I/O 3.3 V Resume Unmultiplexed.
M t
PERp[1:4], I PCI Express Differential Receive Pair 1:4
GPIO26 I/O 3.3 V Resume Unmultiplexed. PERn[1:4]
n
GPIO25 I/O 3.3 V Resume Unmultiplexed. PETp[5:6], O PCI Express* Differential Transmit Pair 5:6
PETn[5:6] Reserved: ICH7
e
GPIO24 I/O 3.3 V Resume Unmultiplexed. Not cleared by CF9h reset (Intel® ICH7R
id
event. Only)
GPIO23 I/O 3.3 V Core Multiplexed with LDRQ1#
f
PERp[1:4], I PCI Express Differential Receive Pair 5:6
GPIO22 I/O 3.3 V Core Multiplexed with REQ4# PERn[5:6] Reserved: ICH7
n
I/O 3.3 V Core Multiplexed with SATA0GP. (ICH7R Only)
GPIO21
GPIO20
GPIO19
GPIO18
I/O
I/O
I/O
3.3 V
3.3 V
3.3 V
Core
Core
Core
o
Unmultiplexed.
C
Multiplexed with SATA1GP.
Unmultiplexed. SM Bus Interface Signals
GPIO17 I/O 3.3 V Core Multiplexed with GNT5#. Name Type Description
GPIO16 I/O 3.3 V Core Unmultiplexed. SMBDATA I/OD SMBus Data:
GPIO[15:12] I/O 3.3 V Resume Unmultiplexed. External pull-up resistor is required.
SMBCLK I/OD SMBus Clock:
GPIO11 I/O 3.3 V Resume Multiplexed with SMBALERT# External pull-up resistor is required.
GPIO[10:8] I/O 3.3 V Resume Unmultiplexed. SMBALERT#/ I SMBus Alert:
GPIO[7:6] I/O 3.3 V Core Unmultiplexed. GPIO11 This signal is used to wake the system or generate SMI#. If not used
for SMBALERT#, it can be used as a GPIO.
GPIO[5:2] I/OD 5V Core Multiplexed with PIRQ[H:E]#.
96

AC’97/Intel® High Definition Auto Link Signals Power and Ground Signals
Name Type Description Name Description
ACZ_RST# O AC’97/Intel® High Definition Audio Reset: Vcc3_3 3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3,
Master hardware reset to external codec(s). S4, S5 or G3 states.
ACZ_SYNC O AC ’97/Intel High Definition Audio Sync: Vcc1_05 1.05 V supply for core well logic (20 pins). This power may be shut off in S3, S4,
48 kHz fixed rate sample sync to the codec(s). Also used to encode S5 or G3 states.
the stream number. Vcc1_5_A 1.5 V supply for Logic and I/O (30 pins). This power may be shut off in S3, S4, S5
t
ACZ_BIT_CLK I/O AC ’97 Bit Clock Input: or G3 states.
t
12.288 MHz serial data clock generated by the external codec(s). This
n
Vcc1_5_B 1.5 V supply for Logic and I/O (53 pins). This power may be shut off in S3, S4, S5
e e
signal has an integrated pull-down resistor (see Note below). or G3 states.
Intel High Definition Audio Bit Clock Output:
r
V5REF Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut
24.000 MHz serial data clock generated by the Intel High Definition off in S3, S4, S5 or G3 states.
c m
Audio controller (the Intel® ICH7). This signal has an integrated VccSus3_3 3.3 V supply for resume well I/O buffers (24 pins). This power is not expected to
e
pull-down resistor so that ACZ_BIT_CLK doesn’t float when an Intel be shut off unless the system is unplugged in desktop configurations.
S u
High Definition Audio codec (or no codec) is connected but the VccSus1_05 1.05 V supply for resume well logic (5 pins). This power is not expected to be shut
c
signals are temporarily configured as AC ’97. off unless the system is unplugged in desktop configurations.
c Do
ACZ_SDOUT O AC ’97/Intel High Definition Audio Serial Data Out: This voltage may be generated internally (see Function Straps for strapping
a
Serial TDM data output to the codec(s). This serial output is option). If generated internally, these pins should not be connected to an external
double-pumped for a bit rate of 48 Mb/s for Intel High Definition
iT ial
supply.
Audio. V5REF_Sus Reference for 5 V tolerance on resume well inputs (1 pin). This power is not
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a expected to be shut off unless the system is unplugged in desktop configurations.
M t
functional strap. See Function Straps for more details. There is a weak VccRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This
integrated pull-down resistor on the ACZ_SDOUT pin. power is not expected to be shut off unless the RTC battery is removed or
n
ACZ_SDIN[2:0] I AC ’97/Intel High Definition Audio Serial Data In [2:0]: completely drained.
e
Serial TDM data inputs from the three codecs. The serial input is Note: Implementations should not attempt to clear CMOS by using a jumper to
single-pumped for a bit rate of 24 Mb/s for Intel® High Definition pull VccRTC low. Clearing CMOS in an Intel® ICH7-based platform can be done
id
Audio. These signals have integrated pulldown resistors, which are by using a jumper on RTCRST# or GPI.
f
always enabled. VccUSBPLL 1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This
power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB
n
not used.
o
VccDMIPLL 1.5 V supply for core well logic (1 pins. This signal is used for the DMI PLL. This
C
power may be shut off in S3, S4, S5 or G3 states.
LPC Interface Signals VccSATAPLL 1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL.
Name Type Description This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if
LAD[3:0]/ I/O LPC Multiplexed Command, Address, Data: SATA not used.
FWH[3:0] For LAD[3:0], internal pull-ups are provided. V_CPU_IO Powered by the same supply as the processor I/O voltage (3 pins). This supply is
LFRAME#/ O LPC Frame: used to drive the processor interface signals listed in Process Interface Signals.
FWH4 LFRAME# indicates the start of an LPC cycle, or an abort. Vss Grounds (194 pins).
LDRQ[0]# I LPC Serial DMA/Master Request Inputs:
LDRQ[1]#/ LDRQ[1:0]# are used to request DMA or bus master access. These
GPIO23 signals are typically connected to external Super I/O device. An
internal pull-up resistor is provided on these signals.
LDRQ1# may optionally be used as GPIO.
97

Functional Strap Definitions Functional Strap Definitions (Continued)
Signal Usage When Sampled Description Signal Usage When Sampled Description
GNT3# Top-Block Rising Edge of The signal has a weak internal pull-up. If the ACZ_SDOU XOR Chain Rising Edge of Allows entrance to XOR Chain testing when TP3
Swap Override PWROK signal is sampled low, this indicates that the T Entrance/PCI PWROK pulled low at rising edge of PWROK. See
system is strapped to the “top-block swap” mode Express* Port Chapter 25 for XOR Chain functionality
(Intel® ICH7 inverts A16 for all cycles targeting Config bit 1 information.
FWH BIOS space). The status of this strap is When TP3 not pulled low at rising edge of
t
readable via the Top Swap bit (Chipset Config PWROK, sets bit 1 of RPC.PC (Chipset Config
t
Registers:Offset 3414h:bit 0). Note that software Registers:Offset 224h). See Section 7.1.34 for
n
will not be able to clear the Top-Swap bit until details.
e e
the system is rebooted without GNT3# being This signal has a weak internal pull-down.
r
pulled down. ACZ_SYNC PCI Express Rising Edge of This signal has a weak internal pull-down.
c m
GNT2# Reserved This signal has a weak internal pull-up. Port Config bit PWROK Sets bit 0 of RPC.PC (Chipset Config
e
NOTE: This signal should not be pulled low. 0 Registers:Offset 224h). See Section 7.1.34 for
S u
REQ[4:1]#XOR Chain Rising Edge of See Chapter 25 for functionality information. details.
c
Selection PWROK GPIO25 Reserved Rising Edge of This signal has a weak internal pull-up.
c Do
LINKALER Reserved This signal requires an external pull-up resistor. RSMRST# NOTE: This signal should not be pulled low.
a
T# GPIO16 Reserved This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
iT ial
SPKR No Reboot Rising Edge of The signal has a weak internal pull-down. If the
PWROK signal is sampled high, this indicates that the SATALED# Reserved This signal has a weak internal pull-up enabled
system is strapped to the “No Reboot” mode only when PLTRST# is asserted.
M t
(ICH7 will disable the TCO Timer system reboot NOTE: This signal should not be pulled low.
feature). The status of this strap is readable via TP3 XOR Chain Rising Edge of See Chapter 25 for functionality information.
n
the NO REBOOT bit (Chipset Config Entrance PWROK This signal has a weak internal pull-up.
e
Registers:Offset 3410h:bit 5). NOTE: This signal should not be pulled low
INTVRMEN Integrated Always Enables integrated VccSus1_05 VRM when unless using XOR Chain testing.
id
VccSus1_05 sampled high.
f
VRM Enable/
Disable
n
EE_CS Reserved This signal has a weak internal pull-down.
o
NOTE: This signal should not be pulled high. Direct Media Interface Signals
C
EE_DOUT Reserved This signal has a weak internal pull-up. Name Type Description
NOTE: This signal should not be pulled low. O
DMI[0:3]TXP, Direct Media Interface Differential Transmit Pair 0:3
GNT5#/ Boot BIOS Rising Edge of This field determines the destination of accesses DMI[0:3]TXN
GPIO17#, Destination PWROK to the BIOS memory range. Signals have weak I
DMI[0:3]RXP, Direct Media Interface Differential Receive Pair 0:3
GNT4#/ Selection internal pull-ups.Also controllable via Boot
DMI[0:3]RXN
GPIO48 BIOS Destination bit (Chipset Config
DMI_ZCOMP O Impedance Compensation Input:
Registers:Offset 3410h:bit 11:10)
Determines DMI input impedance.
(GNT5# is MSB)
DMI_IRCOMP I Impedance/Compensation Compensation Output:
01-SPI
Determines DMI output impedance and bias current.
10-PCI
11-LPC
98

Miscellaneous Signals
INTVRMEN I Internal Voltage Regulator Enable:
This signal enables the internal 1.05 V Suspend regulator when
connected to VccRTC. When connected to Vss, the internal regulator
is disabled.
SPKR O Speaker:
t
The SPKR signal is the output of counter 2 and is internally
t n
“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This
e e
signal drives an external speaker driver device, which in turn drives
r
the system speaker. Upon PLTRST#, its output state is 0.
c m
NOTE: SPKR is sampled at the rising edge of PWROK as a
functional strap. See Function Straps for more details. There is a weak
e
integrated pull-down resistor on SPKR pin.
S u
RTCRST# I RTC Reset:
c Do c
When asserted, this signal resets register bits in the RTC well.
NOTES:
a
1. Unless CMOS is being cleared (only to be done in the G3 power
iT ial
state), the RTCRST# input must always be high when all other
RTC power planes are on.
2. In the case where the RTC battery is dead or missing on the
M t
platform, the RTCRST# pin must rise before the RSMRST# pin.
TP0 I Test Point 0:
n
This signal must have an external pull-up to VccSus3_3.
e
TP1 O Test Point 1:
Route signal to a test point.
id
TP2 O Test Point 2:
f
TP3 I/O Test Point 3:
n
Co
Real Time Clock Interface
RTCX1 Special Crystal Input 1:
This signal is connected to the 32.768 KHz crystal. If no external
crystal is used, then RTCX1 can be driven with the desired clock rate.
RTCX2 Special Crystal Input 2:
This signal is connected to the 32.768 KHz crystal. If no external
crystal is used, then RTCX2 should be left floating.
99
6. System Block Diagram U503 U505

Clock Generator
Intel Pentium M ICS9LPR310
Yonah 533/667
CPU
DIMM0
t nt
re e
RGB Channel A DIMM1
c m
CRT
U506
e
TV-OUT
u
S-Video 200 Pins DDR2
S
North Bridge SO-DIMM Socket * 2
c
LVDS
c Do
TFT LCD Calistoga 945GM
Channel B
a
iT ial
USB2.0 Line in
USB * 4
DMI
M t
External MIC
BLUE TOOTH USB2.0
n
Internal MIC
e
ODD
IDE U515
id
U518 U517
Azalia
SATA South Bridge
f
SATA HDD Audio Codec Amplifier Internal Speaker*2
TPA0212
n
ALC880
PCI_EXPRESS/USB ICH7-M Line out/
o
Mini Express
(Wireless)) SPDIF
New
Card
C PCI_EXPRESS/USB PCI BUS LPC BUS
J507
M.D.C RJ-11 Jack
U514 U513 Internal Keyboard

LAN Controller
Keyboard BIOS
Touch Pad
Winbond
U6 W83L951D Fan
RJ-45 Jack
System BIOS
100
7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This Power
t nt
on Self Test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can
re e
alert you to the problems of your computer.
ec m
S u
If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs
c
ac Do
before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are
used to identify a post error that occurs when the screen is not available.
iT ial
M t
The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can
n
determine where the problem occurred by reading the last value written to the port-80H by the debug card plug at
e
id
Mini PCI slot.
nf
Co
101
7.2 Maintenance Diagnostics
7.2.1 Diagnostic Tool for Mini PCI-E Slot
t nt
re e
ec m
S cu
ac Do
iT ial
M t
en
fid
on
C
Figure 7-1 PCI-E debug card
102
7.3 Error Codes-1

Following is a list of error codes in sequent display on the Mini PCI debug board.
Code POST Routine Description Code POST Routine Description
t
10h Some Type of Lone Reset 20h Test Keyboard
11h Turn off FAST A20 for Post
t
e e n 21h Test Keyboard Controller
12h Signal Power On Reset
r
c m
22h Check if CMOS RAM valid
13h Initialize the Chipset
Se u
23h Test Battery Fail & CMOS X-SUM
14h
c Do
Search for ISA Bus VGA Adapter
c 24h Test the DMA Controller
a
iT ial
15h Reset Counter / Timer 1 25h Initialize 8237A Controller
26h Initialize Int Vectors
M t
16h User Register Config through CMOS
n
17h Size Memory 27h RAM Quick Sizing
18h Dispatch to RAM Test
e 28h Protected Mode Entered Safely
19h Check sum the ROM
fid 29h RAM Test Completed
1Ah Reset PIC’s

on 2Ah Protected Mode Exit Successful
1Bh
1Ch
C
Initialize Video Adapter(s)
Initialize Video (6845Regs)
2Bh
2Ch
Setup Shadow
Going to Initialize Video
1Dh Initialize Color Adapter 2Dh Search for Monochrome Adapter

1Eh Initialize Monochrome Adapter 2Eh Search for Color Adapter
1Fh Test 8237A Page Registers 2Fh Sign on Messages Displayed
103
7.3 Error Codes-2

Following is a list of error codes in sequent display on the Mini PCI debug board.
Code POST Routine Description Code POST Routine Description
t
30h Special Init of Keyboard Controller 40h Configure the COMM and LPT ports
31h Test if Keyboard Present
t
e e n 41h Initialize the Floppies
32h Test Keyboard Interrupt
r
c m
42h Initialize the Hard Disk
33h Test Keyboard Command Byte
Se u
43h Initialize Option ROMs
34h
c Do
Test, Blank and Count all RAM
c 44h OEM’s Init of Power Management
a
iT ial
35h Protected Mode Entered Safely(2) 45h Update NUMLOCK Status
36h RAM Test Complete 46h Test for Coprocessor Installed
M t
n
37h Protected Mode Exit Successful 47h OEM functions before Boot
38h Update Output Port
e
id
48h Dispatch to Operate System Boot
f
39h Setup Cache Controller 49h Jump into Bootstrap Code
3Ah
on
Test if 18.2Hz Periodic Working
3Bh
3Ch
C
Test for RTC ticking
Initialize the Hardware Vectors
3Dh Search and Init the Mouse
3Eh Update NUMLOCK status
3Fh Special Init of COMM and LPT Ports
104
8. Trouble Shooting
8.1 No Power (*1)
8.2 No Display (*2)
8.3 Memory Test Error

t nt
re e
c m
8.4 Keyboard (K/B) or Touch Pad (T/P) Test Error
e
S cu
8.5 Hard Disk Drive Test Error
ac Do
8.6 ODD Test Error
iT ial
M t
8.7 USB Port Test Error
en
8.8 Audio Test Error
fid
8.9 LAN Test Error
on
C
8.10 Mini Express (wireless) Socket Test Error
8.11 New Card Socket Test Error
105
*1: No Power Definition

Base on ACPI Spec, We define no power as while we press the power button, the system can’t leave S5 status
or none the PG signal send out from power supply.
Judge condition:
Check whether there are any voltage feedback control to turn off the power.
t
Check whether no CPU power will cause system can’t leave S5 status.
t
e e n
If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sending
r
out the PG signal. If yes, we should add the effected analysis into no power chapter.
c m
Se u
*2: No Display Definition
c Do c
a
iT ial
Base on the digital IC three basic working conditions: working power, reset, Clock. We define no display as
while system leave S5 status but can’t get into S0 status.
M t
n
Judge condition:
e
Check which power will cause no display.
fid
Check which reset signal will cause no display.
o n
Check which Clock signal will cause no display.
C
Base on these three conditions to analyze the schematic and edit the no display chapter.
Keyword:
S5: Soft Off
S0: Working
For detail please refer the ACPI specification.
106
8.1 No Power-1
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
t
No Power Check following parts and signals:
t
e e n Parts: Signals:
r
c m
Board-level AKPJ501 AKPQ501 ADPIN
Is the
No
Se u
Troubleshooting AKPD502 AKPQ502 +PWR_VDDIN
c
notebook connected AKPL501 AKPL502 DVMAIN
c Do
to power (either AC adaptor AC AKPD501 PD5 -LEARNING
a
or battery)? Where from AKPU501 PL1
power source problem Power I_LIMIT
iT ial
PL2 PU505
Yes Connect AC adaptor (first use AC to PU506 PU508
ADEN#
power it)? +CPU_CORE
M t
or battery. PQ516 PQ517
+VDD3S
Try another known good

en
id
battery or AC adapter.
nf Check following parts and signals:
Power
OK?
No
Co Replace
Motherboard
Parts:
PJ501
Signals:
CHARGING BATT
Battery PQ7 BAT_CLK BAT_T
PQ8
Yes PQ501
BAT_DATA BAT_V
PQ502 LEARNING BAT_C
PD4 BAT_TEMP BAT_D
Replace the faulty AC
PU2 BAT_VOLT
adaptor or battery.
PQ503
107
8.1 No Power-2
Main Voltage Map

PJO506 U509
PL507, PU504 PJO507 EL534
P24 P7
Charge PL511, PU505 EL43,EL44 P20 EL529
P21
EL12
PF502, PL502 +3V_P +3V +3VS +3VS-TVDACA
t
PQ503, PL501
Daughter Board P29 P20
PD501, PD3
P26
EL518
P7
t
BATT
n
AKPJ502 PJ502 +3VS-TVDACB
e e
PQ709
P7
r
EL515
AKPF501
Discharge +3VS-TVDACC
c m
AKPL501
AKPL502
e
P27 P27 P9 P9
AKPR502 AKPQ501 PD5 EL528 R54
u
POWER IN FADPIN ADPIN DVMAIN +3VS-PCI +3VS-USB
S c
P9
AKPJ501 R45
+3VS-REF
c Do
PD4
a
AKPD502 EL527 P9 P9
Discharge R42
+3VS-PCIE +3VS-VDDA
iT ial
P27
P14
+FPWR_VDDIN +PWR_VDDIN U512
CARD_+3.3VS
M t
P21 P15
EL549 EL540
+3V_LAN
n
AVDDL
e
P24 P14
PU505 U512
VCC CARD_+3.3V
id
PL510, PU503 PJO501 U507, EL522
f
P24 P20
PL509, PU505 PJO502 P21 P14
P24 P21 EL523 EL537
PU505 EL535 +5V_P +5V +5VS +5VS_HDD
n
+VDD3_A +VDD3_AVREF
P14
EL18
o
+5VS_CDROM
P24 Q517
C
P21 P21 P17
PU505 EL21 EL539 EL29
+VDD5_A +VDD5 +VDD5S AMPVDD
P16 P16
EL30 EL34
F502
U511, Q515
P21
Q4 P20 +VA AVDD
+VDD3 +3V
P18 U2 P21 Q510 P21

EL536
+KBC_VDD +2.5V 2.5VDDM
NOTE :
ELL543 P15
P11
P33 : Page 33 on M/B Board circuit diagram. D2 DVDD
+VDD3_RTC
P24
Q516, EL538
+VDD3S
108
8.1 No Power-3
t
PF503, PL504, PL505, PQ504~PQ506 P25 P18
t
PQ508~PQ512, PL503
n
R619 P4
R527
+CPU_CORE +KBC_CPUCORE
+VCCA
re e EL13
P7
c m
+1.5VS_DPLLA
e
P7
u
PU506, PQ516 EL10
S
P23 P20
P27 PL508 PQ517, PL512 PJO503~505 +1.5VS_DPLLB
c
+1.05V_P +VCCP
c Do
P7
DVMAIN EL526
+1.5VS_HPLL
a
P23 PJO508 P20
iT ial
PQ519, PL513 PJO509 EL521 P7
+1.5VS_A +1.5VS +1.5VS_MPLL
EL520 P7
M t
+1.5VS_TVDAC
n
EL17 P7
e
+1.5VS_3GPLL
id
EL525 P7
PL514 P22
PU508
VTTR +1.5VS_PCIE
f
PJO508
PJO509 P20
n
+1.5VS_A
o
PJO513
PQ520, PU507 P22 P20 P14
PJO514 U512
+0.9VDDM_P +0.9VDDM
C
CARD_+1.5VS
PQ520, PU507
PU508, PL515 P22 P20 R613 P8
PJO510~512
+1.8VS_DDR_P 1.8VDDS +DDR2_VREF
NOTE :
P33 : Page 33 on M/B Board circuit diagram.
109
8.1 No Power-4
Daughter Board P29

AKPJ502 PJ502 P20
+FPWR_VDDIN
AKPD502
BAV70LT1
+PWR_VDDIN
t
AKPL502
t
120Z/100M
n
AKPQ501
AO4433 PD4
e e
FADPIN PD5 BAV70LT1
AKPJ501 AKPF501 AKPL501 AKPR502 8 PDS1040
r
7A/24V DC 120Z/100M 0.01 3 7 ADPIN 1 P27
1 2 6
c m
POWER IN 1 5 2 DVMAIN
D
S
AKZJO2 AKPD501 PR23 PR22
G
AKPC505 AKPR505
u
AKZJO3 BZV55C24 4.7K 4.7K
S
0.01U AKPR501 470K
3
2
4
c
10
F_GND
ac Do AKPR504
100K
iT ial
3 4
AKPC501
2 AKPU501 5
0.01U
M t
AKPQ502
1 6 2N7002
SC310B AKPJO501
OPEN-SMT2
en AKPR506
1M
id
P20 J503 AKJ503
f
AKZD3
n
AKPR503
10
AKSW3
o
6 PWRBTN# F_PWRSW# 1 2
P28
C
3 4
5
U513 AKPC507
1U
R91
KBC 110
0
I_LIMIT F_I_LIMIT
F_GND
W83L951D
35 LEARNING F_LEARNING
110
8.1 No Power-5
Charge
PQ503
AO4419
PF502 PL502 PL501
t
8 PD501
TR/3216FF-3A 120Z/100M 3 7 33UH SSA34
2
t
ADPIN 6
BATT
n
1 5
e e
D
S
PC509 PC506 PC504 PC16
G
10U PR28
10U 10U
r
PR42 0.1U 20K
PR41
4.7K PR514 PD503 PD3
4.7K
c m
100K B340A RLZ20C
e
GND
S u
PQ9 GND GND
c
PR17
MMBT2222A 23.7K GND
c Do
PQ4 PR15 PR16
a
PQ5 2N7002 13.7K 392K
PD6 PR18
DDTA144WCA BATTERY_TYPE
BAS32L 0
iT ial
P18
CHARGING PQ6
P18 2N7002
M t 8
n
E1 C1
PC5 10 7
e
0.01U E2 P26 GND
11 6 CHARGING PQ3
C2 RT
id
P18 2N7002
12
VCC PU2 CT
5
f
13 4
OUTPUTCTRL DTC
TL594C
n
14 3 PR12 PJS1
REF FEEDBACK
2.49K SHORT-SMT3
o
15 2
2IN- 1IN-
16 1
C
PC3 2IN+ 1IN+
0.01U
PC6 PR14 PC2 PR9 PC7
0.1U 10K 0.1U 6.19K 1U PR13 PC15 PR24
7.5K PR25
100K 1000P
0
PR10
124K
PR502
0.02
PR8
GND GNDB
I_CTRL 0
P18
111
8.1 No Power-6
PQ7
AO4433 8
7 3
Discharge 6
5
2
1
S
G
4
PQ8
AO4433
t
8
t
7 3
n
6 2
BATT DVMAIN
e e
5 1
S
PC10
G
1000P
4
c m
PD706
e
BAV70LT1
PR505 PR504
u
100K
S
4.7K +PWR_VDDIN
c Do c
D PL1
120Z/100M
14 ADEN# PQ502 PJ501
a
G 2N7002
S
PF501
iT ial
PL2
120Z/100M TR/SFT-10A
1,2
P27
M t
PR19
499K
+VDD3_AVREF
n
P18 PC9 PR20
+VDD3_AVREF
3
e
0.1U 100K
Battery Connector
id
D3
BAV70LT1 R90 PR79
U513
f
22 4.99K
1
107 BAT_TEMP BAT_T 5
n
111 BAT_VOLT BAT_V
PR501 PC501
o
R85 20K 0.1U
C133 C132 22
C
KBC 0.1U 0.1U
+5VA
W83L951D
R82 R81
2.7K 2.7K R77 PR29
33 0
41 BAT_CLK BAT_C 3
42 BAT_DATA BAT_D 4
R75 PR30
33 0 ZJO4
ZJO3 SPARKGAP-6
SPARKGAP-6
112
8.2 No Display-1
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display
Monitor
or LCD module
No Replace monitor
t nt
e e
or LCD.
r
OK?
Yes
ec m Board-level
u
Troubleshooting
Make sure that CPU module,
DIMM memory are installed S
c Do c
Properly.
a Refer to port 378H
iT ial
System
Yes error code description
BIOS writes
section to find out
M t
error code to port
Display Yes which part is causing
378H?
n
Correct it. the problem.
OK?
e
id
No No
Replace
1.Try another known good CPU module,
nf Motherboard
o
DIMM module and BIOS.
C
2.Remove all of I/O device (HDD,
ODD…….) from motherboard Check system clock,
except LCD or monitor. reset circuit and
reference power
1. Replace faulty part.

Display Yes 2. Connect the I/O device to the M/B
OK? one at a time to find out which part
To be continued
is causing the problem.
No clock, reset and power checking
113
8.2 No Display-2 +VDD3S
****** System Clock Check ******

C551 R126 R675
56P CLK_GEN- 2.2K 2.2K
57
55 SMBDATA R567 0 R672 0 SMB_DATA
1
X501 54 SMBCLK R565 0 R166 0 SMB_CLK
C552 14.318MHz
56P 2
CLK_GEN+ 58 R576 0 STOP_CPU#
62
t
P11 P12
63 R578 0 STOP_PCI#
t n
DREFCLK# R591 22 15
8 PCICLK_ICH
e e
R593 33
DREFCLK R592 22 14 U515
r
P5 HCLK_MCH# 48
27 R583 27.4 CLK_SATA#
R571 22
c m
26 R584 27.4 CLK_SATA
HCLK_MCH R572 22 49
e
South Bridge
u
U506 DREFSSCLK# 25 R585 22 CLK_ICH#
S
R589 22 18 P9
c
DREFSSCLK R590 22 17 24 R586 22 CLK_ICH
c Do
HCLK_MCH_3G# R587 22 20
ICH7-M
60 R574 33 14M_ICH
a
North Bridge HCLK_MCH_3G R588 22 19
U505 12 R51 22 CLK_USB48
iT ial
HCLK_MCH_OE# 34 +3VS
Intel 945GM R686
MCH_BSEL0 R542 1K
10K
M t
10 R679 0 CORE_CLKEN Q530
MCH_BSEL1 R545 1K
Clock 2N7002
CORE_CLKEN#
n
MCH_BSEL2 R539 1K
Generator
e
R544 1K
id
23 R49 22 PCIECLK_NCARD# 18
R547 1K ICS9LPR310 J8
f
22 R50 22 PCIECLK_NCARD 19
+VCCP P14 New Card
R70 10K
+3VS
n
R540 1K R679 0 NEWCARDCLKREQ# 16
32
Connector
o
R569 22 MINIPCIECLK1#
38 11
C
HCLK_CPU# R43 22 51 R679 0 MINIPCIECLK1 13
39
R661 10K J511
+3VS P17
P3 HCLK_CPU R44 22 52
16 MINIPCIECLKREQ1# 7
Wireless
3 PCICLK_DBC R580 33 PR510 0 PCICLK_DBC_R
Connector
51
U503
CPU_BSEL0 R52 2.2K FS_A 12
CPU
CPU_BSEL1 R573 2.2K FS_B 60 P18
Yonah PCICLK_KBC R595 33 51
U513
64
CPU_BSEL2 R575 2.2K FS_C 61 KBC P19 U6 P15
4
PCICLK_FWH R594 33 31 U514
FWH LAN
5 PCICLK_LAN R56 33 28
Controller
114
8.2 No Display-3
P25
****** Power Good & Reset Circuit Check ******
J503 AKJ503 P29 Daughter Board
+F_3V AKZJO1
AKR4
10K AKR5 AKSW1
100
1 H8_LIDSW# F_LIDSW# 1 3
t
P18 AKC2
2 4
P14
t
0.1U
U514
n
PCIRST# P11 U516 LAN_RST# R638 0 27
e e
74AHC08_V LAN Controller
r
45 PWROK P11 P12
c m
U513 +VDD3 P14 U512
e
CARD_PCIRST# 1
u
R66
S
4.7K New Card
c
50 H8_RESET# 2 4
RESET P21 VCC
c Do
KBC U4 R74
R78 C131 10K +3V
a
1 3
100K 0.1U
GND IMP811 MN U515
iT ial
W83L951D C129
0.01U R337
4.7K
J506
South IDE_RST# P14 Q513 RSTDRV# 5
M t
16 ICH_PWRBTN# ICH_PWRBTN#
Q514 P14 ODD
76 PWRGD R655 0 Bridge Connector
n
P25
e
53
KBC_PCIRST# VRMPWRGD
id
ICH7-M PLT_RST# P11 U516 KBC_PCIRST#
KBC_PCIRST#
74AHC08_V
f
P5 U506
n
P4 North Bridge
U704
o
HCPURST#
Intel 945GM FWH_PCIRST# 2
P19 U6
CPU
C
HPWRGD HPWRGD
FWH
Yonah
J511
MINIPCIE_PCIRST# 22 P17 Wireless
J507 11 ACZ_RST# Connector
MDC P16
P16 U518
R72 39 ACZ_RST#
11 ACZ_RST# P5U506
Audio Codec GMCH_RST#
5
ALC880 North Bridge
115
8.3 Memory Test Error-1

Extend DDR2 SO-DIMM is test error or system hangs up.
Memory Test Error
t nt
1. Check the extend SDRAM module is installed
re e
c m
properly. (J508, J509)
e
2. Confirm the SDRAM socket (J508, J509) is
S u
ok. Board-level
c Do c Troubleshooting One of the following components or signals on the motherboard
a
may be defective, use an oscilloscope to check the signals or
iT ial
Yes replace the parts one at a time and test after each replacement.
Test Correct it.
M t
OK?
Parts: Signals:
n
No
e
U505 +0.9VDDM SMBDATA
id
If your system host bus clock running at U506 +DDR2_VREF SMBCLK
f
J508 SA/B_MA[0..13] NB_CLK _DDR#[0..3]
533/667 MHz then make sure that J509
n
CKE[0..3] NB_CLK _DDR[0..3]
SO-DIMM module meet require of PR2~8
o
Replace CS#[0..3] SA/B_DQS[0..7]
PC3200/PC4200/PC5400. PR502~507 ODT[0..3] SA/B_DM[0..7]
C
Motherboard R59 SA/B_BS[0..2] SA/B_DQ[0..63]
SA/B_CAS# SA/B_WE#
SA/B_RAS#] SA/B_DQS[0..7
Test Yes Replace the faulty
OK? DDR2 SO-DIMM
module.
No
116
8.3 Memory Test Error-2

Extend DDR2 SO-DIMM is test error or system hangs up.
+0.9VS
PR2~8
PR502~507
J508
SA/B_BS[0..2], SA/B_CAS#, SA/B_RAS#, SA/B_WE#, SA_BS[0..2], SA_CAS#, SA_RAS#, SA_WE#
t nt
M_A/B_A[0..13], CKE[0..3], CS#[0..3], ODT[0..3] M_A_A[0..13], CKE[0,1], CS#[0,1], ODT[0,1] P8
e e
SA/B_DQS [0..7], SA/B_DQS#[0..7] SA_DQS [0..7], SA_DQS#[0..7]
r
SA/B_DM[0..7], SA/B_DQ[0..63] SA_DM[0..7], SA_DQ[0..63]
c m
NB_CLK_DDR[0..3], NB_CLK_DDR#[0..3], EXT_TS[0,1]# NB_CLK_DDR[0,1], NB_CLK_DDR#[0,1], EXT_TS0#
P5 P6 P7
Se u
SMBDATA 195
DIMM1
c
SMBCLK
c Do
197
a
iT ial
1.8VDDS
U506
M t
n
North Bridge U505
P9
e
55 GEN_SMBDATA R567 0 SMBDATA
Clock C574 C573
J509
id
2.2U 0.1U
Generator
Intel 945GM
f
54 GEN_SMBCLK R565 0 SMBCLK +DDR2_VREF
ICS9LPR310 C86 C87
n
2.2U 0.1U P8
Co SMBCLK
SMBDATA
197
195
1.8VDDS R613 SB_BS[0..2], SB_CAS#, SB_RAS#, SB_WE# , EXT_TS1#

75
+DDR2_VREF
DIMM0
SB_B_A[0..13], CKE[2,3], CS#[2,3], ODT[2,3]
R599 C78 C77
75 2.2U 0.1U SB_DQS [0..7], SB_DQS#[0..7]
SB_DM[0..7], SB_DQ[0..63]
NB_CLK_DDR[2,3], NB_CLK_DDR#[2,3], EXT_TS0#
117
8.4 Keyboard (K/B) or touch pad (T/P) Test Error-1

Error message of keyboard or touch pad test error is shown or any key does not work.
Keyboard or touch pad

Test Error
t nt
e e
Check Yes
r Board-level J4, J6 Re-soldering.
ec m Troubleshooting for cold solder?
u
Is K/B or T/P No
cable connected to notebook
properly? S
Correct it.
c Do c No
a
Yes
iT ial One of the following parts or signals on the motherboard
M t may be defective, use an oscilloscope to check the signals
n
or replace the parts one at a time and test after each
e Replace replacement.
Try another known good Keyboard
id
or touch pad. Motherboard
f
Parts Signals
on U515 KI[0..7]
C
U513 KO[0..15]
Yes J4 SERIRQ
Test Replace the faulty J6 KBD_US/JP#
Ok? Keyboard or touch pad. X502
LFRAME#
SW1
LPC_LAD[0..3]
No SW2
SW_LEFT
F1
EL16 SW_RIGHT
EL532 T_CLK
EL533 T_DATA
118
8.4 Keyboard (K/B) or touch pad (T/P) Test Error-2

Error message of keyboard or touch pad test error is shown or any key does not work.
+3VS
t
EL535
+VDD3_A 120Z/100M
+VDD3_AVREF
t
J4 Internal
n
103 R164
10K Keyboard Connector
e e
95..102 KI[0..7] 17..24
r
112
C592 C610
10U 0.1U P18
c m
79..94 KO[0..15] 1..16
e u
25
S
KBD_US/JP#
c Do c P18
a
P11 P12 +3VS
iT ial
R67 R684
10K 10K U513
M t
SERIRQ 54
+5VS
U515 +5VS
n KBC
77
e
KBD_US/JP# F1
0.5A/POLYSW
EL16
120Z/100M
J6
id
South Bridge LFRAME# 52 R354 R355 1,2
W83L951D 10K 10K P19
f
EL533 120Z/100M
ICH7-M LPC_AD[0..3] 56..59 6 T_DATA TP_DATA 5,6
Touch Pad Connector

9 T_CLK EL532 120Z/100M TP_CLK 3,4
o SW1
R710
C
200 KBC_X+ 122
1 2 SW_LEFT TP_LEFT 9,10
3 4
R629 5
10M SW_RIGHT TP_CLK 11,12
2 1 KBC_X- 123 SW2

ZJO29~32
1 2
C629 C630 3 4
X502
22P 22P 5
24MHz
119
8.5 Hard Disk Drive Test Error-1

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
Hard Disk Drive Test Error
t nt
re e
1. Check if BIOS setup is OK?.
ec m Board-level
2. Try another working drive.
S cu Troubleshooting
c Do
One of the following parts or signals on the motherboard may
a
be defective, use an oscilloscope to check the signals or replace
iT ial
the parts one at a time and test after each replacement.
Re-boot Yes
M t
Replace the faulty parts.
OK? Parts: Signals:
No
en U515 +5VS
id
J510 +3VS
f
EL537 +5VS_HDD
n
Check the system driver for proper Replace D7 SATA_RXP0
o
installation. Motherboard D8 SATA_RXN0
C
C611 SATA_TXP0
C631 SATA_TXN0
C642~645 HDD_LED#
SATA_LED#
Re - Test Yes
End
OK?
No
120
8.5 Hard Disk Drive Test Error-2

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
J510
t
+3VS
R111
t
e e n
10K
+5VS_HDD
r
EL537
c m
R154 120Z/100M
10K +5VS
e
D7 D8
R110 R153 C611 C631
BAT54A
u
0 LTST-C191TBKT-5A 68 P14
S
SATA_LED# 0.1U 10U
HDD_LED# 2 3
+3VS
P11
c Do c
SATA HDD Connector

a
iT ial
U515
M t
n
South Bridge SATA_RXP0
e
C642 3900P
SATA_RXN0
id
C643 3900P
f
ICH7-M C645 3900P
SATA_TXN0
n
SATA_TXP0
C644 3900P
Co
121
8.6 ODD Test Error-1

An error message is shown when reading data from ODD.
ODD
Test Error
t nt
re e
c m
1. Try another known good compact disk. Board-level
e
Troubleshooting
u
2. Check install for correctly.
S
One of the following parts or signals on the motherboard may
c Do c be defective, use an oscilloscope to check the signals or replace

the parts one at a time and test after each replacement.
a
iT ial
Test Yes
Replace the faulty parts. Parts: Signals:
M t
OK?
n
U515 +5VS
No
e
U518 +3VS
ODD_LED#
id
J506
IDE_RST#
f
EL18
Check the ODD for proper Replace L31 SD_DD[0..15]
n
installation. Motherboard Q513 SDCS[1,3]#
Co Q514
D7
D8
SDA[0..2]
SDDACK
SDIOR#
SDIOW#
R119~124
Re - Test Yes R617~618 SDDREQ
End R153~514 RSTDRV#
OK?
No
122
8.6 ODD Test Error-2

An error message is shown when reading data from ODD. +3VS
R154 J506
10K
D8 D7
R153
LTST-C191TBKT-5A BAT54A
68
3 1 ODD_LED# 37
+3VS
t
EL18
120Z/100M +5VS_CDROM
t n
38..42
+5VS P14
e e
C76 C79
r
10U 0.1U
R617 10K
SD_D[0..15]
ec m SD_DD[0..15] 6..20
S cu
R618 10K
P11
c Do
R1 Q514
a
Q513 DDTC144TCA R201 R291
IDE_RST# DDTC144TCA 10K 4.7K
R1 RSTDRV# 5
iT ial
Refer to Section 8.2 (No display-3)
ODD Connector
SDA[0..2] SDA[0..2] 31,33,34
U515
IDEIRQ IDEIRQ 29
M t
SDDACK SDDACK 28
n
SIORDY SIORDY 27
South Bridge
e
SDIOW# SDIOW# 25
id
SDDREQ SDDREQ 22
f
SDIOR# SDIOR# 24
ICH7-M
SDCS[1, 3]# SDCS[1, 3]# 35,36
on
P16 18 CD_L
CC670 1U R124 6.8K CDROM_LEFT 1
U518 19 CD_GND C668 1U R123 0 CDROM_COMM 3
Audio Codec 20 C669 1U R122 6.8K CDROM_RIGHT 2
CD_R
ALC880
R119 R121 R57
R120 6.8K
100K 10K
6.8K
123
8.7 USB Test Error-1

An error occurs when a USB I/O device is installed.
USB Test Error
t nt
re e
c m
Check if the USB device is installed
e
properly.
S cu
c Do
Board-level Check the following parts for cold solder or one of the following
a
Troubleshooting parts on the mother-board may be defective, use an oscilloscope
iT ial
to check the following signal or replace the parts one at a time
Test Yes
Correct it. and test after each replacement.
OK?
M t
n
No Parts: Signals:
e
id
U515 +F5V
Replace another known good USB
f
AKU501 +F3V
device. AKU502
n
SUSC#
o
AKJ502 F_SUSC#
Replace AKJ504
C
USB_OC01#
Motherboard AKEL1~2 F_USB_OC01#
AKEL503~504 USB_OC23#
AKEL501~502 F_USB_OC23#
Re-test Yes AKEL505~506
Correct it. D/USBP[0..3]+
OK? D13 D/USBP[0..3]-
AKR503 F_USBP[0..3]+
No AKR505 F_USBP[0..3]-
124
8.7 USB Test Error-2

An error occurs when a USB I/O device is installed.
+F3V
P20 J503 AKJ503 P29 Daughter Board AKU501
AKEL501
RT9702A AKR503
120Z/100M
D13 +F5V 4
10K
BAV54A 5
VIN VOUT
1 P29 AKC501 AKC502
F_SUSC# 3
t
3 SUSC# 1 FLG
CE 150U 470P
2 GND
2
n
OC0# USB_OC01# F_USB_OC01#
e e
AKC503 AKJ502
r
OC1#
1U
c m
+VCC_USB_1 1
P12 AKEL1 P29
e
D/USBP0- F_USBP0- 90Z/100M 2
S u
4 1
USB Port
D/USBP0+ F_USBP0+ 3 2 3
c Do
AKEL502
120Z/100M
a
AKEL2 +VCC_USB_1 A1
D/USBP1- F_USBP1- 90Z/100M A2
iT ial
4 1
D/USBP1+ F_USBP1+ 3 2 A3
U515
M t AKZJO[5..8]
n
+F3V
e
AKU502
South Bridge RT9702A AKR505
id
+F5V 4
10K AKEL505 120Z/100M
5
VIN VOUT
f
P29 AKC506 AKC505
SUSC# F_SUSC# 1 3
CE FLG 150U 470P
GND
ICH7-M
n
2
o
OC2# USB_OC23# F_USB_OC23#
AKC504 AKJ504
C
OC3#
1U
+VCC_USB_3 1
AKEL504 P29
D/USBP2- F_USBP2- 90Z/100M 2
4 1
USB Port
D/USBP2+ F_USBP2+ 3 2 3
AKEL506
120Z/100M +VCC_USB_4
AKEL503 A1
D/USBP3+ F_USBP3+ 90Z/100M
A2
4 1
D/USBP3- F_USBP3- 3 2 A3
AKZJO501~504
120Z/100M
125
8.8 Audio Test Error-1

No sound from speaker after audio driver is installed.
Audio Test error
t nt
1. Check if speaker cables are
re e
c m
connected properly.
e
2. Make sure all the drivers are Board-level
u
Check the following parts for cold solder or one of the following parts on the
installed properly.
S c
Troubleshooting
c Do
motherboard may be defective,use an oscilloscope to check the following signal
or replace parts one at a time and test after each replacement.
a
Test Yes
iT ial Parts: Signals:
M t
Correct it.
OK?
n
U515 Q11 +3VS +5VS
e
No U517 Q14 AMPVDD MIC_INT
id
U518 Q15 MIC1_L/R LOUT+/-
f
J506 Q16 DEVICE_DECT# PC_BEEP
n
J512 EL30 DECT_HP_OPT# ACZ_RST#
speaker, ODD.
o
J513 EL34 SPDIFOUT ACZ_SYNC
Replace J514 EL545 SPK_OFF ACZ_SDIN0
Re-test Yes
C Motherboard AKJ1
J2
EL19
EL546
EL547
EL20
SPK_OFF#
SPK_ROUT+/-
ACZ_BITCLK
ACZ_SDOUT
AMP_LEFT
AMP_RIGHT
Correct it. EL23 EL544 CDROM_LEFT CDROM_COMM
OK? CDROM_RIGHT SBSPKR
No
126
8.8 Audio Test Error-2 (Audio In)

EL20
MIC_INT
600Z/100M P16
1
R689
2 MIC1
4.7K C95 EL19
+5VS 28 MIC1_VREFL
47P EL23 600Z/100M ZJO33 Internal
EL34 AVDD 600Z/100M
EL30
120Z/100M 120Z/100M R694
SPARKGAP_6 MIC
25,38 32 MIC1_VREFR 4.7K
t
AVDD1,2
5
t
C169 C687 C667
n
4
10U 0.1U 0.1U
EL545 600Z/100M 3 P16
e e
C680 R687
51 6
1U
J512
r
21 MIC1_L EL544 600Z/100M 2
c m
1
1,9
External
e
+3VS DVDD1,2 C682
R692
1U
u
51 MIC
S
C170 22 MIC1_R
CAGND
c
10U
c Do
48
P16 SPDIFOUT SPDIFOUT
To next page
J506
a
20 C670 1U R122 6.8K CDROM_RIGHT 2
iT ial
P11 P12
ACZ_SDIN0 R645 39 8 U518 18 C669 1U R124 6.8K CDROM_LEFT 1
P14
ODD
R73 39 ACZ_SDOUT 5 Connector
M t
19 C668 1U R123 0 CDROM_COMM 3
U515 R71 39 ACZ_SYNC 10

Audio Codec
n
R119 R121 R120
100K 6.8K 6.8K
ACZ_RST# 11
e
R72 39
id
ACZ_BITCLK
R624 39 EL542 220Z/100M 6
C171 EL547
J513 P16
South Bridge ALC880 1U 600Z/100M 5
f
24 LINEIN_R
SPK_OFF 4
3
n
C72 EL546
6 Line In
ICH7-M To next page 1U 600Z/100M
o
23 LINEIN_L 2
1
C
C649 ZJO511~512
1U
SBSPKR R646 0 PC_BEEP 12
PCBEEP R397
0 C9 1U
36 AOUT_R AMP_RIGHT
To next page
R698 C10 1U
AOUT_L 0
35 AMP_LEFT
To next page
AGND
27 C686 10U
26,42
AGND
127
8.8 Audio Test Error-3 (Audio Out)

P20 J503 AKJ503 P29 Daughter Board

+5VS AMPVDD
EL29 AKJ1 P29
120Z/100M 21 SPK_ROUT+ F_ROUT+ AKEL5 600Z/100M 1
t
ROUT+
7,18,19
VDD,PVDD[0,1] Internal Speaker
16 SPK_ROUT- F_ROUT- AKEL6 600Z/100M 2 R
t
Connector
n
ROUT-
C166 C662 C666
e e
10U 0.1U 0.1U
J2 P17
r
4 LOUT+ EL4 600Z/100M SPK_LOUT+ 1
LOUT+
Internal Speaker
c m
9 LOUT- EL5 600Z/100M SPK_LOUT- 2 L
Connector
e
LOUT-
P17
S u
AMPVDD
c
C665 P17
c Do
1U C684 C679
AMP_RIGHT 20 RHPIN 100U 100U J514
a
From previous page
R143 R699 EL35
23 4.7K 10K 600Z/100M
iT ial
RLINEIN
5
C663
1U EL37
R139 600Z/100M EL36 600Z/100M 4
U517 22
M t
2
AMPVDD AMPVDD
3
n
R114 R140 EL40 DECT_HP_OPT# EL41 600Z/100M 1
e
R142 R138
R115
4.7K
D4
BAW56
100K Audio 1K 1K
22 600Z/100M C996
100P
C998
100P SPDIFOUT EL38
id
2 From previous page 600Z/100M
Q12 LED
DDTC144TKA
3 SPK_OFF# 22 Amplifier 7
Drive
AMPVDD
f
OPTIN# 1 8
R1 C167 9 IC
SPK_OFF 1U
n
From previous page EL39
R116 600Z/100M
o
1K TPA0212 R660
SPDIF Connector
10K
C
15,17 DEVICE_DECT
Q14
DEVICE_DECT# AO3413 +3VS
Q11
DDTC144TKA AMPVDD
C660
1U C173
6 R141 R144
AMP_LEFT LHPIN 1U
10K 10K
From previous page R688
5 100K
LLINEIN 3
GAIN1 OPTIN#
C659 DECT_HP_OPT#
R1 R1
1U 2 Q16
GAIN0
Q15 DTC114TKA
R693
100K DTC114TKA
DEVICE_DECT#
128
8.9 LAN Test Error-1

An error occurs when a LAN device is installed.
LAN Test Error
t nt
1.Check if the driver is installed properly.
re e Check the following parts for cold solder or one of the following
2.Check if the notebook connect with the
ec m parts on the mother-board may be defective, use an oscilloscope
u
to check the following signal or replace the parts one at a time and
S
LAN properly.
c
test after each replacement.
c Do
Board-level
a
Troubleshooting
iT ial
Parts: Signals:
M t
Test Yes U515 +3V +2.5V
Correct it. U514 DVDD AVDDL
OK?
n
U510 MDI[0,1]+/- TX+/-
e
J505 WAKE_UP# MCT3/4
id
No X503 LAN_RST# PJ7/4
f
Q525 PCICLK_LAN RX+/-
n
EL530 LAN_WAKE PJTX+/-
Check if BIOS setup is ok.
o
EL531 PCI_AD[0..31] PJRX+/-
C
Replace EL541 PCI_C/BE#[0..3] PCLK_RUN#
EL543 PCI_INTE# PCI_STOP#
Motherboard
EL540 PCI_IRDY# PCI_TRDY#
R606~609 PCI_PAR PCI_PERR#
Re-test Yes R631~639 PCI_PME# PCI_GNT0#
Correct it.
OK? R651 PCI_REQ0# PCI_FRAME#
R653 PCI_DEVSEL#
No
129
8.9 LAN Test Error-2

An error occurs when a LAN device is installed.
DVDD EL541
120Z/100M 12 26,41..
EL543
+3V
C636
120Z/100M 0.1U 24,30..
+2.5V AVDDL EL540
t
C641 120Z/100M
C653 C671 C688 C691 C639 C655 C674 C673
0.1U
t
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U +3V
e e n
C638 C637 C635 C633
0.1U 0. 1U 0. 1U 0.1U
r
c m
e
J505
S u
EL530
c
1 MDI0+ 8 9 TX+ 90Z/100M PJTX+ 3
c Do
P11 P12 4 1
P15
P15 P15 10
a
2 MDI0- 7 TX- 3 2 PJTX- 6
iT ial
R632 R631 EL531
RJ45 LAN Connector

49.9 49.9 15 RX+ 90Z/100M PJRX+ 1
U514 4 1
M t
C632
0.1U 16 RX- 3 2 PJRX- 2
U510
P9
n
5 MDI1+ 2
U515 PCICLK_LAN
LAN
e
From U505
NS681680P 14 MCT3 PJ7 7,8
LAN_RST# 6 MDI1- 1
id
R638 0 27
Controller 11 MCT4 PJ4 4,5
f
PCI_DEVSEL#,PCI_FRAME# R634 R633
South Bridge 49.9 49.9
R608
R609 R606
R607
PCI_GNT0#,PCI_REQ0# 75
n
75 75
75
PCI_IRDY#, PCI_TRDY#, PCI_TNTE# C634
o
0.1U
PCI_PAR, PCI_PERR#, PCI_SERR#
RTL8100CL
C
ICH7-M C582
PCI_STOP#, PCI_PME# 1000P
XTAL1
PCLK_RUN#
PCI_AD[0..31] XTAL2 R651 1M
PCI_C/BE#[0..3]
WAKE_UP# R179 0
R1 LAN_WAKE C651 C652
X503
22P 25MHz 22P
Q525
DDTC144TCA
130
8.10 Mini Express (Wireless) Socket Test Error-1

An error occurs when a wireless card device is installed.
Mini Express (Wireless) Socket

Test Error
t nt Board-level
Troubleshooting
1. Check if the wireless card device is
re e
installed properly.
ec m
u
2. Confirm wireless driver is installed ok.
S
c Do c
a
Check the following parts for cold solder or one of the following
iT ial
parts on the mother-board may be defective, use an oscilloscope
Test Yes
M t
Replace test after each replacement.
OK? Correct it
Motherboard
No
en
id
Parts: Signals
nf U505 +3VS SIO_48M
o
wireless card device. U515 PCIE_PERN1 SMBCLK
C
J511 PCIE_PERP1 SMBDATA
R661 PCIE_PETN1 USBPCIEP6-/+
R659 PCIE_PETP1 MINIPCIE_PCIRST#
Re-test Yes Change the faulty C191 LAD[0..3] WIRELESS_PD#
OK? C192 LFRAME#
part then end.
R134 LDRQ0#
No R689 MINIPCIE_CLKREQ1#
PR510 MINIPCIECLK1#
PR508 MINIPCIECLK1
131
8.10 Mini Express (Wireless) Socket Test Error-2

An error occurs when a wireless card device is installed.
+3VS
J511
P9
t nt R661
10K
e e
16 MINIPCIE_CLKREQ1# 7
r
U505 38 R569 22 MINIPCIECLK1# 11
P17
c m
39 R570 22 MINIPCIECLK1 13
e
Clock
u
12
Generator SIO_48M 17
S
R53 22
c
54 SMBCLK 30
c Do
ICS9LPR310 55 SMBDATA 32
a
+3VS
Mini Express (Wireless) Connector

iT ial
R134 R684
M t
10K 10K
PCIE_PERN1 23
n
PCIE_PERP1 25
P11 P12
e
C192 0.1U PCIE_PETN1 31
id
C191 0.1U PCIE_PETP1 33
f
LAD0 LAD0_R 37
U515 LAD1 LAD1_R 39
on LAD2 LAD2_R 41
LAD3 LAD3_R 43
C
South Bridge
LFRAME# LFRAME#_R 45
LDRQ0# LDRQ0#_R 47
ICH7-M SERIRQ SERIRQ_R 49
WIRELESS_PD# WIRELESS_EN 20
USBPCIEP6- 36
USBPCIEP6+ 38
MINIPCIE_PCIRST# 22
MINIPCIE_PCIRST#
132
8.11 New Card Socket Test Error-1

An error occurs when a express card device is installed.
New Card Socket

Test Error
t nt Board-level
Troubleshooting
1. Check if the New Card device
re e
c m
is installed properly.
e
2. Confirm New Card driver is
installed ok.
S cu
ac Do Check the following parts for cold solder or one of the following
iT ial
parts on the mother-board may be defective, use an oscilloscope
Test Yes
M t
Replace test after each replacement.
OK? Correct it
Motherboard
No
en
id
Parts: Signals
nf U505 +3V NEWCARD_PERN0
o
New card device. U515 +3VS NEWCARD_PERP0
C
U512 +1.5VS NEWCARD_PETN0
J8 CARD_+3.3VS NEWCARD_PETP0
Q524 CARD_3.3V CPPE#
Re-test Yes Change the faulty R50 CARD_+1.5VS PREST#
OK? RP509 PCIECLK_NCARD SMBCLK
part then end.
C189 PCIECLK_NCARD# SMBDATA
No C190 PCI_PME#
133
8.11 New Card Socket Test Error-2

An error occurs when a express card device is installed.
+3VS
R70
10K J8
P9
t
32 NEWCARDCLKREQ# 16
t n
U505 23 R49 22 PCIECLK_NCARD# 18
e e
22 R50 22 PCIECLK_NCARD 19
r
Clock
P14
c m
Generator 54 SMBCLK 7
ICS9LPR310
e u
55 SMBDATA 8
S
c Do c +3VS
CARD_+3.3VS CARD_+3.3V CARD_+1.5VS
a
4,5 6,7 14,15
12
New Card Connector

17
iT ial
+1.5VS 15,16 P14 13,14 9,10
18
+3V U512
M t
RP509 10K*4 11
P11 P12
12 TPS2231
n
19 CPPE# 17
3
e
8 PREST# 13
2 1 CARD_PCIRST# CARD_PCIRST#
id
U515 21
f
NEWCARD_PERN0
NEWCARD_PERP0 22
n
C190 0.1U NEWCARD_PETN0 24
o
South Bridge C189 0.1U NEWCARD_PETP0 25
ICH7-M C Q524
+3VS
R1
DDTC144TCA
ICH_PME# PCI_PME# 11
USBP4- 2
USBP4+ 3
134
9. Spare Parts List --1

Part Number Description Location(s) Part Number Description Location(s)
526280732003 LT SPMAX;8258IID3/G5A2/0I10I/3XES 271061203112 T F041-TH-RES;20K ,1/16W,1% ,040 PR501
416280732002 CFM-MEDION-LT PF;15.4",WXGA,LG,G 271061220308 T F041-TH-RES;22 ,1/16W,5% ,040 R139,R140,R49,R50,R51,R53,R569
442600000077 T F041-TOUCHPAD MODULE;TM61PDM1G2 271061222104 T F041-TH-RES;2.2K,1/16W,1%,0402, R126,R52,R573,R575,R675
t
411807320001 T F041-PWA;PWA-8258I-MAX,MOTHER B 271061240102 T F041-TH-RES;24.9,1/16W,1% ,0402 R168,R28,R554,R582,R654,R723
t n
411807320003 T F041-PWA;PWA-8258I-MAX,MOTHER B 271061270104 T F041-TH-RES;27.4 ,1/16W, 1%,04 R14,R522,R583,R584
271002000312 T F041-TH-RES;0 ,1/10W,5% ,080 EL31
re e 271061272105 T F041-TH-RES;2.7K ,1/16W,1% ,040 R81,R82
c m
271002102312 T F041-TH-RES;1K ,1/10W,5% ,080 R41,R614 271061330311 T F041-TH-RES;33 ,1/16W,5% ,040 R517,R56,R574,R580,R593,R594,R
271002221304 T F041-TH-RES;220,1/8W,5%,0805,SM
e
PR520,PR524
S u
271061390309 T F041-TH-RES;39, 1/16W, 5%,0402 R19,R20,R39,R40,R503,R504,R61
c
271002472304 T F041-TH-RES;4.7K ,1/10W,5% ,080 PR22,PR23 271061471308 T F041-TH-RES;470 ,1/16W,5% ,040 PR550,PR551,R598
271061000003 T F041-TH-RES;0 ,1/16W,0402,SM
ac Do
PR18,PR26,PR27,PR29,PR30 271061472312 T F041-TH-RES;4.7K ,1/16W,5% ,040 R101,R125,R143,R26,R501,R505,R
iT ial
271061100103 T F041-TH-RES;10,1/16W,1%,0402,SM PR39,PR40,PR45,PR48,PR510 271061490102 T F041-TH-RES;49.9 ,1/16W,1% ,040 R631,R632,R633,R634
271061100312 T F041-TH-RES;10 ,1/16W,5% ,040 PR74 271061492102 T F041-TH-RES;4.99K,1/16W,1% ,040 PR79,R35
271061101109 T F041-TH-RES;100 ,1/16W,1% ,040
M t
R37,R47,R550,R556,R652 271061494101 T F041-TH-RES;499K ,1/16W,1% ,04 PR19
n
271061102113 T F041-TH-RES;1K ,1/16W,1% ,040 PR566,PR567,R116,R129,R138,R1 271061510306 T F041-TH-RES;51, 1/16W, 5%,0402 R524,R687,R692
271061102310 T F041-TH-RES;1K ,1/16W,5% ,040 R635
e 271061540102 T F041-TH-RES;54.9 ,1/16W,1% ,040 R10,R11,R12,R13,R523,R551,R555
id
271061103114 T F041-TH-RES;10K ,1/16W,1% ,040 PR46,PR512,PR516,PR534,PR536 271061560306 T F041-TH-RES;56 ,1/16W,5% ,040 R15,R526,R707,R724
271061103307 T F041-TH-RES;10K ,1/16W,5% ,040
nf
PR505,R154,R617,R618 271061562107 T F041-TH-RES;5.6K ,1/16W, 1%,04 R650
o
271061104108 T F041-TH-RES;100K ,1/16W,1% ,040 PR13,PR20,PR514,PR546,R114,R 271061680305 T F041-TH-RES;68,1/16W,5%,0402,SM R145,R150,R153,R158,R159,R162
C
271061104306 T F041-TH-RES;100K ,1/16W,5% ,040 PR521,PR532 271061682304 T F041-TH-RES;6.8K ,1/16W,5% ,04 R120,R121,R122,R124
271061105307 T F041-TH-RES;1M ,1/16W,5% ,040 PR525,PR533,PR553,PR554,R100 271061750105 T F041-TH-RES;75,1/16W,1%,0402,SM R599,R606,R607,R608,R609,R613
271061106308 T F041-TH-RES;10M ,1/16W,5% ,040 R102,R629 271061822307 T F041-TH-RES;8.2K ,1/16W,5% ,040 R107,R127,R164,R558,R603,R667
271061151110 T F041-TH-RES;150 ,1/16W, 1%,040 R1,R2,R21,R22,R23,R3,R536,R537 271071000312 T F041-TH-RES;0 ,1/16W,5% ,060 EL25,EL27,PR25,PR506,PR70
271061153110 T F041-TH-RES;15K ,1/16W,1% ,040 R636 271071010304 T F041-TH-RES;1 ,1/16W,5% ,060 R169,R45
271061201107 T F041-TH-RES;200 ,1/16W, 1%,040 R36,R710 271071100103 T F041-TH-RES;10 ,1/16W,1% ,060 PR552,PR558
271061202104 T F041-TH-RES;2K ,1/16W,1% ,040 R520 271071102107 T F041-TH-RES;1K ,1/16W,1% ,060 PR34,PR526
135

271071103108 T F041-TH-RES;10K ,1/16W,1% ,060 PR14,PR564 271071362102 T F041-TH-RES;3.6K ,1/16W,1% ,060 R665
271071104108 T F041-TH-RES;100K ,1/16W,1% ,060 PR563 271071394305 T F041-TH-RES;390K ,1/16W,5% ,060 PR543
271071112106 T F041-TH-RES;1.13K,1/16W,1%,0603 PR529 271071432113 T F041-TH-RES;4.3K ,1/16W,1% ,060 PR51
t
271071113115 T F041-TH-RES;11.8K ,1/16W,1% ,06 PR38 271071452101 T F041-TH-RES;4.53K ,1/16W,1% ,06 PR33
t n
271071122105 T F041-TH-RES;1.2K ,1/16W,1% ,060 PR49,PR540,PR556 271071472309 T F041-TH-RES;4.7K ,1/16W,5% ,060 PR41,PR42
271071124117 T F041-TH-RES;124K ,1/16W,1% ,060 PR10
re e 271071473103 T F041-TH-RES;47K ,1/16W,1% ,060 PR569
c m
271071133114 T F041-TH-RES;13.7K,1/16W,.1%,060 PR15 271071478304 T F041-TH-RES;4.7 ,1/16W,5% ,060 PR71
271071152107 T F041-TH-RES;1.5K ,1/16W,1% ,060 R533
Se u
271071512103 T F041-TH-RES;5.1K ,1/16W,1% ,060 PR509,PR68
c
271071154115 T F041-TH-RES;150K ,1/16W,1% ,060 PR69 271071612101 T F041-TH-RES;6.19K,1/16W,1% ,060 PR9
271071181103 T F041-TH-RES;180 ,1/16W,1% ,060 PR53
ac Do 271071642101 T F041-TH-RES;6.49K,1/16W,1% ,060 PR537
iT ial
271071182216 T F041-TH-RES;18.2K,1/16W,1%,0603 PR560 271071682103 T F041-TH-RES;6.8K ,1/16W,1% ,060 PR52
271071184103 T F041-TH-RES;180K ,1/16W,1% ,060 R669 271071683102 T F041-TH-RES;68K ,1/16W,1% ,060 PR538
271071203106 T F041-TH-RES;20K ,1/16W,1% ,060
M t
R97 271071683103 T F041-TH-RES;68.1K ,1/16W,1% ,06 PR50
n
271071203107 T F041-TH-RES;20K ,1/16W,.1%,060 PR28 271071752105 T F041-TH-RES;7.5K,1/16W,1%,0603, PR24
271071213104 T F041-TH-RES;21.5K,1/16W,1% ,060
e
PR507,PR518 271071753102 T F041-TH-RES;75K ,1/16W,1% ,060 PR568
id
271071220106 T F041-TH-RES;22.6,1/16W,1%,0603, R619,R622,R85,R90 271071800101 T F041-TH-RES;80.6 ,1/16W,1% ,060 R600,R601
271071221103 T F041-TH-RES;221 ,1/16W,1% ,060
nf
R552,R553 271072263101 T F041-TH-RES;26.7K,1/10W,1% ,060 PR559
o
271071224102 T F041-TH-RES;226K ,1/16W,1% ,060 PR21 271072372101 T F041-TH-RES;37.4K ,1/10W,1% ,06 PR535
C
271071228306 T F041-TH-RES;2.2 ,1/16W,5% ,060 PR508,PR519,PR522,PR523,PR54 271072394102 T F041-TH-RES;392K ,1/10W,1% ,060 PR16
271071237212 T F041-TH-RES;23.7K,1/16W,1% ,060 PR17 271072482101 T F041-TH-RES;4.87K,1/10W,1%,0603 PR35
271071242104 T F041-TH-RES;2.49K,1/16W,1% ,060 PR12 271072562101 T F041-TH-RES;56.2K ,1/10W,1% ,06 PR555
271071251101 T F041-TH-RES;255 ,1/16W,1% ,0603 R34 271611103305 T F041-TH-RP;10K*4 ,8P ,1/16W,5% RP11,RP501,RP509,RP514
271071292101 T F041-TH-RES;2.94K ,1/16W,1% ,06 PR31 271611560305 T F041-TH-RP;56*4 ,8P ,1/16W,5% RP2,RP3,RP4,RP5,RP502,RP503,R
271071304104 T F041-TH-RES;300K ,1/16W,1% ,060 PR544 271611822307 T F041-TH-RP;8.2K*4,8P ,1/16W,5% RP10,RP12,RP15,RP16,RP511,RP
271071332313 T F041-TH-RES;332K ,1/16W,1% ,060 R98 271621103306 T F041-TH-RP;10K*8 ,10P,1/32W,5% RP14
136

271621472306 T F041-TH-RP;4.7K*8,10P,1/32W,5% RP9 272101224702 T F041-TH-CAP;0.22U ,10V ,+80-20% C48,C531,C62,C69,C70
272000226501 T F041-TH-CAP;22U ,CR,6.3V,0805,X C16,C19,C22,C26,C27,C28,C30,C3 272101473407 T F041-TH-CAP;0.047U,10V,10%,0402 C548,C549,C550,C56,C561,C563,C
272001106514 T F041-TH-CAP;10U,6.3V,+- 20%,080 C115,C123,C124,C125,C130,C166 272101474703 T F041-TH-CAP; 0.47U ,CR,10V,+80- C529,C556,C567,C569,C570,C572
t
272002224405 T F041-TH-CAP;0.22U,16V,0805,10%, PC512,PC527 272102104708 T F041-TH-CAP;0.1U ,16V,+80-20%, C100,C103,C106,C107,C109,C118
t n
272002225705 T F041-TH-CAP;2.2U ,CR,16V ,+80-2 C547,C577,C624,C625 272102223409 T F041-TH-CAP;0.022U,16V ,+-10%,0 C44,C501,C51,C521,C522,C533,C5
272013106504 T F041-TH-CAP;10U,25V,+/-20%,1206
re e
PC504,PC506,PC509,PC514,PC52 272103103407 T F041-TH-CAP;0.01U ,CR,25V ,10%, C632,C634,C659,C663,EC25,EC26
c m
272030102411 T F041-TH-CAP;1000P,2KV,10%,1808, C582,HC3,HC4 272105100307 T F041-TH-CAP;10P ,CR,50V ,5%,04 EC1,EC2,EC24,EC5
272071105411 T F041-TH-CAP;1U ,10V ,10%,0603,X
e u
PC552,PC554,PC570,PC583,PC59
S
272105102421 T F041-TH-CAP;1000P,CR,50V,10%,04 C1,PC10,PC15,PC20,PC35,PC525
c
272071225406 T F041-TH-CAP;2.2U ,CR,6.3V ,10%, C101,C102,C104,C105,C108,C110 272105103704 T F041-TH-CAP;0.01U ,50V,+80-20%, C117,C119,C122,C129,C139,C195
272071475403 T F041-TH-CAP;4.7U,6.3V,10%,0603,
ac Do
C113,C183,C39,C542,C614,C618,C 272105220404 T F041-TH-CAP;22P ,50V ,+ -10%,0 C629,C630,EC13,EC14,EC15,EC50
iT ial
272072105403 T F041-TH-CAP;0.1U ,CR,16V,10%,0 PC2 272105221410 T F041-TH-CAP;220P ,CR,50V ,10%,0 PC34
272072153405 T F041-TH-CAP;0.015U ,CR,16V,10%, PC37 272105222503 T F041-TH-CAP;2200P,50V ,+/-20%,0 C530
272072224405 T F041-TH-CAP;0.22U ,16V ,10%,060
M t
PC19,PC30,PC43,PC553,PC590 272105270305 T F041-TH-CAP;27P ,50V ,5%,0402, C651,C652
n
272072473409 T F041-TH-CAP;0.047U,16V ,10%,060 PC582 272105331303 T F041-TH-CAP;330P,CR,50V,5%,0402 PC32
272073104712 T F041-TH-CAP;0.1U,25V,10%,0603,X
e
EC7,PC534,PC538,PC543,PC559,P 272105392502 T F041-TH-CAP;3900P,50V,+/-20%,04 C642,C643,C644,C645
id
272073105404 T F041-TH-CAP;1UF ,25V,10%,0603, PC31 272105470403 T F041-TH-CAP;47P ,50V ,+ -10%,0 C95
272073223408 T F041-TH-CAP;0.022U,CR,25V ,10%,
nf
PC38 272401227001 T F041-TH-CAP;220U,4V,EEFCX0G221Y C179,C566,C66,C703
o
272075103414 T F041-TH-CAP;0.01U ,CR,50V ,10%, C517 272430227501 T F041-TH-CAP;220uF,2V,±20%,15mo PC550,PC572,PC580
C
272075104710 T F041-TH-CAP;0.1U ,50V,+80-20%, C4,PC16,PC501,PC507,PC537,PC 272430337501 T F041-TH-CAP;330uF,2V,±20%,15mo C159
272075222704 T F041-TH-CAP;2200P,50V ,+/-20%,0 PC39 272431227005 T F041-TH-CAP;220uF,6.3V,7343,25m PC530
272075271408 T F041-TH-CAP;270P ,50V,+-10%,060 PC560,PC563 272431337102 T F041-TH-CAP;330U,2V,-35/+10%,H1 PC40,PC510,PC515,PC518,PC519
272075470315 T F041-TH-CAP;47P ,CR,50V ,5%,060 PC561,PC562 272431477003 T F041-TH-CAP;470U,2.5V,2R5T PE470 C36,C40
272075471415 T F041-TH-CAP;470P ,50V,10%,0603, PC591 272601107521 T F041-TH-EC;100U,6.3V,+-20%,9.3* C679,C684
272101016401 T F041-TH-CAP;.1U ,CR,10V,10%,04 PC539 272603276503 T F041-TH-EC;27uF,25V,+/-20%,H5.7 PC517,PC520
272101105705 T F041-TH-CAP;1U ,CR,6.3V ,80-2 C10,C126,C147,C155,C161,C167,C 273000500184 T F041-TH-FERRIT E CHIP;600OHM/100 EL19,EL20,EL23,EL35,EL36,EL3
137

273000500267 T F041-TH-CHOKE COIL;400uH MIN,12 HL502 286302231002 T F041-TH-IC;TPS2231,POWER INTERF U512
273000500291 T F041-TH-CHOKE COIL;0.36UH,1.1mo PL503,PL506 286306208002 T F041-TH-IC;ISL6208CBZ-T,PWM DRI PU501,PU502
273000610037 T F041-TH,FERRITE CHIP;120OHM/100 EL10,EL11,EL12,EL13,EL14,EL1 286306227003 T F041-TH-IC;ISL6227CAZ, PWM CONT PU506
t
273000610041 T F041-TH,FERRITE CHIP;120OHM/100 EL540,EL541,EL543 286306260002 T F041-TH-IC;ISL6260,IMVP-VI,QFN4 PU3
t n
273000501293 T F041-TH-CHOKE COIL;4.7UH,+/-30% PL509,PL511,PL512,PL513,PL51 286388550001 T F041-TH-IC;ISL88550A,PWM,28 LD PU508
273000996273 T F041-TH-INDUCTOR;33uH,2.3A,93mO PL501
re e 288100032014 T F041-TH-DIODE;BAS32L,VRRM75V,ME D505,D506,PD6
c m
273001050272 T F041-TH-T RANSFORMER;10/100 BASE U510 288100034012 T F041-TH-DIODE;SSA34,40V,3A,SMA PD501,PD502,PD503,PD504
274011431454 T F041-TH-XTAL;14.318MHZ,32PF,50P X501
Se u
288100054034 T F041-TH-DIODE;BAT 54,30V,200mA,S D504,D507
c
274012500452 T F041-TH-XTAL;25MHZ,20PF,30PPM,8 X503 288100054035 T F041-TH-DIODE;BAT 54C,SCHOTT KY D D1,D503
274013275401 T F041-TH-XTAL;32.768KHZ,20PPM,12 X1
ac Do 288100541004 T F041-TH-DIODE;BAT 54ALT1,COM. AN D13,D4,D7,PD506
iT ial
281307085005 T F041-TH-IC;NC7SZ08P5,2-INPUT & U1 288100701003 T F041-TH-DIODE;BAV70LT1,70V,225M D2,D3,PD4
282574008013 T F041-TH-IC;74AHC08,QUAD 2-I/P A U516 288101040012 T F041-TH-DIODE;PDS1040,10A SCHOT PD5
282574014007 T F041-TH-IC;74AHC14,HEX INVERTER
M t
U520 288104148020 T F041-TH-DIODE;RLS4148,200MA,500 D501,D502
n
282574108008 T F041-TH-IC;74AHC1G08,SINGLE AND U501,U502 288105520002 T F041-TH-DIODE;BZV55-C20,ZENER,5 PD3
283468470002 T F041-TH-IC;EEPROM,M93C46-WMN6T, U519
e 288105524005 T F041-TH-DIODE;BZV55-C2V4,ZENER, PD7
id
284500007017 T F041-TH-IC;ICH7M,SOUTH BRIDGE,3 U515 288200114010 T F041-TH-T RANS;DTC114T KA,10K,N-M Q15,Q16,Q527,Q528
284500883002 T F041-TH-IC,ALC883-GR,AUDIO CODE
nf
U518 288200144027 T F041-TH-T RANS;DDT C144WCA,NPN,SO Q5,Q505
o
284500945002 T F041-TH-IC;945GM,NORT H BRIDGE,3 U506 288200144028 T F041-TH-T RANS;DDT C144TCA,NPN,SO Q17,Q513,Q514,Q518,Q522,Q524
C
284508100015 T F041-TH-IC;RT L8100CL-LF,LAN CON U514 288200144029 T F041-TH-T RANS;DTC144WK,NPN,SOT - PQ501
284509310001 T F041-TH-IC;ICS9LPR310, LOW POWE U505 288200144030 T F041-TH-T RANS;DDT C144TKA,N-MOSF Q1,Q11,Q12,Q509,Q519,Q520,Q6
284510321002 T F041-TH-IC;ADM1032ARZ-1,TEMPERA U504 288200301017 T F041-TH-T RANS;FDV301N_NL,N-CHAN Q521
286100212002 T F041-TH-IC;TPA0212,AMPLIFIER,TS U517 288202222021 T F041-TH-T RANS;PMBT2222A,NPN,SOT PQ9
286300594004 T F041-TH-IC;TL594C,PWM CONTROL,S PU2 288203413002 T F041-TH-T RANS;AO3413,P-MOSFET,S Q10,Q14,Q4,Q507,Q510,Q515,Q5
286300692001 T F041-TH-IC;G692L293T CUf,RESET C U4 288203414002 T F041-TH-IC;TRANS;AO3414,N-CHANN Q3,Q511
286301117133 T F041-TH-IC;APL1117-25V,2.5V,1A, U2 288204403011 T F041-TH-T RANS;AO4403,P-MOSFET,4 Q504,U507,U509
138

288204419002 T F041-TH-T RANS;AO4419,P-MOSFET,9 PQ503 294011200514 T F041-TH-LED;BLUE,H0.55,LTST -C19 D10,D11,D5,D8,D9
288204422002 T F041-TH-T RANS;AO4422,24mOHM,N-M PQ516,PQ520 295000010207 T F041-TH-FUSE;FAST ,3A,32V,1206,S PF502
288204433003 T F041-TH-T RANS;AO4433,P-MOS,.018 PQ7,PQ8 295000010213 T F041-TH-FUSE;0.14A/60V,POLY SWI HF502
t
288204702004 T F041-TH-T RANS;AO4702, N-MOSFET, PQ517,PU507 295000010214 T F041-TH-FUSE;0.5A/15V,POLY SWIT F1
t n
288204912002 T F041-TH-T RANS;AO4912,24mOHM ,SM PQ519,PU503,PU504 295000010218 T F041-TH-FUSE;FAST ,2A,63VDC,1206 F501
288213003005 T F041-TH-T RANS;RQA130N03,N-MOSFE
re e
PQ506,PQ508,PQ509,PQ510 295000010243 T F041-TH-FUSE;NANO,10A/125V,R451 PF501
c m
288218003001 T F041-TH-T RANS;RQA180N03,N-MOSFE PQ504,PQ505,PQ511,PQ512 295000010247 T F041-TH-FUSE;FAST ,7A/24V,1206,S PF503
288227002024 T F041-TH-T RANS;2N7002LT1,N-CHANN
e u
PQ3,PQ4,PQ502,PQ513,PQ514,PQ
S
297040100033 T F041-TH-SW;PUSH BUT TOM,5P,SPST , SW1,SW2
c
291000000054 T F041-TH-CON;WT B,S/T,12P,0.8MM,H J507 331000007084 T F041-TH-CON;BATT ERY,2.5mm,7A,7P PJ501
291000010229 T F041-TH-CON;HDR,MA,2P*1,1.25MM, J2
ac Do 331040050029 T F041-TH-CON;CDROM,C1240T-250A1- J506
iT ial
291000010327 T F041-TL-CON;HDR,MA,3P*1,1.25MM, J502 331710015018 T F041-TH-CON;D,FM,15P,3ROW,SUYIN J501
291000000817 T F041-TH-CON;WT B,8P,1.0MM,H2.2,R J7 342804300004 T F041-STAND OFF;MDC,M2.0 H6MM,SA MTG501,MT G502
291000001104 T F041-TH-CON;INVERT ER,1.0mm,1A,1
M t
J3 342804300005 T F041-STAND OFF;MINIPCI EXP,H4.3 MTG503,MT G504
n
291000002205 T F041-TH-CON;SATA HDD,FM,15P+7P, J510 481807320002 T F041-F/W ASSY;KBD CT RL,8258I-MA U513
291000002605 T F041-TH-CON;26P,1MM,H5.4,175901 J8
e 316807300001 T F041-TH-PCB;PWA-8258I/M BD R01
id
291000004781 T F041-TH-CON;S/T,478P,1.27MM,H4. U503 242600000565 T F041-LABEL;BLANK,11*5MM,COMMON
291000011504 T F041-TH-CON;HDR,MA,15P*2,1MM,H4
nf J503 242600000562 T F041-LABEL;6*6MM,GAL,BLANK,COMM
o
291000013044 T F041-TH-CON;HDR,MA,15P*2,88107- J1 242600000632 T F041-LABEL;27*7MM,XF-5811;POLYI
C
291000020001 T F041-TH-CON;HDR,1.25MM,85204-04 J10,J504 242600000560 T F041-LABEL;PAL,20*5MM,COMMON
291000020227 T F041-TH-CON;HDR,MA,2P*1,1.25MM, J9 242600000566 T F041-LABEL;BLANK,7MM*7MM,PRC
291000012612 T F041-TL-CON;HDR,ACES,85202-2602 J4 361200001024 T F041-CLEANNER;YC-336,LIQUID,STE
291000151220 T F041-TH-CON;FPC/FFC,12P,0.5MM,H J6 361200003064 T F041-SOLDER PASTE;SN96.5/AG3.0/
291000622025 T F041-TH-DIMM SOCKET ;DDR2,200P,0 J508 270110000015 T F041-TH-T HERMIST OR;470K,5%,RA,0 PR570
291000622026 T F041-TH-DIMM SOCKET ;DDR2,200P,0 J509 270110000016 T F041-TH-T HERMIST OR;10K,5%,RA,06 PR503
291000810003 T F041-TH-CON;PHONE JACK,2 IN 1,7 J505 271125029102 T F041-TH-RES;.02,1W,1%,RL3720WT- PR502
139

271061474304 T F041-TH-RES;470K ,1/16W,5% ,040 R510 342807300007 T F041-TH,FINGER;EMI GROUNDING SM ET P6
271061120101 T F041-TH-RES;12,1/16W,1%,0402,SM R43,R44,R571,R572 481807320001 T F041-F/W ASSY;SYS/VGA BIOS,8258 U6
271071751104 T F041-TH-RES;750 ,1/16W,1% ,060 PR530,PR531 288100501004 T F041-TH-DIODE;ESD,PESD5V0S1BL,S ZD3,ZD5,ZD8,ZD9
t
271072392102 T F041-TH-RES;3.92K,1/10W,1%,0603 R24 331000008145 T F041-TH-CON;SPDIF 8P,DLT13M1,MP J514
t n
272431227014 T F041-TH-CAP;220uF,4V,+10/-30%,2 PC555 271061204104 T F041-TH-RES;200K ,1/16W,1% ,040 PR504
273000610042 T F041-TH,FERRITE CHIP;220OHM/100 EL542
re e 291000005201 T F041-TH-CON;S/T,52P,0.8MM,H7.2, J511
c m
273000500185 T F041-TH-FERRIT E CHIP;130OHM/100 EL1,EL2,EL3,EL508,EL509,EL51 272105561302 T F041-TH-CAP;56P ,50V ,5%,0402,N C551,C552
273000500309 T F041-TH-CHOKE COIL;90OHM/100MHZ
e
EL530,EL531
S u
272105120310 T F041-TH-CAP;12P ,CR,50V ,5% ,0 C127,C128
c
274011200427 'TF041-T H-XT AL;12MHZ,16PF,30PPM, X502 342808300002 T F041-TH,FINGER;EMI GROUNDING SM ET P4
286306232002 T F041-TH-IC;ISL6232,PWM ,QSOP,28 PU505
ac Do 339115000074 T F041-MICROPHONE;-62dB+-2dB,D6.0 MIC1
iT ial
288200144044 T F041-TH-T RANS;DDT A144WCA-F,PNP, PQ5 365350000004 SOLDER WIRE;LEAD_FREE,ECO,RMA98S
294011200500 T F041-TH-LED;RED,H0.8,0603,LTST- D6 242600000566 T F041-LABEL;BLANK,7MM*7MM,PRC
331000016033 T F041-TH-CON;R/A,DIP T YPE,2mm,3A
M t
PJ502 622200030002 PE FILM;SKIN,PACKING,PRC
n
272101104442 T F041-TH-CAP;0.1U,CR,10V,10%,040 C189,C190,C191,C192 622200000025 T APE;SOLDER PREVENT ,1/2,LL-N15A3
295000010219 T F041-TH-FUSE;FAST ,1A,63V,1206,T F502
e 340804300001 T F041-HOLDER;EXP CARD,T YCO,SABLE
id
271061442213 T F041-TH-RES;4.42K,1/16W,1% ,040 R697,R698 242600000564 T F041-LABEL;25*6,HI-TEMP,COMMON
271071103117 T F041-TH-RES;10.2K,1/16W,1%,0603
nf
PR75 343803700001 T F041-HEATSINK;NORTHBRIDGE,8090
o
271061393103 T F041-TH-RES;39K ,1/16W,1% ,0402 R726,R727 346804300013 T F041-INSULAT OR;CHP,SABLE GT
C
271071333102 T F041-TH-RES;33K ,1/16W,1% ,060 PR76 346804300029 T F041-INSULAT OR;SAFETY-MDC,SABLE
272103330403 T F041-TH-CAP;33P ,25V ,+/-10%,0 EC511 346806000008 T F041-SPONGE;RT C BAT TERY,8258D
286303107003 T F041-TH-IC;AMS3107C,3.3V,1%,VOL U511 346806000023 T F041-SPONGE;MODEM PORT ,8258D
272101683001 T F041-TH-CAP;0.068U,10V,0402,X7R PC18 346807300001 T F041-INSULAT OR;MB,T P,8258I
291000920610 T F041-TH-CON;ST EREO JACK,6P,W9.5 J512,J513 346807300003 T F041-INSULAT OR;SPK,SLD-MB,8258I
342808300004 T F041-TH,FINGER;EMI GROUNDING SM ET P3 346807300005 T F041-INSULAT OR;MB,SOLDER,8258I
342807300006 T F041-TH,FINGER;EMI GROUNDING SM ET P501 348205015010 T F041-GASKET ;2,05,015,010
140

348208050025 T F041-GASKET ;2,08,050,025 272001105410 T F041-TH-CAP;1U ,10%,10V ,0805 AKPC507
371102010620 T F041-SCREW;M2L6,K-HD(+1),D3.3t0 272073104712 T F041-TH-CAP;0.1U,25V,10%,0603,X AKEC501
371102010310 T F041-SCREW;M2L3,K-HD(+),D3.8,t= 272075103414 T F041-TH-CAP;0.01U ,CR,50V ,10%, AKPC505
t
371102010521 T F041-SCREW;M2L5,BIN(+1),D4.1,t1 272101105705 T F041-TH-CAP;1U ,CR,6.3V ,80-2 AKC503,AKC504
t n
343807300001 T F041-HEATSINK;SOUT HBRIDGE,8258I 272102104708 T F041-TH-CAP;0.1U ,16V,+80-20%, AKC2,AKEC502,AKEC503
346805050001 T F041-INSULAT OR;DDR SOCKET,DRAGO
re e 272105100307 T F041-TH-CAP;10P ,CR,50V ,5%,04 AKEC1,AKEC3,AKEC6,AKEC7,A
c m
346807300006 T F041-INSULAT OR;MB,CPU,8258I 272105103704 T F041-TH-CAP;0.01U ,50V,+80-20%, AKPC501
346807300007 T F041-INSULAT OR;MB,MINIPCI-E,825
Se u
272431157520 T F041-TH-CAP;150U,KOCAP,6.3V,20% AKC501,AKC506
c
348207070020 T F041-GASKET ;2,07,070,020 273000500184 T F041-TH-FERRIT E CHIP;600OHM/100 AKEL5,AKEL6
348208035020 T F041-GASKET ;2,08,035,020
ac Do 286300310001 T F041-TH-IC;SC310B,I-SENSE AMP,S AKPU501
iT ial
348210010020 T F041-GASKET ;2,10,010,020 286309702004 T F041-TH-IC;RT 9702APB,POWER DIST AKU501,AKU502
348210015020 T F041-GASKET ;2,10,015,020 288100024013 T F041-TH-DIODE;RLZ24B,ZENER,SOD- AKPD501
422802800003 T F041-WIRE ASSY;BATT T O MB,MOLEX J9
M t 288100701003 T F041-TH-DIODE;BAV70LT1,70V,225M AKPD502
n
346807300008 T F041-INSULAT OR;NEWCARD,8258I 288204433003 T F041-TH-T RANS;AO4433,P-MOS,.018 AKPQ501
411807300007 T F041-PWA;PWA-8258I_8858/DD BD
e 291000010229 T F041-TH-CON;HDR,MA,2P*1,1.25MM, AKJ1
id
411807300009 T F041-PWA;PWA-8258I_8858/DD BD,S 291000000713 T F041-TH-CON;MINI DIN,7P,R/A,C10 AKJ501
271045107104 T F041-TH-RES;.01 ,1W ,1% ,2512
nf
AKPR502 291000011504 T F041-TH-CON;HDR,MA,15P*2,1MM,H4 AKJ503
o
271061101109 T F041-TH-RES;100 ,1/16W,1% ,040 AKR5,AKR7,AKR8 294011200514 T F041-TH-LED;BLUE,H0.55,LTST -C19 AKD1,AKD2
C
271061102310 T F041-TH-RES;1K ,1/16W,5% ,040 AKC502,AKC505,AKR1 295000010247 T F041-TH-FUSE;FAST ,7A/24V,1206,S AKPF501
271061103307 T F041-TH-RES;10K ,1/16W,5% ,040 AKR2,AKR4,AKR503,AKR505 297040100033 T F041-TH-SW;PUSH BUT TOM,5P,SPST , AKSW2,AKSW3
271061104108 T F041-TH-RES;100K ,1/16W,1% ,040 AKPR504 331000008134 T F041-TH-CON;R/A,4P*2,2MM,H15.64 AKJ502,AKJ504
271061105307 T F041-TH-RES;1M ,1/16W,5% ,040 AKPR506 331910000012 T F041-TH-CON;DC POWER JACK,2DC-G AKPJ501
271061151110 T F041-TH-RES;150 ,1/16W, 1%,040 AKR3,AKR6,AKR9 316807300002 T F041-TH-PCB;PWA-8258I_8858/DAUG R01
271061474304 T F041-TH-RES;470K ,1/16W,5% ,040 AKPR505 288227002024 T F041-TH-T RANS;2N7002LT1,N-CHANN AKPQ502
271071100103 T F041-TH-RES;10 ,1/16W,1% ,060 AKPR501,AKPR503 273000610041 T F041-TH,FERRITE CHIP;120OHM/100 AKEL501,AKEL502,AKEL505,AK
141

273000500185 T F041-TH-FERRIT E CHIP;130OHM/100 AKEL3,AKEL4,AKEL7 371102610412 T F041-SCREW;M2.6L4,K-HD(+1),D4.6
273000500309 T F041-TH-CHOKE COIL;90OHM/100MHZ AKEL1,AKEL2,AKEL503,AKEL5 371102610623 T F041-SCREW;M2.6L6,K-HD(+1),D4.6
331000016032 T F041-TH-CON;V/T,DIP T YPE,2mm,3A AKPJ502 371102010269 T F041-SCREW;M2L2.5,K-HD(+0),D4T 0
t
273000610037 T F041-TH,FERRITE CHIP;120OHM/100 AKPL501,AKPL502 370103010617 T F041-SPC-SCREW;M3L6,K-HD(+1),D5
t n
242600000562 T F041-LABEL;6*6MM,GAL,BLANK,COMM 422806020001 T F041-CABLE FFC;TP,8258DM
288100501004 T F041-TH-DIODE;ESD,PESD5V0S1BL,S
re e
AKZD4,AKZD5 344806000026 T F041-DUMMY CARD;NEWCARD,ID2,825
c m
297140200013 T F041-TH-SW;COVER SWITCH,SPST,.1 AKSW1 345803700008 T F041-CONDUCT IVE T APE;INVERTER,8
346806000009 T F041-INSULAT OR;SPEAKER T RB,SLD,
Se u
422804300023 T F041-WIRE ASSY;HW SIGNAL,MB T O
c
346806000011 T F041-INSULAT OR;TRBOARD,SOLDER,8 345803700006 T F041-CONDUCT IVE T APE;LCD,8090
346806000015 T F041-SPONGE;POWER LED,8258D
ac Do 340807300002 T F041-HEATSINK ASSY;MPT,8258I
iT ial
348110010010 T F041-GASKET ;1,10,010,010 343804300002 T F041-SPRING SCREW;HEATSINK;SABL
348210030010 T F041-GASKET ;2,10,030,010 413000021130 CFM Medion,TFT LCD;LP154W01-TLB5
340804300009 T F041-SPEAKER ASSY;L,VECO,SABLE
M t 412806000001 T F041-PCB ASSY;D/A BD,DA-1A08-D1
n
340804300011 T F041-SPEAKER ASSY;R,VECO,SABLE 365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/CU0.
340806020004 T F041-COVER ASSY;KB,8258DM
e 411806000004 T F041-PWA;PWA-8X58 I/V BD,DA-1A0
id
340807320001 T F041-COVER ASSY;8258IM 242804400009 T F041-TH-LABEL;BAR CODE,20*10,BL
340806000005 T F041-COVER ASSY;CPU,8258D
nf 271071000312 T F041-TH-RES;0 ,1/16W,5% ,060 R5
o
340806000006 T F041-COVER ASSY;HDD,8258D 271071103310 T F041-TH-RES;10K ,1/16W,5% ,060 R4
C
340807300001 T F041-HOUSING ASSY;8258I 271071104108 T F041-TH-RES;100K ,1/16W,1% ,060 R8
340806020001 T F041-BRACKET ASSY;T P,NORMAL,825 271071105312 T F041-TH-RES;1M ,1/16W,5% ,060 R12
342803700011 T F041-STANDOFF;IO DVI,8090 271071183103 T F041-TH-RES;18K ,1/16W,1% ,060 R20
344806020013 T F041-COVER;HINGE,R,8258DM 271071184304 T F041-TH-RES;180K ,1/16W,5% ,060 R14
344806020012 T F041-COVER;HINGE,L,8258DM 271071224305 T F041-TH-RES;220K ,1/16W,5% ,060 R21
346804300031 T F041-AL-FOIL;KB,SABLE GT 271071303103 T F041-TH-RES;30K,1/16W,1%,0603,S R1
371102010327 T F041-SCREW;M2L3,K-HD(+0),D3.7T 0 271071333102 T F041-TH-RES;33K ,1/16W,1% ,060 R7
142

271071364102 T F041-TH-RES;360K ,1/16W,1%,060 R6 295000010397 T F041-TH-FUSE;FAST ,1.5A,63VDC,12 F1
271071395101 T F041-TH-RES;3.9M ,1/16W,1% ,060 R9 316681300005 T F041-PCB;PWA-8050 INVERTER BD,G R0D
271071591103 T F041-TH-RES;590,1/16W,1%,0603,S R15 361200003064 T F041-SOLDER PASTE;SN96.5/AG3.0/
t
271071823106 T F041-TH-RES;82K,1/16W,1%,0603,S R2 340806020005 T F041-HOUSING ASSY;LCD,8258DM
t n
272003105402 T F041-TH-CAP;1U ,CR,25V ,10%,0 C7 344806020007 T F041-COVER;REAR,LCD,8258DM
272010181303 T F041-TH-CAP;180P,2KV,5%,1206,NP C3
re e
344806020006 T F041-COVER;LCD,8258DM
c m
272023106505 T F041-TH-CAP;10U,25V,M,1210,T2.5 C1 342806020001 T F041-BRACKET;LCD,L,8258DM
272030000301 T F041-TH-CAP;15P,3KV,5%,1808,NPO C4
Se u
342806020002 T F041-BRACKET;LCD,R,8258DM
c
272071105411 T F041-TH-CAP;1U ,10V ,10%,0603,X C13 340804300002 T F041-HINGE;L,JARLLY,SABLE GT
272072105403 T F041-TH-CAP;0.1U ,CR,16V,10%,0 C15,C8
ac Do 340804300004 T F041-HINGE;R,JARLLY,SABLE GT
iT ial
272072224405 T F041-TH-CAP;0.22U ,16V ,10%,060 C9 345806020001 T F041-RUBBER;COVER,LCD,8258DM
272072473409 T F041-TH-CAP;0.047U,16V ,10%,060 C14 346806020005 T F041-MYLAR;COVER,LCD,8258DM
272073105404 T F041-TH-CAP;1UF ,25V,10%,0603, C2
M t 346802800025 T F041-INSULAT OR;INVERTER,LCD,865
n
272073223408 T F041-TH-CAP;0.022U,CR,25V ,10%, C16 371102010269 T F041-SCREW;M2L2.5,K-HD(+0),D4T 0
272073332405 T F041-TH-CAP;3300P,CR,25V ,10%,0 C12
e 371102010329 T F041-SCREW;M2L3,K-HD(+0),D4T0.3
id
272073682404 T F041-TH-CAP;6800P,CR,25V ,10%,0 C6 371102610412 T F041-SCREW;M2.6L4,K-HD(+1),D4.6
272075103414 T F041-TH-CAP;0.01U ,CR,50V ,10%,
nf
C5 370102631204 T F041-SPC-SCREW;M2.6L6,K-HD,NIW/
o
272075150308 T F041-TH-CAP;15P ,CR,50V ,5% ,0 C11 370102610807 T F041-SPC-SCREW;M2.6L8,K-HD,NIW/
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272075181308 T F041-TH-CAP;180P ,50V ,5% ,0603 C10 422804300003 T F041-WIRE ASSY;LCD WXGA,YI YI,S
273001050279 T F041-TH-XFMR;CI8.5,20T /2000T,16 T1 422804300007 T F041-WIRE ASSY;INVERTER,YI YI,S
286009910003 T F041-TH-IC;OZ9910S,CCFL CT RL ,S U2 422806500002 T F041-WLEN ASSY;CABLE,8858I
288100099015 T F041-TH-DIODE;BAV99,70V,450MA,S D1,D2 242664800093 T F041-LABEL;CAUT ION,INVERT BD,PI
288206602003 T F041-TH-T RANS;AO6602L,N&P-MOSFE U1,U3 345803700006 T F041-CONDUCT IVE T APE;LCD,8090
291000020229 T F041-TH-CON;HDR,MA,2P*1,3.5MM,R CN2 324180787522 T F041-CFM-MEDION IC,CPU;DUAL-COR
291000021109 T F041-TH-CON;HDR,MA,11P*1,ACES,8 CN1 323780340011 CFM-MEDION DDR2 SO-DIMM;HYMP564S
143

523402259065 T F041-CFM MEDION HDD DRIVE;HM100 332800002008 T F041-POWER CORD,250V2.5A 2P BL
370103011402 T F041-SPC-SCREW;M3L3,NIW,K-HD(+) 421311310002 T F041-CABLE ASSY;PHONE LINE,6P2C
340806000013 T F041-SHIELDING ASSY;HDD,8258D 561867880001 SINGLE PAGE;DISPLAY AT TENTION,GN
t
523405320298 CFM Medion ODD DRIVE;GMA-4082N,S 561580730003 T F041-MANUAL;USER'S,SP,MSN400182
t n
342672200010 T F041-BRACKET;CD-ROM,8500 561880730001 T F041-SINGLE PAGE;WARRANT Y,EN/SP
370102010207 T F041-SPC-SCREW;M2L2,NIW/NLK,K-H
re e 565180732001 CFM-MEDION,MS WIN XP MCE 2005 DV
c m
340806000010 T F041-BEZEL ASSY;GBS,D-SM+R9,UJ8 565168680015 CFM-Medion, Nero 6.6.0 15B (w/Re
346803400017 T F041-INSULAT OR;BEZEL,0.6mm,8050
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565180732002 CFM-MEDION,SUPPORT-CD MT INVES M
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346800200015 T F041-MYLAR BEZEL,POLARIS 565167993012 CFM-Medion;Power Cinema Suite 2
242670800148 T F041-LABEL;WINXP,ART EMIS
ac Do 422803400002 T F041-CFM Medion,AC ADPT ASSY;65
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242803700008 T F041-LABEL;CLASS LASER,MICRO MA 222686820002 T F041-PE BAG; L230xW310,TWO HOLE
242807310001 T F041-LABEL;RATING,INVES,MEDION, 565167993021 CFM-MEDION;CYBERLINK POWER CINEM
242808300005 T F041-LABEL;BAR CODE,(25*7MM)*12
M t 441807320006 T F041-BATT ASSY;LI-ION,11.1V/4.4
n
242807310002 T F041-NAMEPLATE;INVES,MEDION,MD9 531880730001 CFM-MEDION BLUET OOH USB ADAPT ER;
242808300010 T F041-LABEL;25*6,HI-TEMP,COMMON,
e 412807300003 T F041-CFM-MEDION T F041-PCB ASSY;
id
242807310004 T F041-CFM-MEDION;COA LABEL WIN M 222667220005 T F041-PE BAG;L560XW345,CERES
242807310003 T F041-CFM-MEDION;INTEL ST ICK CEN
nf 222803410001 T F041-PROTECTING CLOT H;LCD,BenQ,
o
242803400091 T F041-LABEL;MB EOW LABEL,(18x6MM 221807320001 T F041-CARTON;INVES,MEDION,8258I
C
531080830011 T F041-KBD;88,SP,K011818Q5,8350MP 227806000002 T F041-END CAP;NORMAL PACKING,L/R
221803440001 T F041-BOX;AK,BenQ,8050QR 224802630001 T F041-PALLET ;1200x1000x120MM,WHA
222685000001 T F041-PE BAG;ANIT -ST AT IC,200*350 221803450012 T F041-CARD BOARD;T OP/BT M,PALLET,
242300400022 T F041-LABEL;BLANK,60*80MM,LL-261 221803450013 T F041-CARD BOARD;FRAME,PALLET ,W/
222300820002 T F041-PE BAG;50*70MM,W/SEAL,COMM 221803450009 T F041-PARTITION;PALLET ,BenQ,8050
222804920002 T F041-PE BUBBLE BAG;200x240mm,RH 242803700007 T F041-LABEL;SEAL,CART ON,∮50,MED
221803450006 T F041-PARTITION;AK BOX,BenQ,8050 221300850064 T F041-REINFORCE BRKT ;L1078X50X50
144

Part Number Description Location(s)
221300850059 T F041-REINFORCE BRKT ;L788X50X50m
221300850051 T F041-REINFORCE BRKT ;L1032X50X50
561860000039 T F041-SINGLE PAGE;DISPLAY ATT ENT
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145
11. Reference Material
Intel Yonah CPU Intel, INC
Intel 945GM North Bridge Intel, INC
Intel ICH7-M South Bridge Intel, INC
Winbond W83L951G KBC Winbond, INC
8258I Hardware Engineering Specification Technology Corp/MITAC
Explode Views Technology Corp/MITAC

SERVICE MANUAL FOR 8258I
Sponsoring Editor : Ally Yuan
Author : Sanny Gao
Publisher : MiTAC Technology Corp.
Address : No.269, Road 2, Export Processing Zone, Kunshan, P.R.C
Tel : 086-512-57367777 Fax : 086-512-57385099
First Edition : Jun. 2006
E-mail : Ally.Yuan @ mic.com.tw
Web : http: //www.mitac.com http: //www.mtc.mitacservice.com

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SERVICE MANUAL FOR

BY: Sanny Gao

1. Hardware Engineering Specification …………………………………………………………………… 4

4.1 Mother Board (Side A) ….……………………………………………………………………………………..……… 76

5. Pin Description of Major Component ………………………………………………………………….. 78

5.1 Intel Yonah Processor CPU …………………………………………………………………………………………… 78

5.2 Intel 945GM North Bridge ……………………………………………………………………………………………. 83

6. System Block Diagram …………………………………………………………………………………… 100

9. Spare Parts List ………………………………………………………………………………………….. 135

10. System Exploded Views ………………………………………………………………………………... 146

1. Hardware Engineering Specification

1.1.1 General Description

The memory subsystem supports DDR2 SDRAM channels (64-bit wide).

1.2.1 Intel Yonah Processors in Micro-FCBGA Package

• Micro-FCPGA and Micro-FCBGA package technologies

1.2.2 Clock Generator

• 1 - DOT 96 MHz/27 MHz selectable pair

• CPU outputs cycle-cycle jitter < 85 ps

1.2.3 The Mobile Intel 945GM Express Chipset

• All Yonah variants

• Source synchronous double-pumped (2x) address

• Source synchronous quad-pumped (4x) data

• Other key features are

• 64-bit wide per channel

• Three memory channel configurations supported

- Dual channel symmetric

• One SO-DIMM connector per channel

• Support for 2N timings only

• Intel Gen 3.5 integrated graphics engine

• 250 MHz core rendor clock at 1.05 V core voltage

• Supports TV-Out, LVDS, CRT and SDVO

• Hardware motion compensation

• Intermediate Z in classic rendering

• Integrated 400 MHz RAMDAC

• Analog monitor support up to QXGA (2048 x 1536)

• Support for CRT hot plug

• CPIS 1.5 compliant

• Spread spertrum clocking supported

• Panel power sequencing support

• Integrated PWM interface for LCD backlight inberter control

• Three integrated 10-bit DACS

• Macro Vision support

• 32-bit downstream address

• Direct Media Interface asynchronously coupled to core

• Supports 3 virtual channels for traffic class performance differentiation

• Supports both snooped and non-snooped traffic

• Supports isochronous non-snooped traffic

• Supports legacy snooped isochronous traffic

• Supports SMI, SCI and SERR error indication

1.2.4 I/O Controller Hub: Intel ICH7-M

• PCI Express base specification, revision 1.0a support

• Supports Intel high definition audio

• Low Pin Count (LPC) interface

• Firmware Hub (FWH) interface support

1.2.5 Azalia Audio System: ALC880

• Meets performance requirements for audio on PC2001 systems

• Supports 44.1/48/96/192 KHz DAC sample rate

• All ADCs support 44.1/48/96 KHz sample rate

• Applicable for 4 ch/192 KHz and 6 ch/96 KHz DVD-Audio solution