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Design of a Wide Tuning-Range CMOS 130-nm Quadrature VCO for Cell

Impedance Spectroscopy

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 Design of a Wide Tuning-Range CMOS 130-nm
Quadrature VCO for Cell Impedance Spectroscopy

Jorge Enrique Prada Rojas
Hamburg-Harburg
University of Technology
E-mail: jorge.prada@tuhh.de
Prof. Dr.-Ing. Wolfgang Krautschneider Dr.-Ing. Paola Vega Castillo
Institute for Nano- and Medical Electronics Instituto Tecnológico de Costa Rica
Hamburg-Harburg E-mail: pvega@itcr.ac.cr
University of Technology
E-mail: krautschneider@tuhh.de

γ:4Dipole4polarization σ
Abstract—Cell dielectric impedance spectroscopy is a novel ε' α:4ionic4diffussion
Rotation;4water4relaxation

specific4conductivity
technique for diagnosis of biological tissues, by characterizing β:4cellular4membrane

relative4permitivity
properties of the matter such as permittivity and conductivity. polarization

These properties can be measured by the phase difference be-

tween the voltage and the current signals applied to the biological
material under test. The impedance of the biological tissue can
be measured by means of a quadrature signal generator, which
should be capable to perform a wide tuning frequency in order
to obtain an insightful description of the biological material.
This work proposes the design of a wide tuning range 102 104 106 108 1010 1012 [Hz]
quadrature VCO, by using voltage controlled ring-oscillators
as injection-frequency dividers by 2, 3 and 4 of an injected Fig. 1. Different dispersion regions at frequency spectrum for cell permittivity
signal. In this work is also discussed the feasibility of designing and conductivity
the corresponding injection signal source by an LC tank based
differential VCO. The complete circuit is designed in IHP SG 130- →
−
nm technology, obtaining a continuous quadrature signal tuning The matter exposed to an electric field E produces a
→
−
range from 1.66 to 5 GHz. As one of the main qualities of the dielectric displacement D formulated as:
frequency-injected oscillator scheme, an important phase-noise →
− →
−
reduction is observed along the complete frequency range. D = ∗ 0 E (1)
where 0 is the vacuum permittivity. The complex dielectric
I. I NTRODUCTION permittivity ∗ is thus an insightful feature of matter rendered
Tracking diseases traits at the cellular level is becoming as a frequency dependent function. For a material under a
a new trend in the early detection and diagnosis of illnesses. periodical electric field, the complex dielectric permittivity
Some diseases disrupt the cellular characteristics resulting in follows:
distinguishable features from early stages [1]. In order to trace ∗ (ω) = 0 (ω) − i00 (ω) (2)
those features some techniques are already in use, such as the where 0 accounts for the relative permittivity and 00 for the
in-vivo bio-markers to label affected cells, or the dielectric energy losses. The later can be expressed in terms of the
spectroscopy. While techniques like the first are expensive to material conductivity as 00 = σ/ω0 [2].
conduct, the dielectric spectroscopy is simpler to implement
in in-vitro tests, where sample tissues can be tested several As used for matter characterization, the parameters 0 and
times, a larger variety of experiments can be run, and a σ, deployed in frequency domain, can be extracted to acknowl-
comprehensive sample characterization can be obtained. edge the structure response of biological cells exposed to an
electromagnetic wave [3]. Fig. 1 depicts the dispersion regions
Dielectric spectroscopy work principle is based on the α, β and γ, each conveying information about different cellular
interaction between matter and electromagnetic waves up to responses [1]. By contrasting the 0 and σ frequency responses
1011 Hz [2]. In contrast to optical spectroscopy, dielectric of cells from tissue sample cultures, it is possible to associate
spectroscopy can be implemented using electrical circuits that distinctive 0 and σ features with cell states and diseases. The
apply voltages and currents on the samples whose response conductance and permittivity from biological tissue samples
in frequency can be measured by spectrum analyzers. Al- can be extracted by means of an injected current. According to
though the measurements by optical spectroscopy are claimed [4], the in-vitro arrangement to characterize the sample tissue
to be high descriptive and precise at low temperatures [2], can be modeled as RC network, whose equivalent impedance
their implementation is complex and usually tied to stand- Zeq is formulated as:
alone stations. Conversely, a dielectric spectroscopy instrument
A l
may be fully-integrated, and thus the measurement can be Zeq = R − jXC =
+j 0 (3)
simultaneously run over several samples, and the results may σ·l ω 0 A
be gotten readily as electrical signals without further opto- where A and l are cross-section area and longitude of the cell
electronic coupling. patch respectively, and ω the angular frequency. If an harmonic
 Real
0° 0°
(This work scope) 180° cos(φ)
Sample
Oscillator L.P.F.
180° Imag
+ Frequency
I0 φ sin(φ)
_
L.P.F.
90° 270° 270°
90°
Fig. 2. System blocks diagram for measurement system
voltage signal with frequency ω is applied the cell patch, 
and σ are found to be proportional to the imaginary and real
components of the current phasor applied through the cell
patch, as follows:
IIM AG · l
0 = (4)
U · A · ω · 0
IREAL · A
σ= (5)
U ·l
This implies, that given a known applied voltage signal U ,
the resulting current phasor magnitude and phase shift can be
obtained by using an impedance measurement circuit.
Fig. 2 depicts the system block diagram for an impedance
measurement circuit, where the cell patch performs as the load
under test1 . The frequency range and the quadrature signals are
produced by a quadrature VCO. It’s prescribed in the extant
research that noticeable 0 and σ contrasts for breast cells are
found between 3 and 5 GHz [5], becoming a frequency range
of interest to detect malignant cell features. In [6], the results
shows insightful contrast in 0 between normal and malignant
liver cells for frequencies within 1 and 10 GHz. Therefore, the
wide tuning-range capability in the VCO design is desired.
The present report describes the design of the quadrature
wide tuning-range VCO intended to cover a frequency range
from 1 to 5 GHz for the impedance measurement system. The
work here described also aims to propose design methodology
for wide tuning-range VCO based on frequency division. This
design contributes to the endeavor seeking the development
a fully-integrated lab-on-chip, intended to the characterization
and detection of cellular diseases on in/vitro samples.
II. W IDE T UNING -R ANGE Q UADRATURE VCO
Single core LC based VCOs are known to reach higher
quality factors, and therefore, to be highly frequency selec-
tive. Although that may improve the phase-noise and power
performance, the high selectivity results in narrow tuning
frequency operation. Some references in the literature suggest
that phase-noise performance and tuning-range are opposite
design variables. Be the tuning range factor α defined as:
fmax − fmin
α=± · 100% (6)
fmax + fmin
References as [7], [8] prescribe that a single core LC VCO
α factor must be bounded up to ±15% or ±20% to achieve
1 This block diagram system is proposed in the framework of the project
Hochparalelisiertes Gigahertz-Mikrosystem zur Charakterisierung und Kondi-
tionierung von Zellen under direction of Dr.-Ing Paola Vega-Castillo and Prof.
Dr.-Ing Wolfgang Krautschneider at Institute of Nanoelectronics, TUHH
Band
Core VCO
frequencies
σ
f
3/4 f
1/2 f
1/2 f0 3/4 f0 f0 3/2 f0
ε' Freq. division Freq. mixing
Fig. 3. Example frequency plan for a wide-tuning range up- and down-
conversion system.
a reasonable phase noise. If larger α factors are desired,
0 frequency synthesis should be proceeded by frequency mixing
or division to replicate up- and down-converted versions of a
fundamental frequency range respectively, as depicted in Fig.
3. Frequency dividers-by-2 are commonly implemented using
source-coupled logic latched (SCL) or static CML dividers [9],
while frequency mixers are reported as Gillbert cells as single-
side band (SSB) mixers. Signal addition to cancel out side
bands is carried on by signal combiners. Signals at frequency
bands 1, 12 , 32 and 34 are taken at their respective node and
multiplexed to deliver a single system output. Although their
usefulness, the SSB based sideband VCOs demand complex
architecture and the implementation of mixers, combiners,
switches and signals multiplexers, which may result in large
power consumption and noise [7].
A. Injection-Locked Frequency Divider (ILFD)
As alternative to SSB based architectures, a wideband
output can be also obtained by tuning a core VCO at an
upper frequency sub-band and obtaining the rest of sub-bands
by successive frequency divisions. In that case, cascades of
frequency dividers can produce down-converted versions of the
VCO fundamental range [7]. The required frequency division
can be achieved by means of frequency injection locking [10].
By this technique, the frequency division by N can be obtained
by injecting a signal with frequency N f0 to an oscillator with
fundamental frequency f0 . In principle, the frequency injection
mechanism works similar to down-conversion mixing. In real
oscillators, several harmonics besides the fundamental are gen-
erated with distinctive power and later filtered by the low-pass
oscillator selectivity. If the oscillator is injected at a frequency
close to one of the oscillator harmonics, the oscillator output
can be frequency-locked to the injected signal, and thus its
own frequency can be controlled by the injected signal within
a locking range. Therefore, an oscillator can operate as an
injection-locked frequency divider (ILFD), whose concept is
illustrated in Fig.4. In order to improve the frequency locking,
progressive mixing of injected harmonics as proposed in [11],
[12], is depicted in Fig.5, enabling higher division ratios.
For differential LC and ring oscillators, the implementation
of the current injection from another oscillator, N times faster,
is typically conducted directly to the output nodes or by
injecting the current signal on top of the bias current of the
frequency divider.
B. ILFD Phase Noise
A remarkable feature of locked-frequency systems is that
they are phase synchronized with the injection source. This
implies that the phase-noise resulting out of the divider is at
 Lφ(Δf)
Nf0 f0 free-running phase noise

SSB Phase-noise
phase noise from input

Low-pass filter
(N-1)f0 ILFD phase noise

Offset frequency
Non-linearity Δf

Fig. 6. Phase-noise in frequency-locked systems

Fig. 4. Model scheme for an injection-locked frequency divider
1 2 3 4 5 6 7 8 9 10
f0 f [GHz]
4f0
(2f0) Div. by 2 Core VCO
Low-pass filter Div. by 3
Div. by 4
1.66 2.5 3.33 5.0 6.667 10

x2
Fig. 7. Frequency plan for this work
Non-linearity
Divider-by-2
I+

buffer buffer
Fig. 5. Two-step divider-by-four proposed in [11], [12] VDD I-
I+ Q-
I- Q+ Q+
Q- Design work
VVCO- VCO+ VCO-
least as good as the injected signal. Since frequency dividers scope
Divider-by-3 I+
I+

coupling
outline a rather low factor Q to widen their locking range, its

buffer buffer
I- I-
I+ Q-
free-running phase-noise is worsen. References as [10], [13], switch. cap I- Q+ Q+ Q+
VVCO+
[14], [15], [16] thoughtfully analyze the mechanisms behind VCO+ VCO-
Q- Q-

the injection frequency phenomena in oscillators and study Divider-by-4

Differential
Source follower
I+
the phase-noise performance in frequency-locked systems. Fig.

buffer buffer

Q-
Q+

6 illustrates a phase-noise performance comparison between
free-running and frequency-locked oscillators [15].
C. Quadrature ILFD
Quadrature harmonic signals are necessary to obtain the
imaginary and real components of the current phasor, as illus-
trated in Fig. 2. Quadrature VCO can be readily implemented
by coupling two differential LC VCO. If two LC VCO are
differential pair based, their super-harmonic coupling can be
realized by forcing counter-phase signals at their 2f0 nodes, for
instance, at the tail currents, as reported in references [17] and
[18]. Quadrature LC VCO are turned into frequency dividers
when injected by external signal. References [19] and [20]
report quadrature output LC based ILFD, which are attributed
outstanding phase-noise performances. Nevertheles, doubling
the LC VCO to produce quadrature output may largely increase
the area consumption due to the extension of planar inductors.
Alternatively, a ring oscillator with 2n stages can produce
quadrature signals, but just occupying a fraction of the LC
VCO area. ILFD implementations using 2-stage ring oscillators
are described in references as [21], [22] and [23]. Frequency
dividers based on ring oscillators are known to stand for wider
locking range than LC. However their quadrature accuracy is
expected to be lower.
III. D ESIGN S TRATEGY
The placement of the core VCO band set the initial
milestone to unfold the rest of the bands. The discussed
convenience of having a high-Q core VCO points to the
implementation of a LC based oscillator. If doing so, the
placement of the core VCO band towards the highest tier
I-
I+
I-
I+ Q-
VTAIL
Q+ 50Ω
I- Q+
Q-
VCO+ VCO-
Design work scope
(feasibility test) Design work scope
Fig. 8. Overall circuit diagram
helps to down-scale passives as the planar inductor, since its
inductance decreases when area and number of turns reduces.
Moreover, it’s observed that on-chip inductor setups tend to
show better Q factors when designed for less inductance and
higher frequencies [24]. A core VCO based on LC is the
source of harmonic signals, from which the output signals are
obtained by frequency division, as schematized in Fig. 7.
Quadrature signal generation may require two coupled LC
VCO cores. This approach doubles the inductor area, becoming
an expensive frequency divider implementation when several
division factors have to be practiced. In contrast, the 2-stage
ring oscillator can serve as ILFD and consume much less area,
although reducing Q factor. This design demands that quadra-
ture outputs have to be delivered across the entire frequency
range. By prioritizing aspects as frequency performance and
integrability over noise and accuracy, and taking advantage
of integer division factor, the ring oscillator based ILFDs is
chosen as the quadrature frequency divider, while the core LC
VCO band is placed at twice the highest frequency tier. The
low-pass phase-noise qualities of a frequency-locked ILFD,
as reported in [15], suggest that even the low phase-noise
performance of low-Q dividers can be redeemed by a high
quality injection source in the upstream, favoring the selection
of ring-oscillators as ILFD. The designed system is depicted
in Fig. 8.
 OutputVload:V50Ω V DD
FrequencyVplan
defintion
BiasVandVinput RD RD
sourceVfollwer
FrequencyVdivider
design BufferVcoupling Wn,in Wn,c Wn,c Wn,in

CouplingVILFD-VCO + +

CoreVVCOVdesign V IN+ + + V IN-

50Ω V OUT+ V OUT- 50Ω
Fig. 9. Design strategy flowchart - - - -

A. Backwards approach Fig. 10. Differential cross-coupled source follower

The backwards design strategy prioritizes the output fea-
InputDamplitudeDestimation
tures to design the system stages from the last to the first.
For this design work this approach is convenient because Requirement: GainDstageD
the output load requirements are given as start point (50Ω), diff.DoutputD50DmVp definition
and from that the design of the fittest stage to drive that
load sets the load impedance seen by the stage just before. ACDanalysisD@Df0 PSSDanalysis:DTHD
3-D.O.F.:DWn,in,DWn,c,DRD atDf0,DinputDamplitude
Since oscillator circuits are very sensitive of the connected 3-D.O.F.:Wn,in,DWn,c,DRD
output loads, the backwards approach offers from the first
ChoseDsetDofDgainDcompliant
iteration a good approximation of the actual load that every min.DWn,inD
stage has to drive. If it succeeds to find functional stages,
it makes the system reliable to operate as a whole. Fig. 9 SelectDtheDlowestDTHD
depicts the backwards strategy as flowchart, starting from
the specifications and sequentially developing stages from the Fig. 11. Design strategy flow-chart for the differential source follower
output to the core VCO.

A set of design variables named as Wn , Wp , Wp,var ,

B. Differential source follower
The design specification requests the output stage be able
to drive a load of 50Ω while keeping a signal amplitude
of 100 mVpp . Two main concerns motivate the optimization
of the source follower scheme. The large transconductance
needed to overcome the gain-shrinking effect of the 50Ω load
may represent wider Wn with the undesirable side effect of
a conspicuous power consumption. On the other hand, larger
parasitic gate capacitances and DC gate voltage have to be
stood by the previous stage. Therefore, a differential cross-
coupled source follower was presented, to enable acceptable
gains without the excessive area and power expenditure of
the conventional single-ended source follower architecture.
The alternative differential architecture includes two additional
degrees of freedom such as the drain resistor RD and the cross-
coupled NMOS width Wn,c . The design starts by assuming a
DC bias point at the input gate. Furthermore, the stage design
must aim to reduction of distortion, which it is desirable to
have the lowest possible. The design strategy is summarized
in the flow-chart in Fig. 11.
C. ILFD design
The ILFD stage circuit, within each of the ring oscillator
stages, is shown in Fig. 12. In free-running operation, the ILFD
can be tuned by signal VCT R , which controls an extra PMOS
load and drives a f actor times the current on the output node,
so that the load variations are enough to shift the free-running
ILFD’s f0 , while still keeping the MOSFET in saturation and
fulfilling the oscillation conditions.
Wn,x , Wtail and Wtail,x are defined for the ILFD design. In
order to narrow down the design variable space, the design
methodology starts by setting the DC bias point targets at
different nodes in the circuit. The MOSFET QS small-signal
model parameters are set according to the bias target, and
MOSFET widths are swept until find a design point compliant
with the bias target. Once the ILFD DC compliant devices
set is chosen, the QS small-signal is applied to calculate
the input impedance and the stage transfer function H (jω).
Since the ILFD stages are loop-chained in a 2-stage ring
oscillator, the input stage load must be accounted as part of the
output load when formulating the transfer function. Moreover,
additional loads as the buffer input impedance towards the
output coupling stage must be accounted. By every WP sweep
step the transfer function is evaluated at the target f0 to check
if phase-shift completes 90 deg and gain exceeds 1 there. If
yes, this sets of widths is stored as one Barkhausen compliant
set and the H (jω) calculation starts over again by moving to
the next DC compliant set of widths. At the end, the design
having the minimum Wn,tail is selected among Barkhausen
compliant designs, because this is the less-power consuming
compliant design. The described design strategy is illustrated
in the flow-chart in Fig. 13.
D. VCO feasibility design assessment
LC oscillators typically feature higher quality factors than
RC based oscillators and show better phase-noise performance.
Nevertheless, the implementation of on-chip inductors imposes
design challenges in regard of power consumption, area and
tunability. Therefore, the design of LC oscillators has to
 V DD

Wp Wp V CTR
V BIAS factor*Wp

Vout+ Vout-

in+ Wn Wn in-
Wn-x Wn-x

VTAIL,1 Wn,tail Wn,tail-x

V TAIL,2

Fig. 12. ILFD design stage

Fig. 14. Scree-shot HFSS session, inductor with etched substrate
Input data:
Highest°f0°and°bias°point:°:set°of°parametersH
9
xu10
5.5
ILFD−by−2
5.06uGHz ILFD−by−3
Sweep°on°Wn 5
ILFD−by−4
Wn°selection 4.5

Frequencyu[Hz]
Sweep°on°Wp 4
3.33uGHz
Wp,var,°Wn,x°selection 3.5
by°current°comparison
3
2.55uGHz
Wtail°and°Wtail,x°selection 2.5
by°half°current
2 1.67uGHz
Calculation°input
Selected°geometry impedance 1.5u
0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8
ILFDucontroluvoltageu[V]
Calculation°of
transfer°function
Fig. 15. Free running ILFD’s frequency tuning ranges
Input°impedance
Meet°φ=90°,°gain°>1°? from°loads

Min.°power°consumption
:select°set°with°min.°WtailH
Fig. 13. ILFD design strategy flow-chart
account from the beginning on the real inductor characteristics
described by the manufacturer. Since no measured data were
available at the time, planar inductors were modeled account-
ing the IHP SG 130nm technology process in the software
HFSS, as shown in Fig. 14. The S-Parameters were extracted
for a collection of modeled inductors, and from the tank
parasitics, the MOSFET needed to produce stable oscillations
within the range of interest were estimated.
IV. S IMULATION R ESULTS
The system circuit described in Fig. 8 was designed and
modeled with the IHP 130-nm BiCMOS technology and simu-
lated using Cadence Virtuoso. Following the backwards design
approach, source followers and load buffers where specified
and simulated, obtaining output signal excursion no less than
100 mVpp, in agreement with the requirements. The ILFDs
were designed as 2-stage ring-oscillators with division factors
2, 3 and 4, by means of tail current and direct signal injection
from the core VCO. The ILFDs were firstly simulated as free-
running voltage-controlled oscillators using the Cadence PSS
analysis, whose results as illustrated in Fig. 15. Later their
frequency-locking range was simulated using PXF analysis,
showing the ILFDs can be locked to the harmonic signal
from the core VCO, if they are properly tuned. Phase-noise
simulations were conducted over the three ILFD for free-
running and frequency-locked conditions. As formulated in
the theory [15], the phase-noise performance at frequency-
locked operation evidences a noticeable improvement at low
offset frequencies. Quadrature accuracy was measured over
one-period I-Q outputs time-domain differences from results
available by PSS analysis at different frequencies, finding
quadrature offsets no larger than 0.4, 0.6 and 0.1 degrees for
ILFD-by-2, -3 and -4 respectively, as seen in Fig. 16. The DC
power consumption measured at each ILFD is broken down in
Table I. The power consumption is clearly dominated by the
differential source followers due to their low output impedance
(50Ω). In contrast, blocks as the ILFD and buffer prove to
consume dramatically less power, proving the effectiveness
of the low-power design strategy approach for those stages.
The core VCO was modeled and simulated in order to prove
the feasibility by using planar inductor parameters. By means
of HFSS, several inductor geometries on silicon and etched
substrate were tested and S-parameters extracted to run the
circuit simulation. A 900 nH differential octagonal inductor
only allowed VCO operation between 8.69 and 10 GHz. For
lower frequencies the inductor loses overcame the VCO gain
and no start-up condition was possible. Results are illustrated
in Figures 17 and 18.
 I/Qdphasedatdthed50Ω output −3 Tankiadmitance,iL=900pH
xi10

NetiLCitankiadmitancei[S]
90.2
15
90.1
10
90
MeasureddI/Qdphased[°]

89.9 5 8.42iGHz

89.8 0

89.7 2 4 6 8 10 12 14 16
Frequencyi[Hz] xi10
9

89.6
ILFD−by−2 Fig. 17. Core VCO tank admittance, using inductor L=900 nH
89.5 ILFD−by−3
ILFD−by−4
89.4d 10 LCHVCOHtuningHfeature,HL=900pH
0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 xH10

OscillationHfrequencyH[Hz]
ILFDdcontroldvoltaged[V]
2.5

2
Fig. 16. Quadrature phase results at free-running ILFD’s
1.5 500Hf
TABLE I. P OWER CONSUMPTION COMPARISON FROM ILFD- BY-2, -3 900Hf
AND -4. 1
ILFD-by-2 ILFD-by-3 ILFD-by-4
0.5
Circuit Section Power [mW] Power [mW] Power [mW] 0 0.2 0.4 0.6 0.8 1
VariableHcapacitorH[F] xH10
−12
Diff. source followers 5.47 5.40 5.44
Output Buffer 1 0.175 0.096 0.038
Fig. 18. Core VCO tank oscillation frequency, by different varactor
Output Buffer 2 0.145 - -
capacitances
Injector - 0.01 -
ILFD 2-stages 0.181 0.176 0.166
TOTAL 5.98 5.69 5.65
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