PD - 94390

IRLI3615
HEXFET® Power MOSFET
l Advanced Process Technology
D
l Ultra Low On-Resistance VDSS = 150V
l Dynamic dv/dt Rating
l 175°C Operating Temperature
RDS(on) = 0.085 Ω
l Fast Switching G
l Fully Avalanche Rated
ID = 14A…
S

Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve extremely low on-resistance per silicon area.
This benefit, combined with the fast switching speed and ruggedized device
design that HEXFET Power MOSFETs are well known for, provides the
designer with an extremely efficient and reliable device for use in a wide variety
of applications.

The TO-220 Fullpak eliminates the need for additional insulating hardware in
commercial-industrial applications. The moulding compound used provides a
high isolation capability and a low thermal resistance between the tab and TO-220 FULLPAK
external heatsink. This isolation is equivalent to using a 100 micron mica barrier
with standard TO-220 product. The Fullpak is mounted to a heatsink using a
single clip or by a single screw fixing.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 14 …
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 9.8 A
IDM Pulsed Drain Current  56
PD @TC = 25°C Power Dissipation 45 W
Linear Derating Factor 0.30 W/°C
VGS Gate-to-Source Voltage ±16 V
EAS Single Pulse Avalanche Energy‚ 340 mJ
IAR Avalanche Current 8.4 A
EAR Repetitive Avalanche Energy 4.5 mJ
dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 3.3
°C/W
RθJA Junction-to-Ambient ––– 65

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IRLI3615
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 150 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.18 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.085 VGS = 10V, ID = 8.4A „
––– ––– 0.095 Ω VGS = 5.0V, ID = 8.4A „
VGS(th) Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 14 ––– ––– S VDS = 50V, ID = 8.4A
––– ––– 25 VDS = 150V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 120V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 16V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
Qg Total Gate Charge ––– ––– 140 ID = 8.4A
Qgs Gate-to-Source Charge ––– ––– 9.5 nC VDS = 120V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 53 VGS = 10V, See Fig. 6 and 13 „
td(on) Turn-On Delay Time ––– 8.3 ––– VDD = 75V
tr Rise Time ––– 20 ––– ID = 8.4A
ns
td(off) Turn-Off Delay Time ––– 110 ––– RG = 6.2Ω, VGS = 10V
tf Fall Time ––– 53 ––– RD = 8.9Ω, See Fig. 10 „
Between lead,
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.) D
nH
from package
LS Internal Source Inductance ––– 7.5 ––– G
and center of die contact
Ciss Input Capacitance ––– 1600 ––– VGS = 0V S

Coss Output Capacitance ––– 290 ––– pF VDS = 25V

Crss Reverse Transfer Capacitance ––– 150 ––– ƒ = 1.0MHz, See Fig. 5

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
D
IS Continuous Source Current MOSFET symbol
––– ––– 14…
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 56
(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 8.4A, VGS = 0V „
trr Reverse Recovery Time ––– 180 270 ns TJ = 25°C, IF = 8.4A
Q rr Reverse RecoveryCharge ––– 1130 1700 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by „ Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. ( See fig. 11 ) … Caculated continuous current based on maximum allowable
‚ Starting TJ = 25°C, L = 9.5mH junction temperature; for recommended current-handling of the
RG = 25Ω, I AS = 8.4A. (See Figure 12) package refer to Design Tip # 93-4.
ƒ ISD ≤ 8.4A, di/dt ≤ 510A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.

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 IRLI3615

 
100 100 VGS
VGS
TOP 15V TOP 15V
10V 10V
7.0V 7.0V

I D , Drain-to-Source Current (A)

I D , Drain-to-Source Current (A)

5.5V 5.5V
4.5V 4.5V
4.0V 4.0V
3.5V 3.5V
BOTTOM 2.7V BOTTOM 2.7V

10 10
2.7V
2.7V


20µs PULSE WIDTH
T = 25 C
J °
1

20µs PULSE WIDTH
T = 175 C
J °
1
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

100 3.5

ID = 14A
R DS(on) , Drain-to-Source On Resistance


TJ = 25 ° C
I D , Drain-to-Source Current (A)

3.0


TJ = 175 ° C
2.5
(Normalized)

2.0
10
1.5

1.0

0.5

1
V DS = 50V
20µs PULSE WIDTH 
VGS = 10V
0.0
2.0 3.0 4.0 5.0 6.0 7.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
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IRLI3615

100000 20
VGS = 0V, f = 1 MHZ 
ID = 8.4A


Ciss = Cgs + Cgd, Cds SHORTED VDS = 120V

VGS , Gate-to-Source Voltage (V)

Crss = Cgd VDS = 75V
16 VDS = 30V
10000 Coss = Cds + Cgd
C, Capacitance(pF)

12
Ciss
1000

Coss 8

Crss
100
4

10 0

FOR TEST CIRCUIT
SEE FIGURE 13
1 10 100 1000 0 20 40 60 80 100 120 140
QG , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

100
1000
ISD , Reverse Drain Current (A)

OPERATION IN THIS AREA LIMITED

BY RDS(on)
ID, Drain-to-Source Current (A)

100
10


TJ = 175 ° C

10
100µs

1ms
1


TJ = 25 ° C 1
10ms
Tc = 25°C
Tj = 175°C
Single Pulse

V GS = 0 V
0.1
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1 10 100 1000
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRLI3615

14
RD
VDS

12 VGS
D.U.T.
RG
+
I D , Drain Current (A)

10 -VDD

8
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6

Fig 10a. Switching Time Test Circuit

4

VDS
2 90%

0
25 50 75 100 125 150 175
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs. td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

10
Thermal Response (Z thJC )

D = 0.50

1
0.20

0.10


0.05
PDM
0.1 0.02
t1
0.01
 SINGLE PULSE t2


(THERMAL RESPONSE)
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLI3615


1000
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 3.4A
1 5V 5.9A
800 BOTTOM 8.4A

L D R IV E R
VDS
600

RG D .U .T +
V
- DD 400
IA S A
20V
tp 0 .0 1 Ω

200
Fig 12a. Unclamped Inductive Test Circuit

0
25 50 75 100 125 150 175
V (B R )D SS Starting TJ , Junction Temperature ( °C)
tp

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

IAS
Current Regulator
Fig 12b. Unclamped Inductive Waveforms Same Type as D.U.T.

50KΩ

12V .2µF
QG .3µF

+
10 V V
QGS QGD D.U.T. - DS

VGS
VG
3mA

IG ID
Charge Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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 IRLI3615

Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T
• Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• Driver same type as D.U.T. VDD
-
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test

Driver Gate Drive

P.W.
Period D=
P.W. Period

VGS=10V *

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 14. For N-Channel HEXFETS

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IRLI3615
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
1 0 .6 0 (.4 1 7 ) 3 .4 0 (.1 3 3 )
ø 4 .8 0 (.1 8 9 )
1 0 .4 0 (.4 0 9 ) 3 .1 0 (.1 2 3 ) 4 .6 0 (.1 8 1 )
2 .8 0 (.1 1 0 )
-A - 2 .6 0 (.1 0 2 )
3 .7 0 (.1 4 5 ) L E A D A S S IG N M E N T S
3 .2 0 (.1 2 6 ) 7 .10 (.2 8 0 ) 1 - G A TE
6 .70 (.2 6 3 ) 2 - D R A IN
3 - S O U RC E
1 6 .0 0 (.6 3 0 )
1 5 .8 0 (.6 2 2 )
1 .1 5 (.0 4 5 ) N O TE S :
M IN.
1 D IM E N S IO N ING & T O L E R A N C ING
P E R A N S I Y 1 4 .5 M , 1 9 8 2
1 2 3
2 C O N T R O L L IN G D IM E N S ION : IN C H .
3.3 0 (.1 30 )
3.1 0 (.1 22 )
-B -
1 3 .7 0 (.5 4 0 )
1 3 .5 0 (.5 3 0 )
C
D

A
0.4 8 (.0 1 9 ) B
0 .9 0 (.0 35 ) 3X
1 .4 0 (.0 5 5) 3 X 0 .7 0 (.0 28 ) 0.4 4 (.0 1 7 )
3X
1 .0 5 (.0 4 2) 2 .8 5 (.1 1 2 )
0 .2 5 (.0 1 0 ) M A M B 2 .6 5 (.1 0 4 ) M IN IM U M C R E E P A G E
2 .5 4 (.1 0 0 ) D IS T A NC E B E TW E E N
2X A -B -C -D = 4.8 0 (.1 8 9 )

Part Marking Information

TO-220 Fullpak

EXAMPLE: T HIS IS AN IRFI840G

WIT H ASSEMBLY PART NUMBER
LOT CODE 3432 INT ERNAT IONAL
RECT IFIER IRFI840G
ASSEMBLED ON WW 24 1999
LOGO 924K
IN T HE ASSEMBLY LINE "K" 34 32
DAT E CODE
ASSEMBLY YEAR 9 = 1999
LOT CODE WEEK 24
LINE K

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.01/02
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