ISSCC 2013 / SESSION 19 / WIRELESS TRANSCEIVERS FOR SMART DEVICES / 19.
19.4 A Universal GNSS (GPS/Galileo/Glonass/Beidou) SoC
with a 0.25mm2 Radio in 40nm CMOS
Chun Geik Tan1, Fei Song1, Tieng Yi Choke1, Ming Kong1,
De-Cheng Song1, Chee-Hong Yong1, Weimin Shu1,
Zong Hua You2, Yi-Hsien Lin2, Osama Shanaa1
1
MediaTek, Singapore, Singapore, 2MediaTek, Hsinchu, Taiwan
Global Navigation Satellite Systems (GNSS) have a spectrum allocation shown
in Fig. 19.4.1. The time-to-first-lock and location accuracy can be improved
through simultaneous reception of two different satellite signals. This usually
necessitates the use of two dedicated receivers [1] driven by a single and some-
times two separate synthesizers, which increases complexity, die area, and most
importantly current consumption. To solve this problem, the architecture shown
in Fig. 19.4.1 is proposed. The SoC consists of one single reconfigurable low-IF
receiver, a single fractional-N frequency synthesizer, and a digital baseband
processor. Since different satellite signals are uncorrelated and are buried well
below the noise floor, they can be amplified and downconverted by the same
RF/analog chain as an image of one another, and then separated in the digital
domain by the corresponding correlator and signal processor. In the case of
simultaneous GPS/Galileo and Glonass dual reception, the LO (fLO_GG) is set to
1588.608MHz. As a result, the GPS/Galileo signal becomes the image of the
Glonass satellite signal with an IF frequency of 13.1MHz. Similarly, when the LO
(fLO_GB) is set to 1568.256MHz, the resulting IF frequency is about 7.1MHz for
GPS/Galileo and Beidou dual reception. For GPS/Galileo-only reception, the LO
(fLO_GPS) is set to 1571.328MHz resulting in an IF frequency of 4.092MHz.
Figure 19.4.2 depicts the schematic of the single-ended inductorless noise-can-
celling complementary LNA with current-mode output. The cascode device of
the LNA is split into two sections to form a main and an auxiliary branch, which
with a shunt feedback resistor RF forms the required input matching. The volt-
age gain of the auxiliary branch is around 20dB, which allows a large value for
RF for low NF. The drain noise current of input devices M1p/M1n is split between
the main and auxiliary path cascodes, then is fed back and converted into volt-
age at the input via the shunt feedback resistor RF and subsequently is inverted
by M1p/M1n. As a result, the noise of M1p/M1n is partially cancelled with an opti-
mum split ratio N between main and auxiliary paths of 3:1 in this design. The
common-mode voltage at the LNA output is set by the feedback resistor RF and
large resistor RB. The AC current from the main LNA is fed into the current-driv-
en single-balanced passive mixer with 25% duty-cycle LO signals. Large capac-
itors, Cin, are connected between the mixer IF output and ground to avoid satu-
rating the baseband filter by far-out blockers. The mixer IF AC current is fed into
a current-driven OpAmp-RC filter/PGA, which is a cascade of two reconfigurable
Butterworth biquad stages. The first biquad stage is a Thomas-Tow II filter and
has a fixed gain while the second biquad is a multi-feedback (MFB) circuit that
has a built-in PGA function with 26dB AGC range in 2dB gain steps. In
GPS/Galileo-only reception, the first biquad is configured as a complex BPF with
a center frequency of 4MHz and a programmable bandwidth of 2MHz/4MHz,
respectively, while the second biquad is configured as a real LPF with 9MHz
bandwidth. In GPS/Galileo plus Glonsss or Beiduo dual reception, both biquads
are configured to have the same real LPF 3dB corner frequency of 15MHz or
9MHz, respectively. The single-pole open-loop gain of the OpAmps is absorbed
into the filter s-domain transfer function by pre-distorting the RC values of the
relatively low-Q filter to keep the overall filter frequency response unchanged.
This highly relaxes the gain-bandwidth requirement of filter OpAmps, hence
reduces supply current. An RC calibration scheme is activated upon power up,
which injects one test tone at a well-known point on the stopband of the filter
itself, while the digital baseband tunes the filter cap array until the expected fil-
ter rejection is met. The receiver has a total voltage gain of 78dB. A DC-offset
cancellation loop injects differential DC current at the input of the second biquad
to keep the I/Q DC-offset voltage <100mV. The 9b I/Q SAR ADC has a 1Vpp full
scale to accommodate large interferer signals and a 66.192MHz sampling clock
for dual reception, which is dropped to 16.368MHz for GPS/Galileo-only mode
to save current.
334 • 2013 IEEE International Solid-State Circuits Conference
A two-stage differential ring VCO topology, which oscillates at the LO frequency
and inherently generates quadrature LO signals, is adopted instead of an LC VCO
mainly for compact area and immunity to magnetic coupling from multiple on-
chip interferers. The basic delay cell shown in Fig. 19.4.3 is composed of a
PMOS differential pair with complementary latches to compensate resistive loss.
The ring VCO is tuned by a set of MOS varactors connected at the output of each
delay cell for low KVCO and low phase noise. For VCO frequency calibration, the
capacitor bank is preset to the middle sub-band, and the core bias current is
increased until the VCO oscillates within the range between 1.47GHz and
1.67GHz, after which the 5b capacitor bank array is adjusted until the VCO oscil-
lates at target LO frequency. The ΔΣ fractional-N PLL with loop bandwidth of
700kHz exhibits RMS integrated phase error of 3.4° at 1588.608MHz for a refer-
ence clock frequency of 26MHz, while drawing 2.4mA. The measured phase
noise is plotted in Fig. 19.4.4.
Both LNA and VCO are vulnerable to supply noise ripple dominated by the clock
of the integrated 1.8V DC-DC converter. Therefore, two dedicated 1.8V-to-1.3V
ripple-cancelling cap-less LDOs are used to provide sufficient PSRR over a wide
frequency range, as shown in Fig. 19.4.4. Path 1 and path 2 can become out-of-
phase at LDO output by properly choosing the value of Cadd, resulting in the AC
PSRR response of the two paths to be aligned and cancelled out. The ripple-can-
celling LDO achieves better than 50dB PSRR at the DC-DC 1.6MHz switching
clock frequency.
The SoC is fabricated in a 40nm digital CMOS process and is housed in a 32-pin
6mm×6mm QFN package. Figure 19.4.5 shows the measured continuous-wave
(CW) input blocker level at which the GPS signal CNR degrades by 3dB as a
function of blocker offset frequency and compares the result to that of the LC-
VCO based GPS receiver in [6]. In this blocking test, no front-end SAW filter is
used between the antenna and the SoC RF input. When using a SAW filter, tol-
erable modulated blockers at the GPS antenna from other wireless radios are
also shown in Fig. 19.4.5, which meets all required blocker performance from
such radios on a phone platform assuming additional 15dB isolation to the PCS-
DCS antenna. Figure 19.4.6 summarizes the measured performance of this work,
which shows comparable performance to other previously reported papers that
use inductors in VCO and LNA circuits. The SoC occupies 6.4mm2 die area, of
which only 0.25mm2 is occupied by RF and analog circuitry. The die photo in Fig.
19.4.7 shows no on-chip inductors.
References:
[1] Nan Qi, et al., “A Dual-Channel Compass/GPS/Glonass/Galileo
Reconfigurable GNSS Receiver in 65nm CMOS With On-Chip I/Q Calibration,”
IEEE Trans. Circuits and Systems-I, vol. 59, no. 9, pp. 1720-1732, Aug. 2012.
[2] Kuang-Wei Cheng, et al. “A 7.2mW Quadrature GPS Receiver in 0.13μm
CMOS,” ISSCC Dig. Tech. Papers, pp. 422-423, Feb. 2009.
[3] J-M Wei, et al. “A 110nm RFCMOS GPS SOC with 34mW -165dBm Tracking
Sensitivity,” ISSCC Dig. Tech. Papers, pp. 254-255, Feb. 2009.
[4] Paul Yu, et al, “A 1.2mm2 Fully Integrated GPS Radio With Cellular/WiFi Co-
existence,” IEEE Custom Integrated Circuits Conf., pp. 1-4, Sept. 2010.
[5] Hyunwon Moon, et al. “A 23mW Fully Integrated GPS Receiver with Robust
Interferer Rejection in 65nm CMOS,” ISSCC Dig. Tech. Papers, pp. 68-69, Feb.
2010.
[6] S. Wu, et al, “A GPS/Galileo SoC with Adaptive In-Band Blocker Cancellation
in 65nm CMOS,” ISSCC Dig. Tech. Papers, pp. 1892-1901, Feb. 2011.
978-1-4673-4516-3/13/$31.00 ©2013 IEEE
 ISSCC 2013 / February 20, 2013 / 10:15 AM

Figure 19.4.1: The digitally-assisted GNSS SoC architecture and block Figure 19.4.2: Simplified current-mode RX front-end schematic with partial
diagram. noise cancellation.

Figure 19.4.3: Proposed topology of two-stage ring VCO with ripple-cancelling Figure 19.4.4: Measured VCO phase noise at 1588.608MHz with DC-DC
LDO. supply

19

Figure 19.4.5: Measured receiver out-of-band blocking performance and Figure 19.4.6: Measured SoC performance summary and comparison with
comparison with LC-VCO-based GPS receiver in [6]. other previously reported papers.

DIGEST OF TECHNICAL PAPERS • 335

 ISSCC 2013 PAPER CONTINUATIONS

Figure 19.4.7: GNSS SoC die micrograph showing no on-chip inductors.

• 2013 IEEE International Solid-State Circuits Conference 978-1-4673-4516-3/13/$31.00 ©2013 IEEE