.

Dual Split-Three Segment Capacitor Array Design Based

Successive Approximation ADC for Io-T Ecosystem

Savitha M, Venkat Siva Reddy,

School of Electronics and Communication, REVA University Bangalore

ARTICLE INFO ABSTRACT

Article history: The exponential rise in technologies and allied application demands have
Received 00 December 00 revitalized academia-industries to achieve more efficient and productive systems
Received in revised form 00 January 00 amongst which semiconductor devices do have irreplaceable dominance. In last few
Accepted 00 February 00
years, Internet-of-Things (IoTs) have grown significantly to meet major up-surging
demands of social, scientific, businesses as well as defence purposes. However,
Keywords: achieving optimal performance in IoT-ecosystem decisively depends of device’s
efficacy to enable ultra-low power, fast-processing, reliable and miniaturized space
Internet of Things, Successive features. To meet upcoming demands of 24 billion IoT users in 2020, while enabling
Approximation register, SAR- energy-efficient, sensibly-accurate and swift-processing systems, this research
ADC, Digital to Analog emphasizes on developing a novel Successive Approximation Register-Analog-to-
Converter, CDAC, Linearity, Digital (SAR-ADC) design with augmented (minimum) Capacitive Array Digital-
Area. to-Analog (DAC) converter. SAR-ADC being an inevitable device for ultra-
, wideband and Wireless Sensor Networks (WSNs) which has been primarily used in
IoT-ecosystem requires optimal SAR-ADCs to assure accurate, fast, energy-
efficient, reliable performance for sensing and communication with peer terminals.
. To meet these demands, in this paper a novel Dual-Split-Three-Section (DSTS)
capacitor array DAC (DSTS-CDAC) has been proposed to perform 14-bit SAR-
ADC function while retaining Signal-to-Noise Destruction Ratio (SNDR) of 67.9dB
for the ADC. The use of monotonic switching scheme exhibited reduced capacitive
array power consumption for 14-bits CDAC. Furthermore, it requires 185 times
unit capacitances on contrary to the conventional SAR-ADC designs, which
requires 256 times unit capacitances in a capacitive array. A significant reduction
of 28% area too applauds proposed design for low cost CMOS development. The
proposed CDAC model can be of vital significance for noise-resilient sampling of
high frequency differential input signals.

to achieve more efficient and productive systems amongst

which semiconductor devices do have irreplaceable
I. INTRODUCTION dominance. In last few years, Internet-of-Things (IoTs)
The exponential rise in technologies and allied have grown significantly to meet major up-surging
application demands have revitalized academia-industries demands of social, scientific, businesses as well as defense
purposes. Undeniably, the high pace growth and

* Corresponding author. Tel.: +9l9449332086 email-address: savith73@gmail.com

Fax number :08257-232644
Peer review under responsibility of xxxxx.
xxxx-xxxx/$ – see front matter © 2014 xxxxxxxx. Hosting by Elsevier B.V. All rights reserved.
http://dx.doi.org/10.1016/j.aebj.2014.10.012
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000
proliferation of IoT era has demanded the devices with
enriched technologies, augmented computational efficacy,
energy-efficiency and reliable (say, optimal-accurate)
performance. Reviews [1] state that the volume of the
functional internet connected or communicating devices
might up-surge up to 24 billion by the year 2020 and
considering the fact that these all devices would embody
augmented sensing, data acquisition and computing
efficacy. Key technologies such as Low Power Lossy
Networks (LLNs) a key variant of the Wireless Sensor
Networks (WSNs) would require high rate, reliable and
energy-efficient components to meet contemporary IoT-
ecosystem demands. Undeniably, even in current situation
the technologies under function require power efficient,
optimal sensing accuracy, and high-speed data
transmission to meet Quality of Service (QoS) demands.
Such demands would even continue up surging to facilitate
Bigdata computation and allied purposes such as IoT
communication, IoT assisted smart city, Machine-to-
Machine (M2M) communication [2]. These all facts
indicate irreplaceable role of high efficient devices,
especially Silicon Complementary Metal Oxide
Semiconductor (CMOS) devices to enable data sensing,
processing and decision making [3]. The ultra-low power
consumption and fast computation are the predominant
need of a wide range of integrated circuits-based systems
including sensor networks, medical equipment’s,
communication systems, industrial monitoring and control.
Considering technologies up-surge and its efficacy, in the
last few years the ongoing miniaturization of circuits and
allied technologies, especially low transistor channel length
inversely augments the energy performance of digital
circuits due to reduced capacitance at the circuit nodes.
This as a result augments possibility and scope of the
digital domain for signal processing, storage, computation
and control. On contrary, the analog domain features are
closer to the physical events and hence requires robust
interface circuits in between the analog domain and
functional processing domain, called Analog-to-Digital
converters (ADCs). To achieve optimal performance
developing enhanced devices such as ADC converter
and/or Digital-to-Analog Converters (DAC) can be of
paramount significance. In this relation, industry has been
making effort to design more efficient ADCs so that the
pace of emerging IoT-ecosystem demands (energy-
efficient, reliable, fast, memory-efficient, etc) could be
availed. Amongst the major ADC designs, the Successive
Approximation Register (SAR) ADC designs date back to
the 1950s and was exploited significantly for CMOS in the
1970s. The inception applications were primarily the
telephony and relatively low-speed instrumentations and
continued primarily being used for the same purposes till
year 2000. However, development in technologies lead
emergence of the different ADC topologies to enable high-
end processing, primarily high-end audio/video
requirements [4][5]. The ADC key topologies like
oversampling ADC, folding and pipelined ADC
2
architectures played decisive role towards high-end signal
processing purposes; however, entering the era of sub-100-
nm CMOS we witnessed rebound of the SAR topology
cashing in on its compatibility with aggressively scaled
“digital” process technology. This as a result revitalized
academia-industries to achieve more efficient ADC
architecture with better performance.
Considering application specific scenarios, SAR-ADCs
are extensively applied in varied communication systems
including WSNs demanding low-power converters because
of low active circuitry. The classical SAR-ADC embodies
a comparator, a SAR, a capacitive-array DAC (CDAC) and
a sample and hold (S/R) circuit designed by the capacitive
DAC itself [4]. In the classical ADC architecture, the
sampled input voltage is successively approximated which
is then followed by the estimation of the output digital bits
by means of comparison steps. Undeniably, the sequential
functions of the SA algorithm has classically been the
limitation for accomplishing high-speed operation,
however the ever-increasing augmentation in CMOS
technologies and designs, medium resolution (8 to 10b)
SAR-ADCs have achieved sampling rates of several tens of
MS/s [5]. The low-power features and moderate speed
enabled SAR-ADC to perform better for digital
communication and hence makes its suitable for IoT
ecosystem [4]. Considering SA architectures as low power
model identifying optimal design where the maximum
power savings could be achieved is vital. Typically, the
major power dissipation takes place in CDAC component
of SAR-ADC architecture. This as a result motivates
authors to exploit optimal design of CDAC to achieve
optimal function with minimum possible heating problem.
Towards this goal, numerous efforts including capacitive
array DAC structure with single splitting capacitor have
been recommended. Split capacitor CDAC design have
been found efficient to achieve minimum power dissipation
while retaining better linearity characteristics such as
Differential Non-linearity (DNL) and Integral Non-
linearity (INL) values in comparison to the classical
binary-weighted capacitor DAC models. Noticeably, with
increase in resolution, the total number of capacitances too
increases that eventually results into increased power
dissipation and compromised computation speed. It can be
considered as the driving force behind the current research.
In this research paper, a novel Dual-Split-Three Segment
Capacitor Array DAC Design Based Successive
approximation ADC for IoT-Ecosystem has been
developed. Unlike classical multi-split capacitor design, we
applied two split capacitors with three segments in a
capacitive array that eventually augment power efficiency
as well as the speed of the SAR-ADCs making it suitable
for IoT communication systems. To assess linearity
performance of the proposed SAR-ADC design both
theoretical as well as simulation methods have been
applied. Simulation results exhibited that the proposed
DSTS-CDAC model can achieve better linearity with DNL
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000
of the range within ±0.5 LSB and standard deviation
(capacitor) of merely 0.02%. The14-bit SAR-ADC model
designed with DSTS DAC structure employed 1.5V supply
and 100kSps sampling frequency, while the ADC retained
SNDR of 68.9dB.
The other sections of this manuscript are divided as
follows. Section II discusses related work, followed by
proposed method and its implementation in Section III.
Section IV discusses the results and allied inferences while
Section V presents overall research conclusion and future
scopes. References used in this research are presented at
the end of the manuscript.
II. RELATED WORK
1. The up-surging significance of fast, high
rate and power efficient VLSI systems, a number of efforts
have been made globally, amongst which developing
ADC/DAC systems have always been the dominating one.
This section puts a snippet of the key researches made in
last few years to achieve better SA-ADC design. Mauro
Santos et al. [6] carried out survey on analog to digital
converter. As an augmented model, Zhou et al. [7] applied
a split capacitor DAC structure coupled with Merged
Capacitor Switching (MCS) technique to reduce the total
power consumption. Additionally, authors found that the
use of a dynamic comparator without pre-amplifier can be
of utmost significant to achieve better energy efficiency.
Saberi et al. [8] used capacitive array DAC based SA-
ADCs for ultra-low-power applications and found it
promising to meet energy efficient and stability,
particularly for low-power applications. A low-energy
capacitor switching technique was applied by Shakibaee et
al. [9] to design a power efficient SAR-ADC. To further
augment energy efficiency author [9] recommended split
monotonic technique. In major SAR-ADC designs area and
switching complexity often confine efficacy [10] and hence
with intend to deal with such limitations Masoodian et al.
[10] developed a logic circuit-based SAR-ADC that
applied lesser number of flip-flops that eventually
eliminated the need of set and reset nodes in flip-flops, thus
reducing power consumption significantly. Tang et al. [11]
exploited the principle of adiabatic charging for energy
efficiency in ADC. Researchers like Ismail et al. [12] have
also made effort to augment SAR-ADC design by focusing
on optimizing SAR algorithms. Authors [12] developed an
energy-efficient capacitance to digital converter (CDC)
interface for capacitive pressure sensors that in conjunction
with a new direct-capacitance-comparison technique
(DCCT) exhibited better performance for SAR
implementation. CDC was found suitable for energy
efficient and stable SAR –ADC design [12].
Um et al. [13] proposed a digital-domain correlation
method for a split- capacitor DAC to be used in differential
type 11- bit SAADC by correlating its nonlinearities or
instabilities occurring due to the unparalleled DAC
capacitance and the two parasitic capacitances merged
3
parallel to each of the bridge capacitor and the LSB bank
of split DAC. Bai et al. [14] developed a 13-b capacitor to
capacitor (C to C) split array multiphase switched capacitor
power-amplifier (SAMP-SCPA) to be used in 65-nm
CMOS for 16-b resolution. Their model enabled extra
states for linearization using digital pre-distortion (DPD)
mechanism. Similarly, Wang et al. [15] developed an
integrated power- saving SAR-ADC for image sensor
applications. Overcoming the limitations of previous works
here two schemes build-in passive correlated double
sampling (CDS) and programmable gain amplifying (PGA)
were applied to assist correlated noise cancellation and
signal amplification without additional OTAs. To further
augment linearization of SAR-ADC, Zhou et al. [16]
applied two distinct schemes, conventional charge-
redistribution and Vcm-based switching. Authors [16]
deployed a new capacitor array architecture to achieve a 6-
bit 550Ms/s energy-efficient SAR with 65nm CMOS that
reduced circuit area significantly than the classical SARs.
Choi et al. [17] in their research focused on the different
stress equalization models to alleviate short term linearity
issues in SA-ADCs, Haenzsche et al. [18] proposed a 14-
bit SA-ADC with differential architecture and self-
calibrating procedure that improves the linearity values of
the ADC. Mitrovic et al. [19] focused on prediction-based
ADC design that estimated input signal likelihood for
ADC. This approach reduced the N number of cycles
needed to convert analog signal to digital signal to only one
and thus facilitating high speed of SA-ADCs either at the
same power consumption or even lower. To meet the
demand of the applications requiring ultra-low power and
ultra-high-speed function Murmann et al. [20] assessed
SAR ADCs with the competing technologies. Considering
the ultra-high-speed ADCs Le et al. [21] developed SAR-
ADC architecture by exploiting monotonic switching
scheme for sampling high frequency differential input
signals. Additionally, a digital background calibration
scheme was also presented to lessen offset errors, gain
mismatches and memory effect in the ultra-high-speed
ADCs. To achieve high
ratehttps://doi.org/10.1109/ISCAS.2012.6271405
communication with minimum complexity Arian et al. [22]
recommended enhanced CMOS technologies, particularly
ADCs that accommodates sampling rates of several tens of
MS/s (contrary to the traditional ADCs). Aditya et al. [23]
emphasized on the need of low power and low voltage
circuits for the micro air vehicles proposed SAR ADC
architecture (LFSR logic) in which the charge distribution-
based DAC has been replaced instead of segmented current
steering DAC approach to reduce area, power consumption
and improve the speed of the design.
Wang et al. [24] proposed high speed low noise
dynamic comparator to reduce power dissipation,
bootstrapped sampling-switch to suppress nonlinear
distortion and novel push-pull buffer to enhance the
conversion accuracy on a 12-b 100MS/s SAR-ADC.
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000 4

Similarly, Rabuske et al. [25] proposed a full-custom QoS Quality of service

controller based on true single-phase clock latch for Figure M2M Machine-to-machine
of Merit (FOM) to gauge the performance of the DNL Differential non-linearity
controllers. Alleviating Signal-to-Noise Distortion Ratio
INL Integral non-linearity
(SNDR) distortion can be vital to augment overall accuracy
VLSI Very large-scale integration
of ADC design for which capacity array design
optimization can be vital [26]. With this motive Fan et al. MCS Merged Capacitor Switching
[26] proposed a capacitive array optimization scheme that CDC Capacitance to digital converter
enhances the Spurious Free Dynamic Range (SFDR) and DCCT Direct-capacitance-comparison technique
SNDR of SAR- ADC to be used for smart sensor C to C Capacitor to capacitor
SAMP- Split array multiphase switched capacitor power-
specifications. Ke et al. [27] proposed a comparator
SCPA amplifier
assisted switching strategy that augmented capacitor array DPD Digital pre-distortion
selection and thereby reduced hardware component and CDS Correlated double sampling
allied switching complexity significantly. A similar effort PGA Programmable gain amplifying
was made by Chen et al. [28] who derived a switching FoM Figure of Merit
technique using SAR-ADC with low input capacitance SFDR Spurious Free Dynamic Range
employing an on-chip resistive ladder to reduce the total
OTA Operational trans-conductance amplifier
input capacitance. The use of predictive capacitor
switching sequence method enhanced energy-efficiency. Ni LFSR Linear feedback shift register
et al. [29] too centered their research on integrating varied Ca Attenuation capacitance
capacitor switching schemes for SAR-ADCs so as to Q1 and Q2 Provide information pertaining to the smallest value of
facilitate no switching energy consumption. The use of capacitors ratio in the adjacent segment
low- power monotonic switching scheme further Cb3 Extra capacitance
augmented overall efficiency. Liu et al. [30] employed a l and m Length of the segments
monotonic capacitor switching scheme to reduce switching Cu Unit capacitance
energy and total capacitances. Unlike these approaches, Ct Total capacitance
Mahdavi et al. [31] applied a new compound R-2R/C Vin Input select signal
structure to achieve high-resolution and speed SA-ADC Vhigh High input signal
design. To reduce the simulation time especially for Vlow Low input signal
medium and high resolution S Brenna et al. [32] developed
CTotal Sum of array capacitance
a an efficient tool for the design of SAR-ADC
S/H Sample to hold circuit
Undeniably, a number of efforts have been made on MSB Most significant bit
augmenting SA-ADC design to achieve power efficiency; VDD Capacitor to supply voltage
however, the high pace up surging demands, especially
Gnd Ground
IoT-ecosystem centric application demands an optimal
solution to meet high speed, low energy, and reliable NMOS N-type metal-oxide-semiconductor
system for which augmenting SA-ADC can be a σINLMAX Standard deviation of integral non-linearity
revitalizing effort. σDNLMAX, Standard deviation of differential non-linearity

Some of the key variables used and the list of σo Standard deviation of unit capacitance
abbreviation is given in Table 1. δi Random variable with zero mean and variance of σ 2o
Table I List of Abbreviation ΔC Relative standard deviation
σ( )
Variables Description C
Cspec Specific capacitance
DAC Digital to analog converter
Kc Pelgrom constant
ADC Analog to digital converter
Sc Size independent coefficient
IoT Internet of thing
ENOB Effective number of bits
SAR-ADC Successive approximation register-analog-to-digital
converter T-S Top plate of the capacitor to the substrate
WSNs Wireless sensor networks T-B Top plate to the bottom plate of the capacitor
DSTS- Dual-split-three-section capacitor array digital to analog B-S Bottom plate of the capacitor to the substrate
CDAC converter
SNDR Signal-to-noise distortion ratio Di Digital input

CMOS Complementary metal oxide semiconductor Cpar Parasitic capacitance connected at the top plate
LLN Low power lossy network Vout Output voltage
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000 5

AR Attenuation ratio the variables l and m are the length of segments and C u is
Q First flip flop the unit capacitance. To make clear the following formula,
Qb Complement flip flop let Ca1/Cu=a; Cd2/Cu=b; Ca2/Cu=c; and Cd3/Cu=d,
l 4l l
(3)
III. DUAL-SPLIT-THREE-SEGMENT CDAC BASED SAR- c=2 , d= −(2¿¿ l+1+1 ,); x=2 −Q 2 ¿
Q2
ADC DESIGN
(2 ¿ ¿ m−Q1 )a (4)
As this research exploits efficacy of split capacitor b= −( 2m−1 ) Q2 ¿
array for DAC design and hence understating capacitor Q1
architecture in CDAC is vital. A snippet of the capacitor And the ratio of the total capacitance to the unit
structure in DAC design is given as follows: capacitance can be determined based on following factors
and referring table II :
Table II: Capacitive distribution method for N-14 bit

A. Capacitor Structures of CDAC: H M L a b-x c d Ct/Cu

7 4 3 2 8 8 49 217
The binary weighted DAC structure with binary 7 5 2 2 18 3 28 205
weigted capacitive DAC can be used for the design 6 5 3 2 24 8 49 185
successive approximation ADC. But total number of There many others not listing
capacitors required and hence the area needed for capacitor
array is used to be large particularly when the resolution of For the resolution of 14 bit, the capacitors can be
CDAC is high. In such cases to accomplish relatively lower split in varied approaches. Some of the significant possible
capacitors, the circuit can be modified from the traditional combinations of H, M, and L segments are depicted in
single split capacitive method to a well-defined and Table II. Considering the resolution of 14 bits, let the
structured three segment capacitive method that eventually capacitors in the segment be H=6, M=5 and L=3, the
can reduce the total capacitance area. Unlike classical split- capacitor ratio be the unit value (i.e., Q1=Q2=1),a=2,(b-
capacitive models, in this research work the capacitor array x)=c= 8 and d =49 . Now, assigning these values, the total
is split into two components in conjunction with three capacitance needed by our proposed Dual-Split-Three
segments H, M and L that signify the resolution of the Segment (DSTS) CDAC method as 185 units C ufrom
DAC. Noticeably, as indicated in Fig. 1, in our proposed capacitor distribution table. Here, it comprises two
model the CDAC comprises two split capacitances Ca 1 and attenuation capacitances C a 1 and C a 2 , where C a 1 =
Ca2.
2Cu ,and C a 2 = 8Cu.. According to equation (1) and (2) the
value of Cb3= 49Cu and Cb2=31Cu. To augment our
Vref proposed CSDS-CDAC model for noise-resiliency the
GND
D1 D9 D8 D7 D4 D3 D2 D1 D0 overall design is crafted as differential [33].
͙ ͙͙
32Cu 3 ͙ 2CU CU Cb1 16Cu 2CU CU Cb2 4Cu 2CU CU Cb3
͙͙ . ͙͙ . Here, the static power has been estimated with the RC
settling time from maximum value of the capacitance in the
H SEGMENT
Ca1 M SEGMENT Ca2 L SEGMENT + capacitor array. In proposed CDAC model, the dynamic
_
power is proportional to the sum of array capacitance
32Cu ͙ ͙ 2CU CU Cb1 ͙ ͙ 2C C Cb2
16Cu U U 4Cu 2CU CU Cb3 C Total of which the bottom-plate is connected to the
͙D͙ 1 . D9
D8
͙͙ . D
D7 4 D3 D2 D1 D0 reference voltage supply (Fig. 3). It enables DSTS-CDAC
Vref
3 structure to augment energy-efficiency. In other words
GND lower the C Total higher the energy-efficiency of the SAR-
Fig. 1. Three segment CDAC Structure ADC.

Q1 and Q2 provide information pertaining to the

smallest value of capacitors ratio in the adjacent segment. B. Switching Cell
Mathematically, As indicated in Fig. 2, the proposed CDAC structures
Cb 3 2l−1 Ca2 l (1) comprises 2 to 1 multiplexer as switching cell, which is
= – 2 −1 designed by using two transmission gates and with a single
Cu Q Cu
inverter. Here, the transmission gate functions as a switch
Cb 2 2m−1 Ca1 l (2) that selects the analog signals [34]. The input select signal
= – 2 −1
Cu Q Cu V ¿ is used to select one of the transmission gates, whose
Noticeably, in equation (1) C b 3 and C b 2 presents the extra key role is to derive the multiplexer switch design so as to
enable optimal pass characteristics. In switching cell if the
grounded capacitance to be applied in circuit architecture,
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000 6

input selection signal is “high” then the input V High will be
available at the output. Similarly, with the “low” input
selection signal, the input V Low would be available at the
output.
Fig. 2. Switching Cell of the proposed DSTS-CDAC design
A snippet of the proposed 14-bit DSTS-CDAC structure is
given as follows:
C. Switching Method
Being a SA assisted ADC design, our proposed
DSTS-CDAC structure employs the switching circuit for
ADC using Successive Approximation Register (SAR)
control logic, as depicted in Fig. 3, which follows the
monotonic switching mechanism as discussed in [35-37]
The schematic of the proposed SA-ADC which consists of
H- segment, M-segment and L- segment. Here H -segment
is considered to be Main -array, M-segment and L-
segment are together considered to be Sub- Array. Also,
DACp (the capacitive array connected to the comparator's
positive input) DACn (the capacitive array connected to the
comparator's negative input) . The switching operation is
as follows which is as depicted in Fig5. In Sampling
phase, the input signal is sampled to all top plate of
capacitor and whereas the bottom plate of the array is
connected to Vref. During 1st cycle of conversion phase,
sampling switches are made OFF. The comparator
performs the comparison and MSB bit D 1 is determined.
This cycle does not consume any switching energy.
According to the comparator output, the largest capacitor
on the higher voltage potential side is switched to ground
and the other one (on the lower side) remains unchanged.
The switching repeats the procedure until the LSB is
decided. The switching procedure is as depicted in Fig 4.

GND
Vref

32C ͙ ͙ 2CU CU Cb1 ͙

͙
16Cu 2CU CU Cb2 4Cu 2CU CU
u ͙͙ . ͙͙ .
Vinp
_
Ca1
Vinn H SEGMENT M SEGMENT Ca2 L + SAR Control
logic
SEGMENT D1 to D13
32C ͙ 16C Cb
͙ 2CU CU Cb1
͙͙ 2CU CU 2 4Cu 2CU CU Cb3
u u
͙͙ . ͙͙ .
Clk
Vref
GND
Fig. 3. DSTS-CDAC Switching Circuit
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000 7

Vref Vref Vref Vref Vref Vref 2

1CVref
Vref Vref Vref Vref Vref Vref
C 2C C 2C C
2C C 2C C 2C C
Vinp

2 CVref2
2C C 2C C 2C C 2C C 2C C 2C C
Vref Vref Vref Vref Vref Vref Vref Vref Vref Vref Vref Vref

Sampling phase
Vref Vref Vref Vref
C 2C C 2C C
2
Vref Vref Vref Vref Vref Vip-Vin= 3/4CVref
2
C 2C C 2C C 1/4CVref
2C C 2C C 2C C
(1) Vref Vref Vref Vref Vref Vref
Vref Vref Vref Vref Vref
2C C 2C C 3/4CVref2 2C C 2C C
Vref Vref Vref Vref Vref Vref C

Vip-Vin= 1/4CVref2
2C C 2C C 2C C
Vref Vref Vref Vref Vref Vref
Vref Vref Vref Vref Vref Vref
C 2C C 2C C

Vip-Vin= 1/4CVref2
Vref Vref Vref Vref Vref Vref 2C C 2C
C 2C C 2C C 3/4CVref2 C 2C
C
Vref Vref Vref Vref Vref
Vref Vref Vref Vref Vref Vref
(2) 2C C 2C C
2C C 2C C 2C C 1/4CVref2 C
Vref Vref Vref Vref Vref Vip-Vin= 3/4CVref2
2C C 2C C 2C C
Vref Vref Vref Vref

Fig 4: Switching proceduure

The linearity of the capacitive DAC predominantly

Fig 5. Energy consumption curve
Fig 5 shows the array energy consumption as function
of the ADC output code for the proposed architecture, by
following the monotonic switching algorithm. Through
periodic sampling and conversion process. this method
gives average Energy consumed as 126.03CVef2
depends on the matching properties of the capacitors and
parasitic capacitances of the unit capacitive elements.
Typically, the nonlinearity of CDAC is quantified in term
of Integral Nonlinearity (INL) and Differential
Nonlinearity (DNL). In this research work, the standard
deviation of the DNL and INL has been estimated. Here, to
characterize linearity characteristics (i.e., DNL and INL) of
the developed DSTS-CDAC, the SAR-ADC was
constructed based on capacitive-array DAC structures,
where each capacitors in the capacitive array was modeled
as the sum of the nominal value of the capacitances and an
error term [35],[37][38]. For the binary weighted
architecture, each capacitor is obtained as follows:
C i=2N −i C u +δ i
(5)

In addition to the energy-efficiency the proposed DSTS σ i2=E [ δ 2i ]

CDAC design has been assessed for linearity analysis to
ensure its suitability for IoT ecosystem. In (5),σ i states the standard deviation of unit capacitance
c u andδ i signifies the random variable with zero mean and
2
variance of σ i . The power consumption of CDAC
D. Linearity analysis of capacitive DAC
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000
structure is directly proportional to the value capacitor
intern size of the unit capacitor in the capacitive array. The
smallest possible value for is determined either by the kT/C
noise requirement [39], the required matching properties of
capacitor, parasitic capacitance or design rules of the
technology. In general, the matching properties of the
capacitors as well as the parasitic capacitances are the
dominant factors for medium-resolution ADCs of the
converter which affect the linearity characteristics.
Therefore, in this paper a comparative assessment of the
linearity of a SAR-ADC has been performed using the
developed DACs structure due to capacitor mismatch and
the standard deviation of the INL and DNL have been
estimated. In this research work, the effect of capacitance
mismatch has been quantified by its standard deviation for
DNL ( σ DNLMAX ) that actually takes place at the middle of
input code. Referring the works in [38][39] for three
segment CDAC structures the standard deviation for DNL
can be estimated as function of relative standard deviation
ΔC
σ( ). Mathematically,
C connected at the top plate and C Tot =2 C u. For our
N (6)
3 ΔC
σ DNLMAX =2 σ ( ) expression has been obtained for 14 bit with H=6, M=5 and
C l=3 using (9).
In above expression (6), the relative value of
ΔC
σ( ) has been obtained using (7).
C ∑
(7)
k 2c c spec 2 2
σ
ΔC
( )C
=
√ Cu
+ sc x
In {7), c spec refers the specific capacitance, C u is the
unit capacitance, K c states pelgrom constant and Sc states
the size independent coefficient. The value of capacitor is
selected in such manner that there can be minimum value
2
of k c Cspec , and the size of unit capacitance C u. It is
achieved by maintaining σ DNLMAX <0.5 by neglecting the
size-independent term for medium resolution. Though,
DNL and INL do characterize the best metrics for
assessing linearity behavior of CDAC model, the effective
number of bits (ENOB) can also be applied as an indicator
of system performance. Primarily, ENOB relies on the
distribution of the INL along the output code. In addition to
the above stated assesses, the linearity characterization of
the CDAC structures under parasitic capacitance effects
has also been examined.
E. Capacitive Parasitic Effect
In this paper, the parasitic effect of capacitances in
CDAC structure has been assessed by considering
capacitance effect of the top-plate of the designed array to
the substrate, from the top-plate to the bottom-plate of all
unit capacitor, and bottom plate to substrate of each
capacitive bank of the DAC. Typically, the parasitic
capacitances characterize the one connected from the top
8
plate of the capacitor to the substrate (T-S), from the top
plate to the bottom plate of the capacitor (T-B) and the
bottom plate of the capacitor to the substrate (B-S).
However, such type of parasitic capacitance would not
affect linearity behavior of capacitive DAC significantly
because the bottom-plate of the array capacitances is
connected to the ground or supply-voltage. Usually, the
parasitic capacitance is considered to be responsible for
degrading the linearity performance of the three segment
CDAC converter. It can be examined by deriving the
voltage at the output node of the DAC. For the
conventional CDAC the output voltage corresponding to a
given digital input can be obtained by (8) [40].
N (8)
∑ Di .C i
Vout = i=1
C Tot + C Par
In equation (8), Di presents the digital input word for
i=1,2,3 … N , C Par refers the parasitic capacitance
N
proposed DSTS CDAC structures with three segments this
N i
[ ]
2
−1
Di . C
(9)i
∑ Di . C i N
i= −1
Vout= i=1
Ctot+C Par , H
+ AR . 2
Ctot +C ParM +C parL
In equation (9), C i states the capacitance associated with i th
V DD
bit, and AR states the attenuation ratio obtained using (10).
Cu
AR= (10)
C H +C parH
The above expression states that only the parasitic of
C ParM and C parLinfluence the linearity which are
responsible of a deterministic pattern of the DNL, and
hence of the INL. In the proposed research, the transistor
level simulation has been exhibited on 14-bit DSTS-CDAC
with unit capacitance of 100 fF and accordingly the
linearity variations have been retrieved. This study has
revealed that the pattern goes to high at every 128 for 14
bit resolution and the highest value of pattern is obtained at
0.4LSB which is within the range of +0.5LSB/-0.5LSB.
Thus, in this study the value of ENOB is obtained as
11bits. In final state of the characterization, the parasitic
between top- and bottom plate of the H –array capacitors
has been assessed to have its impact on limiting the
linearity performance of the proposed DSTS-CDAC
structure. It is significant to assess this behavior as due to
the routing paths for connecting the capacitor plates there
could be certain parasitic capacitance impacting linearity of
the proposed DSTS-CDAC structure. Usually, such
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000 9

parasitic capacitors affect the unit capacitance C u that inversion region. The equivalent input noise of the
eventually affects major performance parameters including comparator [40] approximately equal to
linearity as well as energy consumption. In the three- KT 8 KT
segment capacitive array model, the parasitic capacitance
affecting C i may impose an error of ΔC i on the output
Vn ,(rms)=
√ √ Cp
.
qV T
(11)

voltage given in (11). VT being the threshold voltage of the second stage input
transistors. In order to make this noise negligible with
N i
2 ×0.5

[ ]
−1
2
∑ Di . ΔC i(10) respect to the LSB for the VDD =0.5 V ( LSB=
∑ D i . ΔC i i=
N
−1
2N
V DD ,= 61µv),the parasitic capacitance has to be larger than
i=1 2
Vout= + AR .
C Par , H C ParM +C parL approximately 3 fF.

In above equation C Par , H ,C ParM ∧C parL are the overall

Vdd
capacitances of the DAC structure. Considering this fact, in
this research the effect of parasitic capacitances has been Vbias M1
assessed, where it exhibits affirmative results ensuring Vinn
optimal performance with minimum power exhaustion and M2 M3 Vinp M10 M11
better stability.
A graphic user interface MATLAB environment
supports the implemented models[ that allow to simulate M4 M5 M12 M13
both mismatch and parasitic effects on linearity. This out2
allows to run simulations in order to accurately evaluate M17
out1
M9
the DNL and INL taking consideration of capacitor M8 M6 M7 M14 M16 M15

mismatch and parasitic effects. Gnd

F. The Comparator
In DSTS-CDAC structure the comparator circuit
compares the output of sample hold circuit with the DAC
output generated by segmented capacitive array method. In
this method, the output of the comparator is fed to SAR
logic as indicated in Fig 6. Figure (Fig. 6) depicts the
dynamic latched structure of the comparator with two
phases [38][41][42]. In our proposed model, in initial phase
it consists of pre-amplifier with NMOS differential pair
which is vital for adopting the monotonic switching
scheme. In later phase, for same bias current and input
trans- conductance, the NMOS pair offers the lower input
capacitance with a reduced effect on the converter
linearity.
For this comparator before the comparison
process begins, the first stage output nodes are pre-charged
low by a positive on Vbias signal. The pre-charging phase
sops at falling edge and starts amplify the differential input
signal and also current starts to flowing into the differential
pair charging the parasitic capacitances Cp at the drain
nodes of the 1st stage. The voltage on the capacitors
increases depending on the input signal, Vinp–Vinn. As the
first stage output voltages reach the threshold voltage of
the second stage input transistors, the latch starts to amplify
the signal. According to simulation, the first stage
differential gain is about 5, high enough to make the noise
of the second stage negligible. Thus, the equivalent input
noise of the comparator is mainly determined by the input
differential pair and its transistor working in weak
Fig 6. Comparator
G. The SAR Logic
In the proposed DSTS-CDAC structure the SAR
dynamic logic generates necessary signal to control the
operation of the CDAC and allied functional comparator.
Applying dynamic logic, the number of transistors required
get reduced significantly that eventually makes proposed
model energy or power-efficient. The SAR logic as
indicated in Fig 7 comprises linear feedback shift register
that enables ADC function based on the binary search
method. Here, the SAR logic has been formed using DFF
that embodies register circuit as additional component.
Reset controls the flip-flop 1’s set signal and reset signal of
other flip-flops. Additionally, the code registers too are
controlled by this reset value. Functionally, the reset value
is initialized with zero. The output of first flip flop Q is ‘1’
and its complement Qb is ‘0’. Here, the complement output
Qb manages the code register flip flop 1’s set value that
enables the code register flip flop 1’s output to becomes
‘1’. In the proposed SAR-ADC structure, the sequence
registers remain in reset state and hence except CF1 all the
code registers input are set to “1” that makes the output of
the code registers at logic zero. Consequently, the sequence
remains in such manner that the MSB is logic ‘1’ and all
the other bits are ‘0’. Thus, applying DAC the equivalent
analog value can be obtained for further processes.
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000
Fig 7. Successive Approximation Register (SAR) Logic
IV. RESULTS AND DISCUSSIONS
Considering the significance of a robust DAC design
for energy-efficient and stable SAR-ADC structure in this
paper a highly robust Dual-Split-Three Segment Capacitive
array DAC model (DSTS-CDAC) has been developed.
Unlike classical capacitive DAC models DSTS-CDAC
architecture enables two split with three segments that not
only reduces energy exhaustion but also memory
consumption. The power consumption of SAR-ADC has
been assessed as a function of sampling rate, varying from
100-kSps to 1MSps and for the two different supply
voltages (1V and 1.5v). The energy consumption by our
proposed DSTS-CDAC model is depicted in Fig. 8. To
perform simulation the sampling rate is selected as 1-
MSps, the input supply of SAR - ADC was selected at
1.5V. In the proposed three-segment capacitive DAC
multiplexer has been applied as the selecting switch that
eventually consumes low power (12µW). And comparator
consumes the power of 10.47µW. The overall power
consumption of successive approximation ADC was
obtained as 90.12μW. On the other hand, the SAR–ADC
model with conventional CDAC structure consumes the
power of 2.47mW at sampling frequency of 1MSps.
Power Consumption Curve
100
power consumption (µW)
90
80
70
60
50
40
30
20
10
0
100 200 300 400 500 600 700 800 900 1000
sampling rate (ksPS)
Fig 8. Power consumption curve
10
Table III exhibits the power consumption of
conventional SAR-ADC and ADC with thee segment
CDAC structure.
Table III Power Consumption Summary
Blocks Power consumed
Segmented capacitive DAC 12µW
Conventional CDAC structure 2.3mW
Segmented DAC SAR_ADC 90.12 µW
Conventional CDAC SAR_ADC 2.47 mW
The static performance of the proposed SAR-
ADC is depicted in Figures (Fig. 9 and Fig. 10), which
reports both DNL and INL in LSB as functions of the
output level code of converter. Here the DNL shows
periodic peaks at every 128 codes for 14-bit resolution.
The measured value of the DNL at 1Msps is +0.4LSB/-
0.2LSB and INL of 1LSB /-1LSB.These DNL/INL
performance are mainly due to the mismatch value of
capacitances present capacitive array. The standard
deviation of DNL, INL versus output ode of converter as
shown in the results (Fig. 11 and Fig. 12) where the
standard deviation goes to the maximum value of
+0.45LSB As for as dynamic performance is concerned, at
a sampling rate of 1MSps with power supply voltage of
1.5v the ADC achieves SNDR of 67.9dB and ENOB of 11
bits. The performance of the implemented SAR-ADC
converter are summarized in Table IV and Compared with
recent state-of-the art SAR -ADCs. The proposed converter
shows that, the parameters derived are in-line with the
other medium-resolution converters. However, this is the
only ADC converter that relies on an optimized array in-
terms of unit capacitance to mitigate the effect of the
capacitive mismatch and parasitic. Finally, the area factor
is analyzed based on the number of unit capacitors required
he by capacitive array of CDAC.
Fig 13 shows the FFT Spectrum at sampling
frequency 200KSps with input sinewave for a frequency
of 96KHz.
Vdd=1.5v
Vdd=1.0v
Fig 9. Simulated plot of DNL
 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000 11

Parameter [41] [43] [44] [45] Proposed

DSTS-
CDAC
Power supply 1.8 1.5 1.2 1.2 1.5
voltage(v)
Resolution (bit) 14 14 14 14 14
Sampling 0.1 40 80 0072 1
rate(MSps)
Technology - 65 130 130 180
Power Cons. by 4.29 66000 3100 130 90.15
SAR_ADC(µw
)
Peak - 13.5 11.6 13.5 11
ENOB(bits)
Fig 10. Simulated plot of INL Peak - 83 71.2 83 67.9
SNDR(dB)
Capacitors - - MOM MiM PiP

V. CONCLUSION
Taking into consideration of the need of a robust data
acquisition and communication system for the advanced
communication purposes such as IoT ecosystem, in this
paper a novel Dual-Split-Three-Section (DSTS) capacitor
array DAC (DSTS-CDAC) was proposed to augment
classical SAR-ADC design. The proposed DSTS-CDAC
model focused on enabling 14-bit SAR-ADC function
while retaining optimal Signal-to-Noise Destruction Ratio
Fig 11 Standard deviation of DNL
(SNDR) of the ADC, A graphic user interface MATLAB
environment supports the implemented models that allow
to simulate both mismatch and parasitic effects on linearity
(DNL and INL). The energy consumption performance by
the switching capacitors in applied CDAC model with
three segment capacitive method revealed that the
proposed DSTS-CDAC model exhibits 190 times reduced
power consumption than the classical switching schemes.
Unlike classical SAR-ADC design, DSTS-CDAC model
that employs dual (i.e., two) split capacitor array with
multiplex switching conserves more than 28% total
capacitance area and hence makes proposed system
memory efficient. Since the proposed design was made
Fig 12. Standard deviation of INL completely differential and hence reduced the noise
parameter SNDR significantly. The proposed CDAC
model can be of vital significance for noise-resilient
sampling of high frequency differential input signals.
However, the simulation results revealed that the proposed
DSTS-CDAC model exhibits better stability or linearity
under as compared to the classical DAC structures. Thus,
the overall results obtained and allied novelties affirm its
suitability for real time applications where high rate data
processing such as acquisition, transmissions etc are
required with minimum possible signal distortion and non-
linearity.

Acknowledgments:
Fig 13: FFT Spectrum at 200Ksps Sampling frequency

Table IV: Performance summary of segmented SAR ADC

 ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000
The authors are very grateful to Principal and
management of KVG college of Engineering Sullia. for
kindly support and for providing appropriate guidance.
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Savitha.M has received the
B.E.degree in electrical and
electronics engineering from
Mangalore University, India
in1995 and the MTech. degree in
industrial electronics from
National institute of technology
Mangalore in 2003
. Presently she is pursuing the Ph.D. Degree in
School of Electronics and communication REVA
University Bangalore .Her research work focuses on design
and analysis of mixed mode circuits. Her area of interest is
analog and digital VLSI Design and mixed Mode circuits.
R. Venkat Siva Reddy has received the
BE degree in Electronics and
Communication from Gulbarga
University and the MTech degree in
Power Electronics from Gulbarga
University. He received the Ph.D. degree
from the Department of Electronics Sri
Krishnadevaraya University, Anantapur
Presently and he professor in School of
Electronics and Communication Reva University.
Bangalore. His research interest include power electronics
and VLSI design circuit. He is professional member of
IEEE and he worked as treasurer for IEEE for 2013-14. He
has several fellowships and he is recognised as Outstanding
Volunteer IEEE Bangalore Section year 2012
ARAB ECONOMIC AND BUSINESS JOURNAL 00 (2014) 000–000 14