L01 Introduction To VLSI

Introduction to VLSI Design
July 25, 2007 Prof. Indranil Sen Gupta, IIT Kharagpur 1

VLSI Design Cycle
• Large number of
System
devices Specifications
• Optimization
requirements for
Manual Automation
high performance
• Time-to-market
competition
• Cost Chip

Typical VLSI Design Flow
• Design entry
• Logic synthesis
• System partitioning
• Floorplanning
• Placement
• Routing
• Fabrication / Prototyping

Design and Fabrication of VLSI Devices
• VLSI chips are typically based on MOS
technology.
• The basic problem is how to fabricate
these devices on the silicon floor.
• The process of fabrication makes use of
masks.
– A mask is a specification of geometric shapes
that need to be created on a certain layer.
– Masks are used to create specific patterns of
each material in a sequential manner and
create a complex pattern of several layers.

Details of Fabrication Processes
• Crystal growth and wafer preparation
• Epitaxy
• Dielectric and polysilicon film deposition
• Oxidation
• Diffusion
• Ion implantation
• Lithography
• Etching
• Packaging

Issues Related to Fabrication Processes
• Process scaling allows:
– High level of integration
– Better yields (for a constant die size)
– Lower costs
– Possibility of larger die sizes (for a constant
yield)
• Several problems and issues crop up:
– Parasitic effects
¾ Stray capacitances
– Interconnect-related issues
¾ Interconnect delay
¾ Noise and crosstalk
– Power dissipation and yield

Parasitic Effects
• Circuit elements lie in close proximity.
– Inter-component capacitances play a major
role in the performance of these circuits.
¾ Stray capacitance
¾ Capacitance between signal paths and ground
¾ Inherent capacitance of a MOS transistor
• Interconnect capacitances.
– Between wires across layers.
¾ More significant.
¾ Can be reduced by connecting wires in adjacent
layers perpendicular to each other.
– Between wires within the same layer.
¾ Can be reduced by increasing the wire spacing and
using power lines shielding.

Interconnect Delay
• Two types of delays in a circuit:
– Gate delay
– Interconnect delay
• Both types of delay depend on parameters
as:
¾ Width and length of the poly
¾ Thickness of oxide
¾ Width and length of metal lines
• The process of extracting these parameters
is called extraction.
¾ Using a tool called RC-extractor.

Noise and Crosstalk
• Reduction in feature sizes and signal
magnitudes.
– Circuits become more susceptible to external
disturbances (noise).
• Noise mainly arises out of resistive and
capacitive coupling.
– Smaller feature sizes result in reduced node
capacitances (i.e. less circuit delay).
– These nodes also become more vulnerable to
external noise, especially they are dynamically
charged.

Contd.
• Coupling between neighboring circuits

and interconnections is the most
prevalent form of internal noise.
• Noise generated by off-chip drivers also
pose a major problem.
• Noise margin is closely related to input-
output voltage characteristics.
LNM = max (VIL) – max (VOL)
HNM = min (VOH) – min (VIH)

Contd.
• Crosstalk
– A particular form of noise.
– Result of mutual capacitance and inductance
between neighboring lines.
– Amount of coupling depends on:
¾ Closeness of the lines.
¾ How far they are from the ground plane.
¾ The distance they run close to each other.
• As a result of crosstalk, propagation delay
increases and logic faults occur.

Power Dissipation
• Heat is generated in a chip.
– Primary heat sources are the individual
transistors.
– Has to be removed by some type of heat
transfer.
– For high levels of integration, heat removal
becomes the dominant design factor.
• If all the generated heat is not removed,
– Chip temperature may rise resulting in thermal
breakdown.
– Hotspots may appear.

Contd.
• Power dissipation has become a topic of
intense research and development.
– Due to the proliferation of lap-top computers
and mobile devices.
– Development of low-power circuits have
become an important research area.
¾ Typically, 25-35% power in a microprocessor is
dissipated in the clock circuitry.
¾ Low power dissipation can be achieved by literally
switching-off blocks that are not needed for
computation in any particular step.

Future of Fabrication Process
• Fabrication process is very costly to
develop and deploy.
• Semiconductor Industry Association (SIA)
published the National Technology
Roadmap for semiconductors in 1977.
– Provides a vision for the future.
– Several manufacturers have released
roadmaps, which are far more aggressive than
the SIA roadmap.

SIA Roadmap
Feature size (micron) 0.25 0.18 0.13 0.10

Time frame 1997 1999 2003 2006
Transistors 3.7 6.2 18 39
(millions/sq cm)
Frequency (MHz) >500 >750 >1100 >1500
Chip size (sq mm) 300 360 430 520

Wiring levels 6 6-7 7 7-8
Package pins 512 512 768 768

n-channel Transistor

n-channel Transistor Operation

n-channel Transistor Layout

p-channel MOS Transistor

Fabrication Layers

MOS Transistor Behavior

Summary of VLSI Layers

VLSI Fabrication

Silicon Wafer

General Design Rules

Types of Fabrication Errors

Width/Spacing Rules (MOSIS)

Poly-Diffusion Interaction

Contacts

Contact Spacing

M2 Contact (Via)

CMOS Layout Example

Stick Diagrams

Static CMOS Inverter

Static CMOS NAND Gate

Static CMOS NOR Gate

Static CMOS Design :: General Rule

Simple Static CMOS Design Example

Static CMOS Design Example Layout

More Difficult Static CMOS Design Example

Layout of Difficult CMOS Example

Layout Styles

Hierarchical Layout

Contd.

Standard Cells

VLSI Design Styles

The Alternatives
• Programmable Devices
– Programmable Logic Device (PLD)
– Field Programmable Gate Array (FPGA)
– Gate Array
• Standard Cell (Semi-Custom Design)
• Full-Custom Design

Field Programmable Gate Array
(FPGA)

Introduction
• User / Field Programmability.
• Array of logic cells connected via routing
channels.
• Different types of cells:
– Special I/O cells.
– Logic cells.
¾ Mainly lookup tables (LUT) with associated registers.
• Interconnection between cells:
– Using SRAM based switches.
– Using antifuse elements.

Xilinx XC4000 Architecture
CLB CLB Vcc

Slew Passive
Rate Pull-Up,
Control Pull-Down
Switch
Matrix
D Q
Output Pad
Buffer
Input
CLB CLB Buffer
Q D Delay
Programmable
Interconnect I/O Blocks (IOBs)
C1 C2 C3 C4
H1 DIN S/R EC
S/R
Control
G4 DIN
G3 G F'
SD
G2 Func. G' D Q
Gen. H'
G1
EC
RD
1
H G'
Y
Func. H'
S/R
F4 Gen. Control
F3 F DIN
Func. SD
F2 Gen.
F'
G' D Q
F1 H'
EC
RD
1
H'
F'
X
K
Configurable
Logic Blocks (CLBs)
XC4000E Configurable Logic Blocks
C1 C2 C3 C4
H1 DIN S/R EC
S/R
Control
G4 DIN
SD
G3 G F'
G' D Q YQ
G2 Func. H'
Gen.
G1 EC
RD
1
H G'
H'
Y
Func. S/R
Gen. Control
F4
F3 F DIN
SD
Func. F'
D Q XQ
F2 Gen. G'
H'
F1
EC
RD
1
H'
X
F'

CLB Functionalities
• Two 4-input function generators
– Implemented using Lookup Tables using 16x1
RAM.
– Can also implement 16x1 memory.
• Two Registers
– Each can be configured as flip-flop or latch.
– Independent clock polarity.
– Synchronous and asynchronous Set / Reset.

Look Up Tables
• Combinatorial Logic is stored in 16x1 SRAM Look Up Tables
(LUTs) in a CLB
Look Up Table
• Example:
4-bit address
Combinatorial Logic
A B C D Z
A
B 0 0 0 0 0
Z 0 0 0 1 0
C 0 0 1 0 0
D
0 0 1 1 1
0 1 0 0 1
Capacity is limited by number 0 1 0 1 1
of inputs, not complexity . . .
Choose to use each function 1 1 0 0 0
generator as 4 input logic (LUT) 1 1 0 1 0
or as high speed sync.dual port 1 1 1 0 0
RAM 1 1 1 1 1

XC4000X I/O Block Diagram

Xilinx FPGA Routing
1) Fast Direct Interconnect - CLB to CLB

2) General Purpose Interconnect - Uses switch matrix
CLB
CLB CLB
CLB
Switch Switch
Matrix Matrix
CLB
CLB CLB
CLB

FPGA Design Flow
• Design Entry
– In schematic, VHDL, or Verilog.
• Implementation
– Placement & Routing
– Bitstream generation
– Analyze timing, view layout, simulation, etc.
• Download
– Directly to Xilinx hardware devices with
unlimited reconfigurations.

Gate Array

Introduction
• In view of the fast prototyping capability,
the gate array (GA) comes after the FPGA.
– Design implementation of
¾ FPGA chip is done with user programming,
¾ Gate array is done with metal mask design and
processing.

• Gate array implementation requires a
two-step manufacturing process:
1. The first phase, which is based on generic
(standard) masks, results in an array of
uncommitted transistors on each GA chip.
2. These uncommitted chips can be customized
later, which is completed by defining the
metal interconnects between the transistors
of the array.

Channeled vs. Channel-less (SoG) Approaches

• The GA chip utilization factor is higher
than that of FPGA.
– The used chip area divided by the total chip
area.
• Chip speed is also higher.
– More customized design can be achieved with
metal mask designs.
• Current gate array chips can implement as
many as millions of logic gates.

Standard Cell Based Design

Introduction
• One of the most prevalent custom design styles.
– Also called semi-custom design style.
– Requires developing full custom mask set.
• Basic idea:
– All of the commonly used logic cells are developed,
characterized, and stored in a standard cell library.
– A typical library may contain a few hundred cells.
¾ Inverters, NAND gates, NOR gates, complex AOI, OAI
gates, D-latches, and flip-flops.

Characteristic of the Cells
• Each cell is designed with a fixed height.
– To enable automated placement of the cells, and routing
of inter-cell connections.
– A number of cells can be abutted side-by-side to form
rows.
• The power and ground rails typically run parallel
to upper and lower boundaries of cell.
– Neighboring cells share a common power and ground
bus.
• The input and output pins are located on the
upper and lower boundaries of the cell.

Standard Cells

Standard Cell Layout

Floorplan for Standard Cell Design
• Inside the I/O frame which is reserved for I/O
cells, the chip area contains rows or columns of
standard cells.
– Between cell rows are channels for dedicated inter-cell
routing.
– Over-the-cell routing is also possible.
• The physical design and layout of logic cells
ensure that
– When placed into rows, their heights match.
– Neighboring cells can be abutted side-by-side, which
provides natural connections for power and ground
lines in each row.

Full Custom Design

Introduction
• The standard-cells based design is often called
semi custom design.
– The cells are pre-designed for general use and the same
cells are utilized in many different chip designs.
• In the full custom design, the entire mask design
is done anew without use of any library.
– The development cost of such a design style is
prohibitively high.
– The concept of design reuse is becoming popular to
reduce design cycle time and cost.

• In real full-custom layout the geometry,
orientation and placement of every transistor is
done individually by the designer.
– Design productivity is usually very low.
¾ Typically 10 to 20 transistors per day, per designer.
• In digital CMOS VLSI, full-custom design is rarely
used due to the high labor cost.
– Exceptions to this include the design of high-volume
products such as memory chips, high-performance
microprocessors and FPGA masters.

Comparison Among Various Design Styles
Design Style
FPGA Gate Standard Full
array cell custom
Cell size Fixed Fixed Fixed Variable
height
Cell type Program Fixed Variable Variable
mable
Cell placement Fixed Fixed In row Variable
Interconnect Program Variable Variable Variable

mable
Design time Very fast Fast Medium Slow

Various CMOS Structures

Transmission Gate

Dynamic Register

Semi-static Storage

Dynamic Shift Register

CMOS Clocked Logic

CMOS Clocked Logic Design

A D Flip-flop

CMOS Inverter Delay

Estimating R and C

Pseudo-NMOS Logic

Domino CMOS

Domino CMOS Example

Charge Sharing

Evaluation of Domino CMOS gates

Pass Transistor Logic

Delay Through Pass Transistor Chains

Full Adder
A B
Cin Full Cout

adder
Sum

Express Sum and Carry in terms of
P,G,D
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A ⊕ B
Delete = A B
Can also derive expressions for S and Co based on D

and P

The Ripple Carry Adder
A0 B0 A1 B1 A2 B2 A3 B3
Ci,0 Co,0 C o,1 Co,2 Co,3

FA FA FA FA
(= C i,1)
S0 S1 S2 S3
Worst case delay linear with the number of bits

td = O(N)
t adder ≈ ( N – 1 )t carry + tsum
Goal: Make the fastest possible carry path circuit

CMOS Full Adder
VDD
VDD
Ci A B
A B
A
B
Ci B VDD
A
X
Ci
Ci A S
Ci
A B B VDD
A B Ci A
Co B
28 Transistors

Inversion Property
A B A B
Ci FA Co Ci FA Co
S S

Minimize Critical Path by Reducing Inverting
Stages
Even Cell Odd Cell
A1 B1 A3 B3
A0 B0 A2 B2
Ci,0 C o,0 Co,1 C o,2 C o,3

FA’ FA’ FA’ FA’
S0 S2
S1 S3
Exploit Inversion Property
Note: need 2 different types of cells

nMOS Pass Transistor Logic
B B A CC A A
A
B
A
B
C A
C
A
Sum Sum Cout Cout

Transistor count (CPL) : 28

Carry Bypass Adder
P0 G1 P0 G1 P2 G2 P3 G3
Ci,0 C o,0 C o,1 Co,2 Co,3

FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
Multiplexer
FA FA FA FA
Co,3
Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C0, else “kill” or “generate”.

Manchester Carry Chain
P0 P1 P2 P3 BP
Ci,0 Co,3
G0 G1 G2 G3
BP
Carry Bypass Adder (contd.)
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
Setup Setup Setup Setup
Carry Carry Carry Carry

C i,0 Propagation Propagation Propagation Propagation
Sum Sum Sum Sum
The Binary Shifter
Right nop Left
Ai Bi
Ai-1 Bi-1
Bit-Slice i
...
The Barrel Shifter
A3
B3
Sh1
A2
B2
Sh2 : Data Wire

A1
B1 : Control Wire
Sh3
A0
B0
Sh0 Sh1 Sh2 Sh3
Contd.
A3
A2
A1
A0
Sh0 Sh 1 S h2 Sh3
B uffer
Logarithmic Shifter
Sh1 Sh1 Sh2 Sh2 Sh4 Sh4
A3 B3
A2 B2
A1 B1
A0 B0
Contd.
Summary
• An overview of the process of VLSI design
has been presented.
• Various nMOS/CMOS design styles have
been discussed.
• As case studies, MOS realizations of
typical arithmetic circuits and shifters are
shown.

L01 Introduction To VLSI

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L01 Introduction To VLSI

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Introduction to VLSI Design

July 25, 2007 Prof. Indranil Sen Gupta, IIT Kharagpur 1

July 25, 2007 Prof. Indranil Sen Gupta, IIT Kharagpur 2

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• Coupling between neighboring circuits

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Feature size (micron) 0.25 0.18 0.13 0.10

Chip size (sq mm) 300 360 430 520

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CLB CLB Vcc

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1) Fast Direct Interconnect - CLB to CLB

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