United States Patent [191 [11] Patent Number: 5,053,651

Frerking et a1. [45] Date of Patent: Oct. 1, 1991 g

[54] DEGLITCHED DIGITAL MIXER CIRCUIT 4,775,840 10/1988 Ohmori et a1. .................... .. 328/111
[75] Inventors: Marvin E. Frerking, Cedar Rapids; FOREIGN PATENT DOCUMENTS
Roy W. Berquist, Toddville, both of 58452928 4/1983 Japan _
1°“ 0189317 9/1985 Japan ................................. .. 307/443
[73] Assignee: Rockwell International Corporation, Prima’y Examiner_-rimothy P_ Callahan
. El Segundo, Cahf- Attorney,v Agent, or Firm-—John C. McFarren; John J.
[21] APPL Na; 576,134 Horn; H. Fredrick Hamann
[22] - Filed: Aug. 28, 1990 [57] ABSTRACT
. .
A di 3 ital mixer employs a plurality of flip-?ops to mix
Related US. Application Data two digital input signals and provide a beat frequency
[63] Continuation of SCI. No. 264,429, om. 31, 1988, aban- °“tP"t- The ?rst in?“ Sign! is Pr°"1_d¢d as a °1°°k
doned, signal to a ?rst D ?ip-?op and to a third JK ?ip-?op.
5 The second input signal is provided as a clock signal to
[51] Int. C1. ...................... .. H03B 19/00; G066 7/00 a second D ?ip_?op_ The inverted Output of the ?rst
[52] US. Cl. .................................. .. 307/529; 307/443; ?ip_?op is provided as a clock input to a fourth JK
_ 307/2721; 307/2471; 328/111; 328/158 flip-flop. The non-inverted and inverted outputs of the
[58] Field of Search ............. .. 328/133, 134, 111, 158, second ?ip_?op are connected, respectively, to the J
328/160’ 162' 165; 307/529’ 491’ 247'1’ 443’ and K inputs of the third ?ip-?op. The non-inverted
2721' 272'3' 234 outputs of the second and third ?ip-?ops are input to a
[56] References Cited ?rst AND gate, the output of which connects to the J
input of the fourth ?ip-?op. Likewise, the inverted
U‘s' PATENT DOCUMENTS outputs of the second and third ?ip-?ops are input to a
3,610,954 10/1971 Treadway ......................... .. 307/232 second AND gate, the output of which connects to the
3,906,382 9/1975 Miyamoto et a1. 328/134 K input of the fourth flip-?op. The non-inverted output
.4. . . .. .. . . .. . - . . .. of the fourth provides a beat frequency is

, ,
:lranaka ettall- ~
agnowe a. .... ._
one-half the difference frequency of the two input sig
. ._ . .. .

4,399,412 8/1983 Rinaldi . . . . . , . . . . . .. 307/234 n'iils'h'rhe thug g‘p M91.“ ‘h? d‘gétali rglxert. prevents
4,467,285 8/1984 Rinaldi . . . . . . . . . . . . .. 307/234 8 “c 65 am“ ‘ e “ansmc’n “me o t 8. eat requency
4,468,784 8/1984 Jagnow et a1_ 375/1 output even for very low beat frequencies.
4,525,635 6/1985 Gillberg ................... .. 307/234
4,739,278 4/1988 Des Brisay, Jr. et a1. ........ .. 328/133 8 Claims, 1 Drawing Sheet

10 \
FF] 12 FF4
S4 10 0i - J 04 -——¢

0] 41 C
D K
14

52 P, 0 02 H J 03
'—o C

D 02 K Q3
"2 FF3
 5,053,651
1 2
BRIEF DESCRIPTION OF THE DRAWINGS
DEGLITCHED DIGITAL MIXER CIRCUIT
For a more complete understanding of the present
This application is a continuation of application Ser. invention and for further advantages thereof, reference
No. 07/264,429 filed Oct. 3l, 1988, now abandoned. 5 is made to the following Description of the Preferred
Embodiment taken in conjunction with the accompany
TECHNICAL FIELD ing Drawings, in which: FIG. 1 is a functional block
The present invention relates to electrical circuits diagram of the digital mixer circuit of the present inven
that ‘mix input signals and, in particular, to a digital tion, and FIG. 2 is a waveform timing diagram of the
mixer designed to prevent spurious indications in the digital mixer of the present invention.
beat frequency output. DESCRIPTION OF THE PREFERRED
EMBODIMENT
BACKGROUND OF THE INVENTION
In electrical circuits that use ?ip-?ops as digital mix FIG. 1 is a functional block diagram of a digital mixer
ers, spurious transitions or spikes, generally referred to
circuit 10 of the present invention. Signals S1 and S; are
provided as inputs to digital mixer 10. Signal 5; is con
as glitches, may be generated. In conventional circuits nected to the clock input of a D flip-?op FF1 and to the
using a flip-flop as a digital mixer, glitches in the output clock input of a JK ?ip-?op FF3. An inverted output
signal are likely to occur when the input signals drift Q1 of FF! is connected to the clock input of a J K ?ip
through an in-phase condition. When the input signals ?op FF4 and is fed back to the D input of FF; to halve
change state simultaneously, the mixer ?ip-?op may or the frequency of input signal S1. The second input sig
may not be properly clocked and may assume the 0 or nal S2 is connected to the clock input of D ?ip-flop FFZ.
1 states randomly for several successive clocks. As a A non-inverted output Q2 of FF; is connected to the J
result, the beat frequency output may include undesir input of FF3. The inverted output Q2 of FF; is con
able spurious transitions. 25 nected to the K input of FF3 and is fed back to the D
Thus, there is a need for a simple digital mixer that input of FF; to halve the frequency of input signal 8;.
employs flip-flops and prevents the generation of glit The non-inverted outputs Q2 and Q3 of FF1 and FF3,
ches in the beat frequency output even for very low respectively, are provided as inputs to an AND gate 12,
beat frequencies. the output of which is connected to the_J input of FF4.
30 Likewise, the inverted outputs Q2 and Q3 are provided
SUMMARY OF THE INVENTION to an AND gate 14, the output of which is connected to
The present invention comprises four flip-?ops con the K input of FF4. A non-inverted output Q4 of FF4
nected in a circuit that performs the function of a digital provides a beat frequency output of digital mixer 10.‘
mixer. The beat frequency output of the digital mixer is Referring to the timing diagram of FIG. 2, various
one-half the difference frequency between two input 35 waveforms of digital mixer 10 are illustrated. As shown
signals. in FIG. 2, Q; is one-half the frequency of input signal 5;.
The digital mixer of the present invention receives Likewise, Q; is one-half the frequency of input signal 5;.
two digital input signals S1 and S; that generally have Q3 is output by FF3, which is clocked by the negative
independent and unrelated frequencies. S1 is input as a edge of input signal S1. FF3 could be clocked equally
clock signal to a ?rst D ?ip-?op and to a third I K flip 40 well by the negative edge of input signal 82. Because
flop. S2 is input as a clock signal to a second D ?ip-?op. Q1 is one-half the frequency of input 51, the transitions
The inverted output of the ?rst flip-?op is provided as of Q3 lag those of Q; by one-fourth period. As shown in
a clock input to a fourth J K ?ip-?op. The non-inverted FIG. 1, Q2 and Q3 are input to AND gate 12, which
and inverted outputs of the second flip-flop are con connects to input I of FF4. Likewise, Q2 and Q3 are
nected, respectively, to the J and K inputs of the third provided to AND gate 14, which connects to input K of
?ip-flop. The non-inverted outputs of the second and FF4. As a result, Q4 cannot make a transition from O to
third ?ip-?ops are input to a first AND gate, which 1 unless both Q2 and Q3 are high.
provides the J input to the fourth ?ip-?op. Likewise, FF4 is clocked by the negative edge of Q3. For the
case shown in FIG. 2 with the frequency of S2 greater
the inverted outputs of the second and third flip-flop are 50 than that of S1, Q; will be high first (when FF4 is
input to a second AND gate, which provides the K clocked) and then a few clock cycles later Q3 will also
input to the fourth ?ip-?op. The purpose of the third go high. When this occurs, both inputs to AND gate 12
?ip-?op is to prevent extraneous transitions or glitches are high and Q4 is clocked high on the next negative
in the beat frequency output Q4 of the fourth ?ip-?op. edge of Q1. With Q4 high, if Q3 is not clocked high on
In the digital mixer of the present invention, Q4 cannot 55 the next cycle due to clock jitter, Q4 will remain high
make a transition from O to 1 unless the non-inverted because Q; is still high and Q2 input to AND gate 14 is
outputs from the second and third ?ip-?ops are both still low. Thus, Q4 cannot go low momentarily unless
high. Likewise, Q4 cannot make a transition from 1 to 0 the phase of 5; changes sufficiently so that both Q2 and
unless the inverted outputs of the second and third Q3 are low (which requires a one-fourth cycle change in
?ip-?ops are both low. Thus, as long as the jitter on 5;). Since the jitter on S1 and S2 normally is much less
signals 51 and S2 is less than one-half cycle, the digital than one-fourth cycle, no glitches are generated. Digital
mixer of the present invention prevents glitches around mixer 10 is particularly effective when S1 and S; are
the transition time of the beat frequency output Q4 even nearly equal in frequency and the near in-phase condi
for very low beat frequencies. Furthermore, the digital tion persists for a relatively long period of time.
mixer of the present invention is particularly effective 65 The cross-hatched area of waveform Q3 of FIG. 2
when S1 and S; are nearly equal in frequency and the illustrates a possible ambiguity. If the frequency of sig
near in-phase condition persists for a relatively long nal S1 jitters only slightly,‘ the cross-hatched area of Q3
tirn . may be either high or low. To illustrate the immunity
 5,053,651
3 4
from glitches of the present invention, assume that sig
nals S1 and S; are at the same frequency and in the phase said second divided down signal with said components
relationship shown at the left most edge of the cross
hatched area of Q3. In this case, Q3 may alternate be
tween the high and low states in a random fashion. If 5 means for dividing down said ?rst and second mixer
Q3 is high during any cycle, Q4 will go high as illus
trated. If Q3 then goes low during the next cycle due to
phase jitter, Q4 will remain high because Q; is high
during the low-to-high transition of signal S1. Thus, Q2
would have to change by one-fourth cycle before Q4
could go low. As a result, multiple spikes on the output
Q4 are prevented.
Although the present invention has been described
with respect to a speci?c embodiment thereof, various
changes and modi?cations may be suggested to one
skilled in the art, and it is intended that the present
invention encompass such changes and modi?cations as
fall within the scope of the appended claims.
We claim:
1. A digital mixer circuit adapted for processing ?rst
and second mixer input signals in order to produce a
beat frequency output signal and for suppressing the
production of glitches in its beat frequency output sig
nal, said circuit comprising:
means for separately dividing down said ?rst and 25
second mixer input signals in order to produce a
?rst divided down signal and a second divided
down signal having inverted and non-inverted
components; .
?rst flip-flop means for providing a beat frequency
output signal, said ?rst ?ip-?op means having a
clock by said ?rst divided down signal and having
?rst and second signal inputs connected for receiv
ing non-inverted and inverted components of a
regulated signal from a means for gating so as to be
coupled for following the transitioning of said reg
ulated signal;
means for delaying said second divided down signal
in order to produce a phase delayed signal having
non-inverted and inverted components; and
means connected for receiving said non-inverted and
inverted components of said second divided down
signal and said non-inverted and inverted compo
nents of said phase delayed signal and for gating
said components of said second divided down sig
nal with said components of said phase delayed
signal in order to generate said components of said
regulated signal supplied to said ?rst flip-?op and
control the transitioning of said ?rst ?ip-?op to
occur only when said second divided down signal 50
and said phase delayed signal assume similar logic
states.
2. The digital mixer circuit of claim 1, wherein said
' means for delaying comprises a second ?ip-flop having
a clock input clocked by said ?rst mixer input signal and
coupled for following the transitioning of said second
divided down signal by having its ?rst and second sig
nal inputs connected for receiving the non-inverted and
inverted components of said second divided down sig
nal.
3. The digital mixer circuit of claim 1, wherein said
?rst J K ?ip-?op comprises a J K ?ip-?op and said mean
for gating comprises a pair of AND gates having out
puts separately connected to the J and K inputs of said
JK ?ip-?op for separately gating said components of
of said delayed signal.
4. The digital mixer circuit of claim 2, wherein said
input signals includes a pair of D ?ip-flops.
5. A digital mixer circuit adapted for suppressing the
production of glitches in its beat frequency output sig
nal, said circuit comprising:
a ?rst D ?ip-flop for dividing down the frequency of
a ?rst mixer input signal to produce a ?rst divided
signal;
a second D ?ip-flop for dividing down the frequency
of a second mixer input signal to produce a second
divided signal;
a ?rst JK ?ip-?op clocked by said ?rst mixer input
signal and coupled to follow the transitioning of
said second divided signal in order to produce a
delayed signal;
20
AND function means for gating said second divided
signal with said delayed signal and gating a com
plement of said second divided signal with a com
plement of said delayed signal in order to produce
an AND function means output; and
a second JK ?ip-?op clocked by said ?rst divided
signal and coupled to follow the transitioning of
said output of said AND function means.
6. The digital mixer circuit of claim 5, wherein said
AND function means comprises a pair of AND gates
separately connected to the J and K inputs of said sec
ond JK ?ip-?op for separately gating said second di
vided signal with said delayed signal and gating a com
plement of said second divided signal with a compleé
ment of said delayed signal.
7. A digital mixer circuit adapted for suppressing the
production of glitches in its beat frequency output sig
nal, said circuit comprising:
a ?rst D ?ip-?op for dividing down the frequency of
a ?rst mixer input signal to produce a ?rst divided
signal;
a second D ?ip-?op for dividing down the frequency
of a second mixer input signal to produce a second
divided signal;
45 a ?rst J K ?ip-flop clocked by said second mixer input
signal and coupled to follow the transitioning of
said second divided signal in order to produce a
delayed signal;
AND function means for gating said second divided
signal with said delayed signal and gating a com
plement of said second divided signal with a com
plement of said delayed signal in order to produce
an AND function means output; and
a second JK ?ip-?op clocked by said ?rst divided
signal and coupled to follow the transitioning of '
.said output of said AND function means‘
8. The digital mixer circuit of claim 7, wherein said
AND function means comprises a pair of AND gates
separately connected to the J and K inputs of said sec
ond JK ?ip-?op for separately gating said second di
vided signal with said delayed signal and gating a com
plement of said second divided signal with a comple
ment of said delayed signal.
I i l ‘ t
65