Int. ASIC conference, Sept. 1999, Washington, D.C.
A Low-Power Viterbi Decoder Design
for Wireless Communications Applications
Samirkumar Ranpara
Portland Technology Division,
Intel Corporation.
Hillsboro OR 97124
Abstract ---Viterbi decoders employed in digital
wireless communications are complex and dissipate
large amount of power. In this paper, we investigate
power dissipation for three different
implementations of Viterbi algorithm for wireless
communications applications, including our
proposed low-power Viterbi decoder. The schemes
employed in our low-power design are clock-gating
and toggle filtering. We described the behavior of
three Viterbi decoders in VHDL and synthesized
using a synthesis tool. The synthesized circuits were
placed and routed in the standard cell design
environment. Power estimation obtained through
gate level simulations indicates that the proposed
design reduces the power dissipation of an original
Viterbi decoder design by 55%.
I. INTRODUCTION
Viterbi decoders are used to decode
convolutional coding, which has been used in deep
space communications as well as wireless
communications. A wireless cellular standard for
CDMA (code division multiple access), IS-95 employs
convolutional coding. A third generation wireless
cellular standard, to be introduced in early 2000s,
adopts turbo coding, which stems from convolutional
coding.
The Viterbi algorithm is to find a maximum-
likelihood sequence of state transitions, equivalently a
path, in a trellis by assigning a transition metric to
possible state transitions. A transition metric is called a
branch metric, and the cumulative branch metrics along
the path from the initial state to a given state is called
the path metric of the state. When two or more paths
end at the same state, the path with the smallest (or
largest) path metric is selected as the most likely path.
The survivor path obtained by backtracing in time
corresponds to the decoded output.
1
Dong Sam Ha
Bradley Dept. of Electrical and Computer Eng.
Virginia Tech, Blacksburg VA 24061
E-mail: ha@vt.edu Web: www.ee.vt.edu/ha
The hardware complexity of a Viterbi decoder
is proportional to the number of states in the trellis,
which is equal to the number of states of the
corresponding convolutional encoder. For instance, the
CDMA standard IS-95 employs a convolutional
encoder with 8 states. Hence, a Viterbi decoder for the
CDMA system has 256 states in the trellis, which
results in complex hardware and high power dissipation
unless designed properly for low power dissipation.
The design of high performance Viterbi
decoders has been investigated intensively in the past
three decades [1]. Recently, the low-power design of
Viterbi decoders has been an important issue for mobile
and portable applications. Numerous techniques to
reduce power dissipation have been proposed, and we
review three recent works briefly. Chan, Lee, Lin and
Chen implemented an adaptive Viterbi decoder based
on an earlier work [2]. The adaptive decoder discards
some states (in the trellis) with high path metrics
dynamically during the decoding process. Seki et al.
and Lang et al. suggested the use of a scarce state
transition (SST) scheme [3],[4]. The scheme employs a
simple pre-decoder followed by a pre-encoder to
minimize signal transitions at the input of a
conventional Viterbi decoder, which leads to lower
dynamic power dissipation. Kang and Wilson studied
various issues in designing a low-power Viterbi
decoder for the IS-95 CDMA system [5]. Their decoder
employs various low-power design schemes such as
state partition, gated control, and gray coding.
In this paper, we investigate two different
implementations of the Viterbi algorithm in the IS-95
CDMA environment. We compare the area and power
dissipation of the two implementations and suggest a
low-power Viterbi decoder design to save power.
II. VITERBI DECODER
In this section, we describe key parameters and
the architecture of the Viterbi decoders considered in
 Int. ASIC conference, Sept. 1999, Washington, D.C.
the paper. We also explain two different methods for
management of survivor path information and a block
diagram of a Viterbi decoder.
2.1 Parameters of the proposed Viterbi decoder
The IS-95 CDMA system employs a 256-state
convolutional encoder with a rate of r=1/2 in the
forward link and a convolutional encoder with the same
number of states but with a reduced rate of r=1/3 in the
reverse link. In this paper, we consider a small-sized
Viterbi decoder, which corresponds to a scaled-down
version of the IS-95 convolutional encoder in the
reverse link, a 16-state encoder with a rate of r=1/3. The
number of symbols in a frame for IS-95 is as high as
192, but we limit the number of symbols to 20 for our
Viterbi decoder. Like the IS-95 system, the tail
sequence in each frame is fixed to ‘0’ and resets the
convolutional encoder to its initial state. Therefore, the
traceback operation can start from a known state for our
Viterbi decoders as well as for an IS-95 decoder.
2.2 Management of survivor path information
Two basic approaches used to record survivor
paths are register-exchange and traceback [1]. Since
one of our objectives is to investigate the power
efficiency of the two approaches, we describe the two
approaches in detail.
In the register exchange, a register assigned to
each state contains information bits for the survivor
path from the initial state to the current state. In fact,
the register keeps the partially decoded output sequence
along the path, as illustrated in Figure 1. The register of
state S1 at t=3 contains ‘101’, which is the decoded
output sequence along the bold path from the initial
state.
S3 11 111 1011
S2 10 110 1010
S1 1 01 101 1101
S0 0 00 000 1100
t=0 t=1 t=2 t=3 t=4
Figure 1: An example register-exchange approach
The register-exchange approach eliminates the
need to traceback since the register of the final state
contains the decoded output sequence. However, this
ii
approach results in complex hardware due to the need
to copy the contents of all the registers in a stage to the
next stage.
In traceback, the survivor branch of each state
is recorded. One bit is assigned to each state to indicate
if the survivor branch is the upper or the lower path.
Using the one-bit information of each state, it is
possible to traceback the survivor path starting from the
final state (which is identical to the initial state for the
Viterbi decoders considered in this paper). The decoded
output sequence can be obtained from the identified
survivor path through the trellis.
Figure 2 illustrates the traceback approach. For
simplicity, only the significant bits of registers are
shown in the figure. As in the register-exchange
approach, a register is assigned to each state. Each
register contains the past history of survivor branches,
‘1’ for the upper branch and ‘0’ for the lower branch in
the figure. As the decoding process proceeds, new bits
for survivor path information are appended to the
existing one.
S3 0 01 010
S2
0 00 000
S1 0 00 001 0011
0 00 000 0001
S0
t=0 t=1 t=2 t=3 t=4
Figure 2: An example of traceback approach
The survivor path information is applied to the
least significant bit of each register, and all the registers
perform a shift left operation at each stage to make
room for the next bits [12]. Hence, each register fills in
the survivor path information from the least significant
bit toward the most significant bit. The scheme is called
shift update in this paper to distinguish it from the
proposed scheme. The shift update method is simple in
implementation but causes high switching activity due
to the shift operation and, hence, results in high power
dissipation. We propose a low-power Viterbi decoder
design to address the problem.
 Int. ASIC conference, Sept. 1999, Washington, D.C.
2.3 System architecture
The major building blocks of a Viterbi decoder
are shown in Figure 3. The role of each block is
described briefly below.
Viterbi Decoding Block
Branch Path
Output interface
metric ACS metric
Input interface
storage storage
Survivor path storage
Output generator
Control block
Figure 3: Block diagram of a Viterbi decoder
Input and output interface: Input and output interface
blocks provide the interface, including a serial-to-
parallel conversion and vice versa.
Branch metric storage: The block calculates the
branch metrics of each stage in the trellis, and a branch
metric is calculated as the hamming distances between
the received symbol and expected symbol in this paper.
Path metric storage: The block stores the path metric
of each state at the current stage.
ACS: The ACS (Add-Compare-Select) block is a
collection of ACS units. An ACS unit receives two
branch metrics and two path metrics. It adds each
incoming branch metric to the corresponding path
metric and compares the two results to select a smaller
one. The path metric of the state is updated with the
selected one. An ACS unit can be time-shared between
multiple modules, but it incurs more power dissipation
due to the control circuitry. One ACS unit is assigned to
each state in our designs.
Survivor path storage: The block is a bank of
registers, which record the survivor path of each state
selected by the ACS module. A register is assigned to
each state, and the length of a register is equal to the
frame length (which is 20 for our decoders).
Output generator: This block generates the decoded
output sequence. It is trivial for the register-exchange
approach since the decoded output is the content of the
register of the final state. In the traceback approach, the
block incorporates combinational logic, which traces
back along the survivor path starting from the final state
iii
and generates the decoded output corresponding to the
path.
III. PROPOSED LOW-POWER DESIGN
We explained two basic approaches used to
record survivor paths: register-exchange and traceback.
Both methods cause substantial switching activity and
hence are inefficient in power dissipation. In this
section, we present two schemes to reduce power
dissipation in the traceback approach.
3.1 Survivor path storage block and clock gating
In the traceback approach, one flip-flop is
necessary to record the survivor branch for each state
per stage. The shift update scheme forms a shift register
for each state by collecting the flip-flops in the
horizontal direction as shown in Figure 4 (a). The
survivor branch information is filled into the least
significant bits of the registers as explained earlier. We
propose the formation of registers vertically as shown
in Figure 4 (b). The survivor branch information is
filled into registers from left to right as time progresses.
This scheme is called selective update in this paper.
New survivor
path information
S15 R15
New
survivor
path
information R0 R1 R19
S1 R1
R0
S0
t=0 t=1 t=19
(a) Shift update (b) Selective update
Figure 4: Shift update versus selective update
The key difference between the two schemes
is that the content of a register in the selective update
method does not change once it is updated. Hence, the
register incurs less switching activity, thus reducing
power dissipation. Moreover, the fact makes it possible
to apply a clock-gating scheme to further reduce power
dissipation. The clock of each register is enabled only
when the register updates its survivor path information.
Figure 5 shows the proposed survivor path
storage block for the selective update method with
employment of clock-gating. In the figure, register Ri
holds the survivor path information of all the states at
stage i, where i is 1 to 20 for our decoders. The five-bit
counter keeps track of the current stage, which is equal
to the number of code symbols received so far for the

frame. When the ith code symbol is received, the clock
of register Ri is enabled, and the survivor path
information of all the states at stage i is recorded in the
register. Note that all the other registers hold their state
since the clock of the other registers is disabled.
Therefore the proposed survivor path storage reduces
switching activity to a minimal level to save power.
Finally, it is possible to replace the five-bit counter and
the demultiplexer with a ring-counter.
Survivor path
information
16
R1 R2
Clock
0 0
Demux
0
0
1 Trace back block
1
0
5-bit
counter
Figure 5: Proposed survivor path storage block for the
selective update with clock gating
3.2 Toggle filtering of the output generator block
The output generator block in the traceback
approach traces back the survivor path after all the
symbols have been received and generates the decoded
output sequence. The block is a combinational circuit,
which can be active during only one clock cycle as
shown in Figure 6.
Begin a new frame
inactive active
18 19 20 1 2
Figure 6: Activation of the output generator block
A block diagram of the output generator block
is shown in Figure 7. Ignoring the AND gates with an
enable input for the time being, the block receives
inputs from the survivor storage block containing the
survivor path information. The block traces the survivor
Int. ASIC conference, Sept. 1999, Washington, D.C.
path at the end of the frame and generates the decoded
output sequence. The decoded output sequence is
loaded into a register at the first clock.
Since the registers update the survivor path
information progressively throughout the entire frame,
the output generator receives spurious inputs, which
cause unnecessary switching activity to dissipate
power. The proposed design blocks spurious inputs
applied to the block. The array of AND gates and the
enable signal shown in Figure 7 are introduced for this
purpose. The enable signal is activated during the one
clock period at the end of the frame as shown in Figure
7.
R 19 R 20
R1 R2 R20
Enable 16 16 16
1 0
16 16 16
20
Parallel load
Clock
Register
Figure 7: A block diagram of the output generator
IV. EXPERIMENTAL RESULTS
We measured the area and power dissipation
of the three different implementations of Viterbi
decoders: the register-exchange; the traceback approach
with the shift update scheme; and the proposed low-
power design.
We implemented the three different Viterbi
decoders in the standard cell environment. First, we
described the three Viterbi decoders at the register
transfer level in VHDL and synthesized them using a
inactive Synopsys tool. Then the synthesized gate-level circuits
were migrated into Cadence environment and placed
and routed using Cadence tools. The processing
time unit
technology used in our experiments was CMOS six-
metal layer 0.25 µm with the supply voltage of 1.8V.
Power dissipation was estimated for the
synthesized gate-level circuits using Synopsys tools.
The process for power estimation is as follows. About
10,000 random patterns were simulated at the clock
frequency of 10 MHz for each Viterbi decoder, and the
switching activity of each node was recorded. Then, the
power dissipation of the circuit was estimated using a
iv
 Int. ASIC conference, Sept. 1999, Washington, D.C.
formula, P= αCV2f, where α is the switching activity, C
is the parasitic capacitance, V is the supply voltage
(=1.8V), and f is the clock frequency. The clock
frequency was set to 10 MHz [6]. The static power
dissipation of cells was not considered due to the
limitation of the library cells used in our experiments.
Experimental results for three Viterbi decoders
are shown in Table 1. Among the three designs, the
register-exchange approach has the largest area and the
proposed low-power design the least area. The area of
the proposed design is 30% less than that for the
register-exchange approach and 22% less than that of
the traceback approach. We observed that the large area
for the register-exchange method is due to the
complexity of the survivor path storage block.
Table 1: Performance of the three Viterbi decoders
Type Register- Traceback Proposed
exchange design
Total area
176085 157284 123309
(µm2)
power
dissipation
1167 1529 683
(µw)
The power dissipation of the three decoders is
small due to the small size of the decoders and is in the
range of 0.7 mW to 1.5 mW. The traceback approach
dissipates the largest amount of power, while the
proposed low-power design dissipates the least power.
The proposed method reduces the power dissipation by
41% compared with the register exchange approach and
by 55% compared with the traceback approach. We
observed that the selective update scheme and toggle
filtering are most effective in saving power and the
clock gating the least effective. Details on the
experiments, including the area of each block and the
power dissipation for several derivatives of the
decoders, are available in [7].
V. SUMMARY
Viterbi decoders employed in digital wireless
communications are complex and dissipate high power.
In this paper, we investigate power dissipations of two
different implementations of Viterbi decoders: the
register-exchange approach and the traceback approach
with shift update scheme. We propose a low-power
Viterbi decoder design based on the traceback
approach. The schemes employed for our low-power
design are clock-gating of the survivor path storage
block and toggle filtering of output generation block.
We implemented the three designs in the
standard cell design environment and measured the
performance in terms of area and power dissipation.
Among the three implementations, it is interesting to
note that the proposed low-power design takes the
smallest area and dissipates the least power. The
proposed design reduces the power dissipation of the
register-exchange approach by 55%. However, our
design and the traceback approach with the shift update
scheme are slower than the register-exchange approach
due to the need for the traceback operation.
Finally, it is difficult to make a head-to-head
comparison of power efficiency between the proposed
method and other existing methods due to different
environments (such as hard decision versus soft
decision) and constraints imposed. Nonetheless some of
our techniques can be applied to other low-power
designs to further save power.
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