Lab report 11 - The Switched Capacitor Circuit

1st Luiz Augusto Frazatto Fernandes 2nd Yasmim de Souza

Department of Electrical and Electronic Engineering Department of Electrical and Electronic Engineering
Federal University of Santa Catarina Federal University of Santa Catarina
luiz.a.frazatto.fernandes@gmail.com yasmimdesouza30@gmail.com

Abstract—This report aims to explore the concepts of Switched

Capacitor (SC) based circuits and to analyze the behavior of a
Switched Capacitor as an AC resistance.
Index Terms—Switched Capacitor, AC resistance. ∆Q C1 · (VIN − VOU T )
= (4)
T T
I. S WITCHED CAPACITOR AS A RESISTANCE C1
∴ IAV G = · (VIN − VOU T ) (5)
T
Switched capacitors can be used to represent resistances 1
∴ REQ = (6)
controlled not only by the capacitance itself, but also by the C1 · fCLK
frequency at which the switches oscillate.
The basic circuit for a switching capacitor can be seen
below:
Given it is possible, then, to obtain the resistance when both
switching frequency and capacitance are known, the project of
VIN S1 S2 VOU T
a filter is rather intuitive:

C1 VIN S1 S2 VOU T

C1 C2

Fig. 1. Simplified switching capacitor.

From the above representation, we can then derive the

relation between the capacitor and a resistance. When S1 is Fig. 2. Simplified filter using switching capacitor.
closed, and, by definition, S2 opened, the charge distributed
on the capacitor is given by:
As seen, the equivalent circuit can be described using a
Q1 = C1 · VIN (1) resistance as a replacement of the switching capacitor:

When the switches configuration changes, and S2 is closed,

while S1 is opened: VIN REQ VOU T

Q2 = C1 · VOU T (2)
C2
Therefore, the variation of charge on the capacitor can be
derived:

∆Q = C1 · (VIN − VOU T ) (3) Fig. 3. RC filter using switched capacitor as resistance.

Then, if both sides of the above equation are differentiated Therefore, considering C1 << C2 , where C1 = 100pF and
in relation to the switches oscillation period, it gives: C2 = 4.7nF
 C2 1
τ = REQ · C2 = (7)
C1 · fCLK 0.9

REQ (100kHz) = 100kΩ (8) 0.8

REQ (200kHz) = 50kΩ (9) 0.7

REQ (500kHz) = 20kΩ (10)

voltage across V2 (V)

0.6

τ (100kHz) = 94µs (11) 0.5

τ (200kHz) = 235µs (12) 0.4

τ (500kHz) = 470µs (13) 0.3

0.2

0.1

0
0 1 2 3 4 5 6 7 8 9 10
II. T RANSIENT ANALYSIS time (s)

The transient analysis of the circuit can be done, mathemat-

ically, accordingly to the difference equation which is obtained Fig. 4. Voltage across C2 .
from the circuit. In order to do so, some considerations shall
be done: In order, then, to obtain a voltage of 0.99V across V2 , it
1. The capacitor C2 is initially discharged. must be true that:
2. The analysis starts when S2 closes. When it happens, the
C1 is considered to be already charged from the voltage
V2 [n] = 0.99 (17)
source VIN .
3. The clock frequency which controls the switches is 1Hz, 1
∴ n+1 = 0.01 (18)
and it has a square waveform with duty cycle of 50%. 2
4. VIN = 1V and C1 = C2 = 1F. ∴ n = 5.64 → n ≥ 6 (19)

When S1 is closed, C1 is charged with 1C. Then, every

time the switch S2 closes, C2 is charged by C1 , with the
difference of both of them having, by definition, the same
amount of charges accumulated on their terminals, since their
capacitances are equal. It leads to the following relation:
initially, a 1C charge is distributed for both C1 and C2 ; S1
closes and C1 is recharged until it reaches 1C total; next time
S2 closes, not only 1C will be equally redistributed across the
capacitors, but a charge equal to the sum of both capacitor’s.
Therefore, the following difference equation is derived,
having in mind that Q = C · V :
It means that, from the 7th time S2 closes, the voltage across
V2 would be at least greater or equal to 0.99V.
III. S TEADY S TATE A NALYSIS
Considering a load of 0.1mA connected to the output of the
filter, it is possible, then, to estimate the output ripple:
During the first semi-cycle of clock, when C1 is charging C2
(S2 closed), the current source of 100mA draws the equivalent
of 0.05C from the system, which is compose. Meanwhile,
when S1 is closed, then another 0.05C is dragged from
capacitor C2 .

1  
1 + Q2 [n]
Q2 [n] = · Q2 [n − 1] + 1 (14) Q2 [n + 1] = − 0.05 (20)
2 2
1  
Q2 [n] = Q2 [n + 1] − 0.05 (21)
=⇒ V2 [n] = · V2 [n − 1] + 1 (15)
2

Where, because of the steady state condition, the system is

The above difference equation has, then, a solution given periodical, and the capacitor C2 has a periodic charge.
by: The solution of the above described equations lead to:

!n+1
1 Q2 [n + 1] = 0.85C (22)
V2 [n] = 1 − (16)
2 Q2 [n] = 0.8C (23)

This solution is graphically represented by: Therefore:

 TABLE I
M EASUREMENTS FOR ”F CLK ” EQUAL TO 100 K H Z

VIN mV [RMS] VOU T mV [RMS] Freq. (Hz) Fase (º)

781 727 101.71 −11.4
VRIP P LE = 50mV (24) 762 667 206.55 −25.0
806 609k 328.84 −35.3
VM ED = 825mV (25) 778 556 399.08 −41.4
782 491 508.62 −48.0
783 440 608.99 −52.0
811 400 694.53 −56.1
771 363 810.55 −59.5
749 278 910.98 −39.7
793 256 1061.4 −47.4
Graphically, the output voltage would be something like: 755 143 2369.4 −59.7
792 108 3142.1 −71.3
743 83 4395.5 −77.5
725 74 4695.3 −78.6
783 56 6126.9 −77.6
806 47 7210.5 −80.0
769 44 8115.6 −80.6
747 41 8959.8 −80.0
8.5 774 36 10060.0 −82.6
0.825
0.8
Voltage across V2 (V)

0
0 T/2 T 3T/2 2T 5T/2 3T 7T/2 4T
Time (s)

Fig. 5. Voltage across C2 with load of 0.1A.

IV. E XPERIMENTAL R ESULTS TABLE II

M EASUREMENTS FOR ”F CLK ” EQUAL TO 200 K H Z

VIN mV [RMS] VOU T mV [RMS] Freq. (Hz) Fase (º)

788 772 103.69 −7.23
768 738 204.16 −14.4
The experiments are concerning the inductive DC-DC con- 789 730 309.89 −21.0
verter. 776 695 401.14 −24.8
729 635 515.35 −32.1
While experimentation, the following characteristics were 780 630 601.39 −35.2
810 603 711.38 −41.4
measured: 773 562 808.15 −44.0
750 528 907.68 −44.4s
799 475 1095.6 −50.5
• V+5 = 5.02 V 770 306 2037.1 −67.5
∼
• V∼ min = 0.0 mV 785 210 3059.0 −71.6
787 164 4021.7 −76.7
• V max = 10.9 mV 777 133 5014.0 −79.4
• C33 = 32.40 nF 788 108 6187.7 −81.1
• L2m = 2 ∗ 1mH 808 93 7056.1 −83.3
• R750 = 737Ω (1,5k//1.5k) 779 86 7921.7 −83.3
749 77 9130.1 −82.8
• R1.5k = 424Ω 776 68 10066.0 −84.1
• R1k//750 = 97.7kΩ
 TABLE III
M EASUREMENTS FOR ”F CLK ” EQUAL TO 500 K H Z

VIN mV [RMS] VOU T mV [RMS] Freq. (Hz) Fase (º)

787 783 103.77 −2.25
756 754 205.98 −7.25
776 766 299.55 −9.26
768 751 408.80 −10.6
786 759 512.14 −13.3
784 749 608.94 −17.2
812 764 699.48 −19.4
771 721 813.56 −22.8
751 694 905.02 −22.2
783 704 1017.4 −26.4
782 568 2008.0 −41.9
800 424 3221.0 −60.3
770 366 4058.7 −64.3
786 298 5159.7 −66.9 Fig. 7. Peak-to-peak ripple voltage for load =1 MΩ.
780 262 6068.9 −69.9
807 225 6975.3 −72.8
777 205 7934.6 −77.1
746 189 9057.9 −78.3
775 167 10097.0 −76.3

We repeated the measurements with different loads, as

shown in table IV. We took figures of the loads of 10 MΩ(Fig.
6), 1 MΩ(Fig. 7) and 100 kΩ(Fig. 8).

TABLE IV
M EASUREMENTS FOR ”F CLK ” EQUAL TO 100 K H Z WITH L OAD
Fig. 8. Peak-to-peak ripple voltage for load =100 kΩ.
VOU T V [DC] VRIP P LE mV [PP] Load (Ω)
6.37 48.0 10M
6.02 36.8 1k
5.64 31.2 560k
The next pictures show the Bode diagram for the frequencies
5.22 36.0 330k of 100 kHz (Fig. 9), 200 kHz (Fig. 10) and 500 kHz (Fig. 11),
3.62 58.0 100k comparing the measured values with the theoretical values.

0 Theoretical curve
Experimental points
-5
Gain (dB)

-10

-15

-20

-25

-30
2 3 4
10 10 10

0
Theoretical curve
Experimental points
-20
Phase (deg)

-40

-60

-80

-100
2 3 4
10 10 10
Frequency (Hz)

Fig. 6. Peak-to-peak ripple voltage for load =10 MΩ. Fig. 9. Bode diagram for the frequency 100 kHz
 5

0 Theoretical curve
Experimental points
-5
Gain (dB)

-10

-15

-20

-25

-30
2 3 4
10 10 10

0
Theoretical curve
Experimental points
-20
Phase (deg)

-40

-60

-80

-100
2 3 4
10 10 10
Frequency (Hz)

Fig. 10. Bode diagram for the frequency 200 kHz

0 Theoretical curve
Experimental points
-5
Gain (dB)

-10

-15

-20

-25

-30
2 3 4
10 10 10

0
Theoretical curve
Experimental points
-20
Phase (deg)

-40

-60

-80

-100
2 3 4
10 10 10
Frequency (Hz)

Fig. 11. Bode diagram for the frequency 500 kHz

V. C ONCLUSIONS
The values obtained were close to the theoretical values.
Furthermore, we identified that in this case the capacitive
resistance represents a discrete system, being able to discretize
a system.