9/19/2019

ĐẠI HỌC QUỐC GIA TP.HỒ CHÍ MINH

TRƯỜNG ĐẠI HỌC BÁCH KHOA
KHOA ĐIỆN-ĐIỆN TỬ
BỘ MÔN KỸ THUẬT ĐIỆN TỬ

Embedded System Design

Chapter 3: Hardware design for an embedded

system

1. Hardware components
2. Design block diagrams
3. Micro controller
4. Board bus
1

1. Hardware components
1. Microprocessors/Microcontrollers
– 8/16/32-bit microcontroller: PICs, ARMs
– DSP
2. Peripherals
– Input devices: button, switch, keyboard, mouse, touch-screen
– Display devices: LED, text LCD, graphic LCD
– Sensors: temperature, humidity, light, motion
– Actuators: motor, solenoid, relay, FET, triac, SCR
– Interfaces: UART, USB, I2C, SPI, Ethernet, Wifi, Bluetooth, Zigbee
3. Clock / reset circuits
4. Power supply
– AC/DC adapters
– Battery

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1. Hardware components
• Microprocessors/Microcontrollers
– Is a center processing unit
– Control input devices, sensors, actuators, display devices
– Process tasks, functions, and algorithms
– Interface other systems

microprocessor

Example of an embedded system

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1. Hardware components
• Microprocessors/Microcontrollers
– The Intel MCS-51 (commonly referred to as 8051) is a Harvard
architecture, CISC instruction set, single chip microcontroller (µC) series
which was developed by Intel in 1980
– PIC is a family of modified Harvard architecture microcontrollers made
by Microchip Technology
– ARM is a family of instruction set architectures for computer processors
developed by British company ARM Holdings, based on a reduced
instruction set computing (RISC) architecture.

8051 PIC ARM

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1. Hardware components
• Peripherals
– Input devices: button, switch, keyboard, mouse, touch-screen
– Display devices: LED, text LCD, graphic LCD
– Sensors: temperature, humidity, light, motion
– Actuators: motor, solenoid, relay, FET, triac, SCR
– Interfaces: UART, USB, I2C, SPI, Ethernet, Wifi, Bluetooth, Zigbee

Display device: LCD

Input device: keypad

Interface: UART

Actuator: relay

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2. Design block diagram

• Block diagram
– Is a diagram of a system in which the principal parts or
functions are represented by blocks connected by lines
that show the relationships of the blocks
– Use to model the system graphically and show the
relationships in the process.
– presents a quick overview of major process steps and key
process participants, as well as the relationships and
interfaces.

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2. Design block diagram

• Hardware block diagram
– Use a rectangle for a hardware block

– Use an arrow for a connection

One way One way

Two ways Two ways Multiple ways

Single connection Multiple connections

Curve connection

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2. Design block diagram

• Hardware block diagram
– Use a symbol for a special block

Speaker Lamp Energy Network computer Database

Antenna Bell Microphone Amplifier Converter Rectifier

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2. Design block diagram

• Block diagram features:
– Block diagram name
– Physical blocks
• Block name
• Have at least one connection
– Connections
• One direction / two directions/ multiple directions
• Single / multiple connections
• Data type of connections
– Special block
• Block name
• Extra information
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2. Design block diagram

• Recommendations
1. CPU block is at the center
2. Sensor/input blocks are at the left side
3. Actuator blocks are at the right side
4. User interface blocks are at the top
5. Memory/ database/ blocks are at the bottom
6. Use different colors for differently functional blocks
7. Use symbols for special blocks
• Exceptions
– Not enough space
– Special systems such as SoC, NoC
– Complex systems
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Sabre lite board

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Sabre lite board

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DE2 board

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Hardware block diagram – Example 1

• Poor example
Temperature PIC
Buttons
sensor Microcontroller

Heater

– No block diagram name

– Wrong direction of connection
– Problem of single / multiple connections
– No data type of connections

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Hardware block diagram – Example 2

MOTOR CONTROL BLOCK DIAGRAM

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Hardware block diagram – Example

Temperature monitor board
Temperature
LCD16x2
sensor

PIC
Microcontroller

SIM900

=> Make this block diagram better!

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Team work
• Draw the hardware block diagram of your
project

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Embedded system hardware

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Micro controller selection

• Step1. Make a list of required hardware interfaces

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Micro controller selection

• Examine the software architecture
– the algorithms require floating point
mathematics?
– Do we need special hardware like FPU, DMA
– Are there any high frequency control loops or
sensors?
– how long and how often each task will need to
run?
– What interrupts will we need?
– How many timer will we need?

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Micro controller selection

• Select the architecture

– Do we need to process 16/32 bit data often?
– Can the application get by with 8/16 bit
architectures?
– Are there libraries that support the architecture
we chose?

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Micro controller selection

• Identify Memory Needs

– What is the largest data structure?
– How much is the size of the RTOS/libraries we will
use?

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Micro controller selection

• Start searching for microcontrollers

– Supplier like Digikey, Arrow or other trusty
website.
– Chip manufacturer website (microchip, ST,TI,
Atmel, etc)
– https://en.wikipedia.org/wiki/List_of_common_m
icrocontrollers

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Micro controller selection

• Examine Costs and Power Constraints

– If the device will be powered from a battery and
mobile, low-power feature is absolutely necessary
– Price is very important with large quantity project

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Micro controller selection

• Check part availability

– Are they kept in stock at multiple distributors or is
there 6 – 12 week lead time?
– What are your requirements for availability?
– When will this part be obsolete? (life cycle)

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Micro controller selection

• Step 8: Select a development kit

– Is there any development kit available?
• Step 9: Investigate compilers and tools,
resource
– Can we have C compiler, IDE and programming
tools?
– Does this micro controller has good support
(community, libraries, resource)

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Memory
Max Erase Cost (per
Type Volatile? Writeable? Erase Size Speed
Cycles Byte)
SRAM Yes Yes Byte Unlimited Expensive Fast
DRAM Yes Yes Byte Unlimited Moderate Moderate
Masked Inexpensiv
No No n/a n/a Fast
ROM e

Once, with a
PROM No device n/a n/a Moderate Fast
programmer

Yes, with a Limited

Entire
EPROM No device (consult Moderate Fast
Chip
programmer datasheet)

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Memory
Writeable Max Erase Cost (per
Type Volatile? Erase Size Speed
? Cycles Byte)

Fast to
Limited read, slow
EEPROM No Yes Byte (consult Expensive to
datasheet) erase/writ
e
Fast to
Limited read, slow
Flash No Yes Sector (consult Moderate to
datasheet) erase/writ
e

Expensive
NVRAM No Yes Byte Unlimited (SRAM + Fast
battery)
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Memory mapped bus

rd'/wr D<0...7
P0 D Q
Processor Memory >
A<0...15
enable /CS >
/OE
ALE G /WE
addr[0-11] CS2 /CS
8 1
data[0-7] P2
74373
/WR /CS
/RD HM6264
D<0...7>
/PSEN
A<0...14>
bus
/OE
bus structure

27C256

8051
P0 Adr. 7..0 Data

P2 Adr. 15…8

Q Adr. 7…0

ALE

/RD

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Memory mapped bus with 8051

MAIN
VCC

VCC

P0.[0..7] A.[0..15] D.[0..7]

VCC
U101 U102 U103
GND P1.[0..7] nEA 31 39 P0.0 D.0 2 19 A.0 A.12 10 11 D.0
EA/VP P0.0 38 P0.1 D.1 3 D0 Q0 18 A.1 A.7 9 A0 D0 12 D.1
P1.0 1 P0.1 37 P0.2 D.2 4 D1 Q1 17 A.2 A.6 8 A1 D1 13 D.2
P1.1 2 P1.0 P0.2 36 P0.3 D.3 5 D2 Q2 16 A.3 A.5 7 A2 D2 15 D.7
P1.2 3 P1.1 P0.3 35 P0.4 D.4 6 D3 Q3 15 A.4 A.4 6 A3 D3 16 D.6
P1.3 4 P1.2 P0.4 34 P0.5 D.5 7 D4 Q4 14 A.5 A.3 5 A4 D4 17 D.5
P1.4 5 P1.3 P0.5 33 P0.6 D.6 8 D5 Q5 13 A.6 A.2 4 A5 D5 18 D.4
P1.5 6 P1.4 P0.6 32 P0.7 D.7 9 D6 Q6 12 A.7 A.1 3 A6 D6 19 D.3
P1.6 7 P1.5 P0.7 D7 Q7 A.8 25 A7 D7 1
P3.[0..7] P1.7 8 P1.6 30 ALE 11 A.9 24 A8 NC1
P1.7 ALE/P 1 LE A.10 21 A9
VCC P3.6 P3.2 12 OE A.11 23 A10
P3.7 P3.3 13 INT0 21 P2.0 74HC573 A.0 2 A11
SW101 P3.4 14 INT1 P2.0 22 P2.1 A.13 A12
C101 P3.5 15 T0 P2.1 23 P2.2 A.14 22
+
VCC 10u P3.0 10 T1 P2.2 24 P2.3 A.15 27 OE
P3.1 11 RXD P2.3 25 P2.4 20
nCS.1 WE
RESET 9 TXD P2.4 26 P2.5 26 CS1
RESET P2.5 27 P2.6 VCC CS2
RESET X1 19 P2.6 28 P2.7 6264
X1 P2.7 P2.[0..7]
R101 C102 RAM: 0x2000 - 0x3FFF
10k 30p Y 101 16 P3.6
WR 17 P3.7 nWR
11.059MHz
X2 18 RD 29 nPSEN
C103 X2 PSEN U106A U106B
30p AT89C52 nRD 1 4
nRD 3 6
Dung de ZIF 2 5
XTAL_OUT
74HC00 74HC00
VCC

R104
10k
JD02

nPSEN 1 2

PROG_MEM_OVERLAP

nCS.[0..7]
U104
A.13 1 15 nCS.0
A.14 2 A Y0 14 nCS.1
A.15 3 B Y1 13 nCS.2
VCC C Y2 12 nCS.3
6 Y3 11 nCS.4
4 G1 Y4 10 nCS.5
5 G2A Y5 9 nCS.6
G2B Y6 7 nCS.7
Y7
74LS138

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Memory bus
U12K
U11
DDR_D0 E22 A11 DDR_A0 U16 DDR3-512MB
DDR_D1 D21 DDR_D0 DDR_A0 C12 DDR_A1 DDR3-512MB
DDR_D2 C22 DDR_D1 DDR_A1 B12 DDR_A2 DDR_D8 E3 N3 DDR_A0
DDR_D3 D22 DDR_D2 DDR_A2 E13 DDR_A3 DDR_D0 E3 N3 DDR_A0 DDR_D9 F7 DQ0 A0 P7 DDR_A1
DDR_D4 A23 DDR_D3 DDR_A3 C13 DDR_A4 DDR_D1 F7 DQ0 A0 P7 DDR_A1 DDR_D10 F2 DQ1 A1 P3 DDR_A2
DDR_D5 B23 DDR_D4 DDR_A4 A14 DDR_A5 DDR_D2 F2 DQ1 A1 P3 DDR_A2 DDR_D11 F8 DQ2 A2 N2 DDR_A3
DDR_D6 D23 DDR_D5 DDR_A5 B14 DDR_A6 DDR_D3 F8 DQ2 A2 N2 DDR_A3 DDR_D12 H3 DQ3 A3 P8 DDR_A4
DDR_D7 E23 DDR_D6 DDR_A6 C14 DDR_A7 DDR_D4 H3 DQ3 A3 P8 DDR_A4 DDR_D13 H8 DQ4 A4 P2 DDR_A5
DDR_D8 D6 DDR_D7 DDR_A7 D14 DDR_A8 DDR_D5 H8 DQ4 A4 P2 DDR_A5 DDR_D14 G2 DQ5 A5 R8 DDR_A6
DDR_D9 C6 DDR_D8 DDR_A8 E14 DDR_A9 DDR_D6 G2 DQ5 A5 R8 DDR_A6 DDR_D15 H7 DQ6 A6 R2 DDR_A7
DDR_D10 B6 DDR_D9 DDR_A9 C15 DDR_A10 DDR_D7 H7 DQ6 A6 R2 DDR_A7 DDR_D24 D7 DQ7 A7 T8 DDR_A8
DDR_D11 E7 DDR_D10 DDR_A10 B15 DDR_A11 DDR_D16 D7 DQ7 A7 T8 DDR_A8 DDR_D25 C3 DQ8 A8 R3 DDR_A9
DDR_D12 C7 DDR_D11 DDR_A11 D18 DDR_A12 DDR_D17 C3 DQ8 A8 R3 DDR_A9 DDR_D26 C8 DQ9 A9 L7 DDR_A10
DDR_D13 E8 DDR_D12 DDR_A12 C16 DDR_A13 DDR_D18 C8 DQ9 A9 L7 DDR_A10 DDR_D27 C2 DQ10 A10/AP R7 DDR_A11
DDR_D14 D8 DDR_D13 DDR_A13 B16 DDR_A14 DDR_D19 C2 DQ10 A10/AP R7 DDR_A11 DDR_D28 A7 DQ11 A11 N7 DDR_A12
DDR_D15 C8 DDR_D14 DDR_A14 A16 DDR_A15 DDR_D20 A7 DQ11 A11 N7 DDR_A12 DDR_D29 A2 DQ12 A12/BC# T3 DDR_A13
DDR_D16 C18 DDR_D15 DDR_A15 DDR_D21 A2 DQ12 A12/BC# T3 DDR_A13 DDR_D30 B8 DQ13 A13 T7 DDR_A14
DDR_D17 B17 DDR_D16 B13 DDR_CLK DDR_D22 B8 DQ13 A13 T7 DDR_A14 DDR_D31 A3 DQ14 A14
DDR_D18 A17 DDR_D17 DDR_CLK A13 DDR_CLKN DDR_D23 A3 DQ14 A14 DQ15 M2 DDR_BA0
DDR_D19 A20 DDR_D18 DDR_CLKn DQ15 M2 DDR_BA0 DDR_CKE0 K9 BA0 N8 DDR_BA1
DDR_D20 C19 DDR_D19 D11 DDR_BA0 DDR_CKE0 K9 BA0 N8 DDR_BA1 DDR_CS0N L2 CKE BA1 M3 DDR_BA2
DDR_D21 B18 DDR_D20 DDR_BA0 C11 DDR_BA1 DDR_CS0N L2 CKE BA1 M3 DDR_BA2 DDR_ODT0 K1 CS# BA2
DDR_D22 B20 DDR_D21 DDR_BA1 B11 DDR_BA2 DDR_ODT0 K1 CS# BA2 ODT J7 DDR_CLK
DDR_D23 B21 DDR_D22 DDR_BA2 ODT J7 DDR_CLK DDR_RASN J3 CK K7 DDR_CLKN
DDR_D24 B2 DDR_D23 D17 DDR_ODT0 DDR_RASN J3 CK K7 DDR_CLKN DDR_CASN K3 RAS# CK#
DDR_D25 B3 DDR_D24 DDR_ODT0 C17 DDR_ODT1 DDR_CASN K3 RAS# CK# DDR_WEN L3 CAS# E7 DDR_DM1
DDR_D26 C3 DDR_D25 DDR_ODT1 DDR_WEN L3 CAS# E7 DDR_DM0 WE# LDM D3 DDR_DM3
C4 DDR_D26 A8 WE# LDM D3 VCCDR B2 UDM
DDR_D27 DDR_CS0N DDR_DM2
D5 DDR_D27 DDR_CS0 B9 VCCDR B2 UDM D9 VDD1 F3
DDR_D28 DDR_CS1N DDR_DQS1P
DDR_D29 C5 DDR_D28 DDR_CS1 D9 VDD1 F3 DDR_DQS0P G7 VDD2 LDQS G3 DDR_DQS1M
DDR_D30 B5 DDR_D29 C9 DDR_CKE0 G7 VDD2 LDQS G3 DDR_DQS0M K2 VDD3 LDQS#
DDR_D30 DDR_CKE0 VCCDR VDD3 LDQS# VDD4
DDR_D31 A5 B8 K2 K8 C7 DDR_DQS3P
DDR_D31 DDR_CKE1 K8 VDD4 C7 DDR_DQS2P N1 VDD5 UDQS B7 DDR_DQS3M
DDR_DQS0P B22 A10 DDR_RASN N1 VDD5 UDQS B7 DDR_DQS2M N9 VDD6 UDQS#
DDR_DQS0M A22 DDR_DQS0 DDR_RASn B10 DDR_CASN R145 N9 VDD6 UDQS# R1 VDD7
DDR_DQS1P B7 DDR_DQS0n DDR_CASn C10 DDR_WEN 2K R1 VDD7 R9 VDD8 B1
DDR_DQS1M A7 DDR_DQS1 DDR_WEn R9 VDD8 B1 VDD9 VSSQ1 B9
DDR_DQS2P B19 DDR_DQS1n E11 DDR_RST VDD9 VSSQ1 B9 A1 VSSQ2 D1
DDR_DQS2M A19 DDR_DQS2 DDR_RESET A1 VSSQ2 D1 A8 VDDQ1 VSSQ3 D8
DDR_DQS3P B4 DDR_DQS2n G13 A8 VDDQ1 VSSQ3 D8 C1 VDDQ2 VSSQ4 E2
A4 DDR_DQS3 DDR_VREF G12 VREF_DDR C1 VDDQ2 VSSQ4 E2 C9 VDDQ3 VSSQ5 E8
DDR_DQS3M
DDR_DQS3n DDR_VREFAO C9 VDDQ3 VSSQ5 E8 D2 VDDQ4 VSSQ6 F9
DDR_DM0 D20 F7 D2 VDDQ4 VSSQ6 F9 E9 VDDQ5 VSSQ7 G1
E6 DDR_DM0 MVDD1 F8 VCCDR E9 VDDQ5 VSSQ7 G1 F1 VDDQ6 VSSQ8 G9
DDR_DM1
DDR_DM2 C20 DDR_DM1 MVDD2 F10 F1 VDDQ6 VSSQ8 G9 H2 VDDQ7 VSSQ9
DDR_DM3 A2 DDR_DM2 MVDD3 F11 H2 VDDQ7 VSSQ9 H9 VDDQ8 A9
DDR_DM3 MVDD4 F13 H9 VDDQ8 A9 VREF_DDR VDDQ9 VSS1 B3
G15
R146240R%1 R0402 MVDD5 F14 VREF_DDR VDDQ9 VSS1 B3 H1 VSS2 E1
E10 DDR_PZQ MVDD6 F16 H1 VSS2 E1 M8 VREFDQ VSS3 G8
VCCDR E16 DDR_RETEN MVDD7 F17 M8 VREFDQ VSS3 G8 VREFCA VSS4 J2
E17 DDR_ATO MVDD8 G11 VREFCA VSS4 J2 DDR_RST T2 VSS5 J8
E18 DDR_DTO1 MVDDAO DDR_RST T2 VSS5 J8 L8 RESET# VSS6 M1
DDR_DTO0 L8 RESET# VSS6 M1 ZQ VSS7 M9
RK3188 ZQ VSS7 M9 R58 J1 VSS8 P1
BGA453-19X19 R84 J1 VSS8 P1 240R%1 J9 NC1 VSS9 P9
240R%1 J9 NC1 VSS9 P9 L1 NC2 VSS10 T1
L1 NC2 VSS10 T1 L9 NC3 VSS11 T9
L9 NC3 VSS11 T9 DDR_A15 M7 NC4 VSS12
DDR3 RK3188_K DDR_A15 M7 NC4
NC5
VSS12 NC5

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Basic protocol concepts

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A strobe/handshake compromise

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Parallel communication

• Multiple data, control, and possibly power wires

– One bit per wire
• High data throughput with short distances
• Typically used when connecting devices on same IC or same
circuit board
– Bus must be kept short
• long parallel wires result in high capacitance values which requires more
time to charge/discharge
• Data misalignment between wires increases as length increases
• Higher cost, bulky

Question:
List some parallel communications and peripherals you know?

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Serial communication

• Single data wire, possibly also control and power wires

• Words transmitted one bit at a time
• Higher data throughput with long distances
– Less average capacitance, so more bits per unit of time
• Cheaper, less bulky
• More complex interfacing logic and communication protocol
– Sender needs to decompose word into bits
– Receiver needs to recompose bits into word
– Control signals often sent on same wire as data increasing protocol
complexity

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UART connection

Standard baudrate:
1200, 2400, 4800, 9600, 19200, 38400, 57600 and 115200

Find and list all the modules and sensor you know that
use UART interface?

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I2C bus

• I2C (Inter-IC)
– Two-wire serial bus protocol developed by Philips Semiconductors
nearly 20 years ago
– Enables peripheral ICs to communicate using simple communication
hardware
– Data transfer rates up to 100 kbits/s and 7-bit addressing possible in
normal mode
– 3.4 Mbits/s and 10-bit addressing in fast-mode
– Common devices capable of interfacing to I2C bus:
• EPROMS, Flash, and some RAM memory, real-time clocks, watchdog
timers, and microcontrollers

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I2C bus structure

SDA SDA SDA SDA

SCL SCL SCL SCL

Start Sending 0 Sending 1 Stop
condition condition

From From
Servant receiver

D
C
S A A A A R A D D D A S O
T R 6 5 0 / C 8 7 0 C T P
T w K K
Typical read/write cycle

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SPI bus

• A 4-wire communications bus • Always full-duplex

• Typically communicate across short distances – Communicates in both
directions simultaneously
• Supports
– Single master – Transmitted (or received)
data may not be meaningful
– Multiple slaves
• Synchronized • Multiple Mbps transmission
speeds
– Communications are “clocked”
– 0-50 MHz clock speeds not
Bus wires uncommon
• Master-Out, Slave-In (MOSI)
• Transfer data in 4 to 16 bit
• Master-In, Slave-Out (MISO)
• System Clock (SCLK)
characters
• Slave Select/Chip Select (SS1#, …, • Supports multiple slaves
SS#n or CS1, …, CSn)

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Bus configuration

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SPI clocking
• Four clocking “modes”
– Two phases
– Two polarities
• Master and selected slave must be in the same mode
• During transfers with slaves A and B, Master must
– Configure clock to Slave A’s clock mode
– Select Slave A
– Do transfer
– Deselect Slave A
– Configure clock to Slave B’s clock mode
– Select Slave B
– Do transfer
– Deselect Slave B
• Master reconfigures clock mode on-the-fly!
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SPI clock modes

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SPI pros and cons

• Pros
– Fast for point-to-point connections
– Easily allows streaming/constant data inflow
– No addressing in protocol, so it’s simple to implement
– Broadly supported

• Cons
– Slave select/chip select makes multiple slaves more
complex
– No acknowledgement (can’t tell if clocking in garbage)
– No inherent arbitration
– No flow control (must know slave speed)
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Other board bus

• One wire
• USB
• PCI
• LVDS

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