CS/EE-520 - Computer Architecture

Quiz-4 (Sec 1), November 07, 2017 (Fall 2017)

Solutions

Consider execution of the following loop on a 3-issue/commit speculative processor. Assume that there is
only one memory unit (with effective address calculation) for LD/SD instructions. In addition, there are
separate units for integer ALU operations and branch condition evaluation.

You have 20 ROB entries, 4 Load Buffers (LB), 4 Reservation Stations (RS) for FP MUL/DIV, 2 RS for FP ADD/SUB, 6 RS
for INT ADD/SUB/Branch Instructions.

Execution stage lengths are: DIV.D: 20 cc, MUL.D: 10 cc, ADD.D/SUB.D: 5 cc, INT ADD/SUB/Branch/L.D: 1 cc, S.D: 2cc

NOTE: Consider inter-iteration dependence where applicable.

ITER MEM COMMIT to
INSTRUCTION IS EX WR to CDB COMMENTS
# READ RF/DMEM
1 L.D F1, 0(R3) 1 2 3 4 5

1 DIV.D F2, F1, F3 1, 2-4 5-24 - 25 26 RAW(F1)

1 MUL.D F6, F2, F4 1, 2-25 26-35 - 36 37 RAW(F2)

1 DADDIU R3, R3, -8 2 3 - 4, 5-36 37

1 L.D F6, 48(R2) 2 3 4 5, 6-36 37

1 ADD.D F8, F6, F2 2, 3-5-25 26-30 - 31, 32-37 38 RAW(F6), RAW(F2)

1 S.D F8, 0(R2) 3 4,5-31,32-37 - - 38 RAW(F8)

1 DADDIU R2, R2, -8 3 4 - 5, 6-37 38

1 BNEZ R3, Loop 3, 4 5, 6-38 - - 39 RAW(R3)

2 L.D F1, 0(R3) 4 5 6 7, 8-38 39

2 DIV.D F2, F1, F3 4, 5-7 8-27 - 28, 29-38 39 RAW(F1)

2 MUL.D F6, F2, F4 4, 5-28 29-38 - 39 40 RAW(F2)

2 DADDIU R3, R3, -8 5 6 - 7, 8-39 40

2 L.D F6, 48(R2) 5 6 7 8, 9-39 40

2 ADD.D F8, F6, F2 5, 6-8-28 29-33 - 34, 35-40 41 RAW(F6), RAW(F2)

2 S.D F8, 0(R2) 6 7,8-34,35-40 - - 41 RAW(F8)

2 DADDIU R2, R2, -8 6 7 - 8, 9-40 41

2 BNEZ R3, Loop 6, 7 8, 9-41 - - 42 RAW(R3)