Implementation and Design of CPLD-Based
Switched-Capacitor Step-Down DC-DC Converter
with Multiple Output Choice
Yuen-Haw Chang
Department and Graduate Institute of Computer Science and Information Engineering,
Chaoyang University of Technology, Taichung, Taiwan, R.O.C.
Abstract--A simple quasi-switched-capacitor (QSC) step-
down DC-DC converter with multiple output choice (9V/5V,
9V/3.3V, 9V12V) is designed and implemented via complex-
programmable-logic-device-based (CPLD) digital controller for
low-power applications (Input: 7.0-9.OV, load: 50-4000hms).
The integrated digital controller is implemented by combination
with Verilog CPLD and ADC/DAC chips to achieve the closed-
loop control of QSC converter. Such a Verilog-based CPLD can
make controller design more flexible, simple and reliable. In
fact, SC circuit needs no inductive element, so I.C. fabrication
is promising, and it is pretty suitable for low-power VLSI
applications. An interleaved current-mode control is employed
here from battery source interleaved charging to the series
capacitors of different cells by a voltage-controlled current
source, so the continuous input current comes into being, and it
results in a good feature: low electromagnetic interference
(EMI). Such a current-mode control is able to not only enhance
output robustness against source variation/noise, but also keep
regulation capability of converter with loading variation.
Finally, the hardware experiments are illustrated to show the
efficacy of the scheme designed, where some topics include:
voltage conversion and output ripple percentage, output
robustness against source variation, and regulation capability of
converter with loading variation.
Index Terms--quasi-switched-capacitor, step-down, DC-DC
converter, Verilog-code, CPLD.
I. INTRODUCTION
In recent years, due to the popularity of potable
electronic equipments, for example, PDA, notebook,
cellular phone, digital camera, pager, and e-book ... etc.,
their DC-DC power module always asks for some good
features of small volume, light weight, high power
density and efficiency, and good regulation capability.
Besides, to fit in with requirements of various functions
all in one, both multiple output choice and flexible
controller design become essential to power module
design gradually. Therefore, more manufactures and
researchers pay much attention to this topic on
development of a more flexible power converter for low-
power applications, ultimately requiring DC-DC
converters realized on a chip by mixed analog VLSI
technology.
In 1996, Chung and loinovici suggested a completely
new converter scheme, called quasi-switched-capacitor
(QSC) step-down converter, employed by current-mode
control idea [1]. Basically, this converter configuration is
composed of two SC cells working in anti-phase periods.
In fact, this configuration is almost similar to that of
Cheong's [2], but the most different point between them
is to use a constant current source for charging capacitors
1-4244-0844-X/07/$20.00 ©2007 IEEE. 1651
(current-mode), not to use a constant voltage source
(voltage-mode). Here, some MOSFETS are operated in
pinch-off region as a voltage-controlled current source, so
the capacitor voltage is linearly changed with time, not
exponentially charged as [2]. Thus, the input current is
continuous and constant, but not discontinuous and
variant as [2], so EMI problem can be improved. From
1999, researchers are concentrated mainly in regulation
improvement and capability enhancement of the QSC
converter [3]-[8]. Henry suggested a multi-stage design
of QSC DC-DC converter for improving voltage
regulation and current drive capability [3]. For step-down
design, n capacitors are discharged in parallel, and then
the larger output current can be generated for the heavier
load drive [4]. For step-up design, n capacitors are
discharged in series for supplying the higher voltage load
[5]. However, some improvement spaces still exist, for
example, multiple output choice, controller reliability,
and controller design flexibility. In this paper, based on
the CPLD-based digital controller, a simple QSC step-
down DC-DC converter with multiple output choice is
implemented for a variety of low-power output. Such a
Verilog-code-based CPLD chip can make controller
design more flexible, simple, and reliable.
II. CONFIGURATION OF CPLD-BAsED CONVERTER
In this section, an overall circuit configuration of
CPLD-based QSC step-down DC-DC converter is
suggested, and then the relative power-part circuit: QSC
step-down converter is introduced, including: basic
control operation and circuit formulation.
2.1 CPLD-BASED QSC CONVERTER SCHEME
Fig. 1 shows the overall circuit configuration of CPLD-
based QSC step-down DC-DC converter, and it contains
two parts: "power part" and "control part" for achieving
the closed-loop control of QSC converter with multiple
output choice. First, the above half of Fig. 1 deals with the
power part: QSC step-down DC-DC converter, which is
composed of capacitors and MOSFETS as shown in Fig.2
[1]. The basic control operation is described as follows.
In the first half-cycle, let QSA operate in pinch-off region
as a constant controlled current source, turn off SA and
QSB, and turn on SB in triode region as a small resistor.
Thus, all capacitors of cell A are linearly charged by the
constant current source. At the same time, all capacitors
of cell B are discharged to supply the load RL . Based on
the same idea, in the second half-cycle, exchange the
works of two cells, and then run the operation cyclically.

Fig. 1 CPLD-based QSC step-down converter scheme
I
IcellB
Ir-- q-- _-
iCell B
Fig.2 Power-Part: QSC Step-Down Converter
Thus, it is obvious that the output vo can be regulated
relative to how much the capacitors are charged by
controlled current source. Fig.3 shows the theoretical
current waveforms of this QSC converter.
Secondly, the control part: CPLD-based digital
controller is shown in Fig. 1 below, which is composed of
Verilog-code-based CPLD, ADC/DAC chips, crystal
oscillator, and low-pass filter. From the view of controller
signal flow, the feedback signal of the converter: output
vo is sent into the OP-amp low-pass filter for high-
frequency noise rejection, and next the filtered signal is
transferred into the digital form by an ADC chip. Then,
the filtered/digitalized output is sent into the CPLD chip,
and then compared with the desired output reference
(selected by the multiple output choice) to produce the
digital-form control signal VGS. Next, with the DAC
chips, this digital-form control signal VGS is transferred
back into the analog form, and then to adjust the drain
current iD (IQSA/IQSB of QSA/QSB) for the capacitor
voltage regulation of two cells. So, the Verilog-code-
based CPLD chip has two tasks to do: (1). the dynamic
production of the digital-form control signal VGS
according to both the filtered/digitalized output and the
desired output reference, and (2). the static generation of
the timing-control signals of QSC converter cells
according to the scheduled operation of Fig.3. Here, by
using Verilog programming, the CPLD-based digital
1652
IQSA C TS
TS /2 Ts /2
v [---l
ISA {\
0 1 - _ 1 t
IQE3B
IST
I cell AT
'c.ell B
]ID
n I
t
Cell A Charging Dis charging Charging Discharging Charging
Cell s Dischargig Charging Discharging Charging Discharging
Fig.3 Theoretical current waveform
controller has a more flexible, simple and reliable design
process for multiple output choice.
2.2 FORMULATION OF QSC STEP-DowN CONVERTER
By increasing the number of capacitors of two cells in
Fig.2, a circuit configuration of n-stage QSC step-down
DC-DC converter is suggested as shown in Fig.4 to
supply the load RL from the source Vs. This n-stage
QSC converter is still composed of two n-stage cells A
and B in parallel between source Vs and output VO. For
each cell, there includes n capacitors C1, C2 Cn, & 3n-1
switches S1 ,S2 ...S3 (i.e., power or complementary
MOSFETS), where each capacitor has capacitance C
with equivalent series resistance (ESR) rc and similarly
,
the output capacitor has capacitance C0 with ESR rc0,
and MOSFETS S ,S2 .S3n-I are operated as static
switches with the on-state resistance rT
.
According to the scheduled operation of Fig.3, it is
obvious that both cells A and B are basically operated in
anti-phase: when cell A is in the capacitor-charging
period, cell B is working in the capacitor-discharging
period, and vice versa. So, the duty cycle is fixed at 0.5
for each cell. Here, in the first half-cycle period, let QSA
be in pinch-off region as a controlled current source, turn
off SA & QSB, and turn on SB in triode region as a small
resistor. Then, n capacitors CAI -CAn of cell A are
linearly charged in series by the constant controlled
 0.5, such a constant duty cycle is much useful especially
to control design and theoretical analysis.
First, for the aim to steady-state analysis, based on the
formulation of (1), around one static operating point, all
voltages and currents are divided into two parts: static
+ operating points and dynamic small signals as:
IRL vO VCa (t) = Vca + VCa (t) VCb (t) = VCb + VCb (t), (2a,b)
Vco (t) VCO VCo (t), D (t) 'D ld (t)
= + = + , (2c,d)
vO (t) = VO + io (t) , VGS (t) = VGS + 1gs (t) I (2e,f)
I & SB where VCa, Vcb, VCo, ID,Y VGS represent the static
signals, and CaC, vCb, C,dId, io3gs are the dynamic small
c, t' ,l signals. By substituting states variation x'(t) =0 of (1),
ti
S SHIt the steady-state output VO and J0 can be shown as
11 *Steady-state analysis and expression:
IC12 -] S -I] ag ICo
VO =-CavAav Ba u= nRLID = n -LK(VGS -Vt)2, (3a)
Fig.4 n-stage QSC step-down DC-DC converter
k0 =VO/RL =n ID =n-K(VGs Vt)2, (3b)
where K is the process parameter of MOSFET, and Vt is
the threshold voltage. Here, it is notable that both output
current source, and at the same time, n capacitors voltage VO and output current J0 are not function of
CBR1 CBn of cell B are discharged in parallel to supply source Vs . In other words, when the source Vs is
the load RL . Based on the same idea, in the second half- decreasing a little, such a source variation cannot affect
cycle, they exchange their works. By this way, charging output VO & J0 immediately. Since Vs is not directly
in series and discharging in parallel for n capacitors connected to the load RL at any half-cycle of period, the
cyclically, the step-down function can be realized to keep variation of source Vs will not make any immediate
output on Vs/n ideally. Here, for simplification, since all response on output VO and Jo. That is a very excellent
capacitors of cells A and B are selected identically by the advantage for QSC converter, so it could have better
value of C, i.e. CA= =CAn= CB1= =CB=C, the output robustness against source variation or noise. Based
voltage drop across each capacitor of the same cell is on the conclusion of (3), the steady-state input/output
assumed identical, denoted by vca (t) and VCb (t) for power of QSC converter can be computed as:
capacitor voltage in cells A and B, respectively.
According to these two circuit topologies (charging into n Pi VS IS= VS ID, (4a)
capacitors in series and discharging from n capacitors in Po VO 10 RL I0 = VO *nIID (4b)
parallel), a completely state-space averaged description of Thus, using Equations (4a)-(4b), the power conversion
n-stage QSC step-down DC-DC converter of Fig.4 can be efficiency of converter is derived as Equation (5), where
derived as M = VO /Vs represents the voltage conversion ratio.
rc( +RL O RL V=P n -ID =n. VO =n.M. (5)
vCa'(t)- 2nC A 2nC A vCa(t) 2C Pi VS ID VS
VC'(t) = 0
rcO+ RL RL [iD(6)], Next, around some static operating point, followed by
2nC-A 2nC A using the small-signal analysis, the dynamic equation can
V. VC(t) +
-vco'(t)j RL RL rl + rT + RL be presented in Equation (6), and consequently the small-
2C. A 2C, . A Co -A 0
signal transfer function of the QSC step-down converter
can be also suggested in Equation (7):
rCORL (rl+rT)-RL V (t)
[VO(t)]= rco RL
VCb (t)
(la,b) *Small-signal state-space expression:
LA rco +RL RL
SvcI(t) _-
L-Vco@ (0

where 2nC A 2nC A ~(t) gm~

[,o
L o(t)j-L RL-A
+ 2C
rT + rl+RL L~co(t)i
r1 = ((C + 2rT)/n, (1 c) 0

A = (rT +rl)(rc, +RL)+rC,RL, (Id) CO Co -A

iD (t) is the average drain current of QSA/QSB, and vo (t), FrCO RL (ri + rT )RL
(6a,b)
Vco (t) represent the load voltage and output capacitor A A LCo (t)j
voltage, respectively.
In this research, such a QSC configuration is adopted *Small-signal transfer function expression:
with increasing some advantages as follows. (1) Since the gmrCoRL(+1)
interleaved current-mode technique is adopted, the input
current Is can be constant continuously. The input
G(s) V 0 (s)) 2C-A rCCO(7)
gS ( )2+ Co(rco+RL)+2nC(rT +rl +RL) 1S+I
current waveform has no high current peak/jump, so that 2nCCO A 2nCCO A
EMI problem is improved greatly. (2) Since all the where airgm
ig ,and g =2K ID/K is the trans-
elements in power-part circuit contain only MOSFETS conductance. If the QSC step-down converter is regarded
and capacitors, the uniform feature is helpful to I.C. as an open-loop plant of control system, then its small-
fabrication and realization. (3) Since the two cells are signal open-loop model has been derived here with two
working complementarily, i.e., the duty cycle is fixed at forms of: state-space and transfer function expression as

1653
Equations (6)-(7). Next, some compensation techniques
can be applied, for examples, PID compensator or state-
feedback controller, to form a closed-loop feedback
control system for more excellent response performances.
III. CONTROL DESIGN OF CPLD-BASED CONVERTER
First of all, before the closed-loop design, let's take a
look at the stability of the open-loop QSC converter.
Obviously, for the better power efficiency, the applied
value of load resistance RL is supposed to be much larger
than value of parasitic rT , rc , rc0 . So, the assumption of
RL >> rc, RL >> rco, RL >> rT is supposed to be accepted
basically. In fact, the resistance value of load RL is about
in Q -level, and the value range of parasitic rT , rc , rco is
about in mQ -level. Around some operating point of VGS,
the open-loop two-order transfer function of (7) can be
approximately reduced into the open-loop one-order
transfer function model with one dominant pole as:
C(s)
G gs
= 0 n -grn-RL8a
(C + 2nC)RL s+l
poled ( (8b)
(CO + 2nC)RL
It is obvious that the open-loop QSC step-down converter
is locally stable because this dominant pole is located in
the left half of s-plane. Furthermore, the variation of
operating point of VGS will not directly affect the
location of the dominant pole, so the result almost
ensures the global stability of the open-loop QSC
converter. Thus, it is one of advantages that the converter
scheme has an inherent good stability.
Next, let's discuss the closed-loop control design and
implementation of the QSC converter. First for steady-
state regulation, according to (3a), the steady-state output
voltage V. is linearly regulated by drain current 'D
which is controlled by the gate-source voltage VGS
Thus, for the aim to steady-state voltage regulation, it is
desired that the steady-state output voltage V. can follow
reference Vref by adjusting the gate-source VGS. Based
on (3a), let V. be identical to the desired Vref, and then
obtain the nonlinear compensator f as (9) to produce the
static gate-source voltage VGS for achieving the steady-
state regulation,
VGS f(Vref ) Vrf +v *
nRLK
Secondly for the small-signal transient regulation,
according to (7), the small-signal output voltage vO is
with two-order transfer function of small-signal gate-
compensator
(eCVL
V
C ) )A ; 0
Vtref C 3 s
1p igVs
Fig. 5 Overall closed-loop control of QSC converter
source voltage 1gsI Thus, for the aim to small-signal
voltage regulation, it would be better to employ the
closed-loop control for dynamic compensation of output
vO As the control scheme of Fig. 1, a simple PI-type
I
controller with cut-off frequency WL and proportional
gain KP is applied here to compensate the transient
difference between output & desired reference, even for
some good performances, for example, rise time and
setting time. In this PI controller, there are two
parameters of WL , KP, where the gain KP is designed for
tracking error compensation, and the cut-off frequency
WL is designed for the possible high-frequency noise
rejection. Therefore, combining the ideas of steady-state
and transient control, the overall closed-loop control of
QSC step-down DC-DC converter can be presented as
shown in Fig.5, in which a voltage limiter of VGS is used
in order to protect the drain current not to be larger than
safe drain current of MOSFET.
Next, let's look at CPLD controller implementation.
Here, an integrated digital controller is implemented via
(8a)
combination with Verilog-code CPLD and ADC/DAC
/OSC/OP chips to achieve the closed-loop control of QSC
step-down converter with multiple output choice. From
the angle of signal flow of the digital controller, the
output signal vo of the converter gets in through the OP-
amp low-pass filter for the high frequency noise rejection,
and then the filtered analog output signal is transferred
into the digital form by the ADC chip. Then, the
digitalized output signal is sent into the CPLD chip and
compared with desired reference Vref, and following to
produce the suitable digital-form control signal vGs.
Next, with the DAC chips, the digital-form control signal
vGs can be transferred into the analog form for the
adjustment of iD . The scheme of the digital controller is
shown in the Fig. 1 below. In addition, the CPLD chip has
to handle the timing control of the converter in
accordance with the scheduled operation of Fig.3. Here,
by using Verilog programming, both control signal
production and timing control operation can be easily
realized and integrated in this CPLD chip.
IV. EXPERIMENT OF CPLD-BAsED QSC CONVERTER
In this section, the hardware implementation and
experiment of the closed-loop CPLD-based QSC step-
(9) down DC-DC converter is illustrated. The hardware
implementation of closed-loop QSC converter is shown
in the photo of Fig.6, and all the hardware elements are
listed in Table.l. Here, the core: CPLD chip has to not
only handle the control signal production, but also realize
0oltaae
vGs
tS
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 compensation as Equation (9) in the CPLD chip. So, the
table-look-up method is employed here to produce the
static control signal VGS for the different reference Vref,
i.e., the static VGS can be computed for the different
Vref , and stored in the program in advance, as the
declared parameters: v5,v3, and v2 in Appendix. Here,
the cut-off frequency WL is taken by 1470rad/sec, i.e.
234Hz, for the high-frequency noise reduction. In
addition, the different gain K. can be designed for the
different output choice, where Kr is set on the values of
8/8/6 for the desired output voltage of 5V13.3V12V
respectively, as shown in Appendix. The hardware
implementation of the closed-loop CPLD-based QSC
step-down converter of Fig.6 is with the circuit-layout
size of 12cmx8cm, and the wires of the circuit board is
made by the prototype circuit-carving machine. For
Fig. 6 Hardware implementation of CPLD-based QSC step-down checking closed-loop performance, some experiments are
converter with multiple output choice discussed and measured (Tool: Tektronix Oscilloscope
TDS 210), including: (A). voltage conversion and output
Table. 1 Hardware elements of CPLD-based converter ripple percentage, (B). output robustness against source
IRF510(NMOS) x 2 CPLD XC9572 x 1 variation, and (C). regulation capability of converter with
J77(PMOS) x 2 ADC0804(ADC) x 1 loading variation.
33ufx 3 DAC0800(DAC) x 2
(A). First, the QSC step-down converter is operated
47ufx 1 HA17741(OP amp) x 6
from source Vs of 9V conversion into output VO of
2V ( Vref = 2V ) for supplying the load RL of 200Q at the
1.8402MHz Crystal x 1 | DIP 2bit x 1
switching frequency of 12.5kHz. The steady-state output
conversion is measured as shown in Fig. 8(a). It is
obvious that the conversion works stably, and the output
ripple percentage can be measured and computed as:
rp = Avo/V0 = 1.510% . Here, for simplifying hardware
implementation, the stage number n is only taken by one
( n 1), but it results in the bad efficiency about 22%
indeed. In order to improve the power efficiency, it is
practicable to increase or change the stage number n for
the better efficiency. According to the theoretical
Fig. 7 Terminals of CPLD controller conclusion of (5), the efficiency is enhanced up to 66%
while the stage number n is three (n = 3 ), or further, the
Table 2. Terminals of Verilog-code-based CPLD efficiency can be improved to 88% while number n is
Terminal name Bit I/0 Function taken by four ( n =4 ). Besides, for the other output
CLK 1 Input Input for clock signal from the choices ( Vref 3.3V, 5V ), the steady outputs are
crystal oscillator measured as shown in Fig. 8(b)-(c). It is obvious that the
SELI I Input Selection input 1 for multiple conversions still work stably, and the relative output
output choice ripple percentages are measured as: 1.78% and 1.01%,
SEL2 I Input Selection input 2 for multiple respectively. These results show that the QSC converter
output choice hardware has a pretty good steady-state performance.
VO[7:0] 8 Input Input for the filtered digitalized (B). Secondly, since the source voltage is decreasing
output from ADC naturally with increasing running time of battery, or
OUTNI I Output Output for the control of varying from the bad-quality battery, the output
MOSFET SA
robustness against the source noises must be considered
OUTN2 I Output Output for the control of and emphasized. Here, it is applied to the hardware that
MOSFET SB
source Vs has the average value of 8V and extra 0.5V
OUTADC1[7:0] 8 Output Output for the control of pulse noise as shown in Fig. 9(a) above. Then, the output
MOSFET QSA to DAC
OUTADC2[7:0] 8 Output Output for the control of voltage vo is measured as shown in Fig. 9(a) below, and
MOSFET QSB to DAC it is found that output vo is still following the reference
Vref to supply output of 2V , even though source Vs has
the timing control operation as Fig. 3. So, by using the smaller than standard source of 9V and the pulse
Verilog programming, both the goals can be easily disturbance. Besides, for the other output choices
achieved and integrated in this CPLD chip, and Appendix ( Vref =3.3V, 5V ), the output robustness can be also
deals with the embedded Verilog code of CPLD digital experimented and measured as shown in Fig. 9(b)-(c). In
controller, where there are 8 output/input terminals these figures, it is found that this converter can still
planned as shown in Fig. 7, and their functions/behaviors firmly supply the outputs of 3.3V, 5V respectively in
are described in Table 2. To deserve to be mentioned, it's spite of the source variation. So, the closed-loop QSC
not easy to realize square-root computation of nonlinear converter has a good robustness against source noises.

1655

Fig. 8(a) Steady output
Fig. 8(b) Steady output conversion (mode: 9V/3.3V)
T~~~~~~~~:::
Fig. 8(c) Steady output conversion (mode: 9V/5V)
Fig. 9(a) Steady Output while
~~~~~~~I
VW
conversion (mode: 9V/2V) Fig. 9(b) Steady Output while source variation (mode: 9V/3.3V)
Fig. 9(c) Steady Output while source variation (mode: 9V/5V)
(C). Finally, the regulation capability of the converter
with loading variation is discussed. Fig. 10(a) shows the
transient output waveform when the load is added in
double, i.e. the same load is added and connected in
parallel with the output terminals (200Q -* IOOQ). Fig.
10(b) shows the transient output waveform when the
added load is removed away from the output terminals
(IOOQ -* 200Q). From Fig. 10(a)-(b), it is obvious that
the output voltage can be still regulated to hold on about
2V ( Vref =2V ) no matter when the extra load is added in
or removed away. Of course, ones can also find that the
output ripple becomes larger during the time interval of
supplying the heavier load. Besides, for the other output
choices ( Vref =3.3V, 5V ), the output regulation capability
can be also experimented and measured as shown in Fig.
10(c) (f). In these figures, it is found that this converter
can still keep the outputs on about 3 .3V, 5V respectively
in spite of the loading variation. So, by using this CPLD
digital controller, this closed-loop QSC converter has a
pretty good regulation capability.
V. CONCLUSIONS
A simple QSC step-down DC-DC converter with
multiple output choice (9V/5V, 9V/3.3V, 9V/2V) is
implemented by using CPLD-based digital controller for
a variety of low-power output requirement (Specification:
Input voltage: 7.OV 9.0V, load range: 50-4000hms). In
this paper, an integrated digital controller is designed and
9V/2V)
implemented via combination with Verilog-code CPLD
source variation (mode:
and ADC/DAC chips to achieve the closed-loop control
1656
 -4

...... .... .... .... ....._ .... .... .... .... -..._

Fig. 10(a) Transient output during increasing load (mode: 9V/2V) Fig. 10(e) Transient output during increasing load (mode: 9V/5V)

...

...
..

.. ..

., .,
.

Fig. 10(b) Transient output during decreasing load (mode: 9V/2V) Fig. 10(f) Transient output during decreasing load (mode: 9V/5V)

of QSC step-down DC-DC converter. Such a Verilog-

Fig. 10(c) Transient output during increasing load (mode: 9V/3.3V)
Fig. 1O(d) Transient output during decreasing load (mode: 9V/3.3V)
based CPLD can make controller design more flexible,
simple and reliable. Finally, the hardware experiments are
illustrated to show the efficacy of the scheme, where
some cases include: voltage conversion and output ripple
percentage, output robustness against source variation,
and converter regulation capability for loading variation.
The following advantages of the proposed scheme are
involved. (i) Since all the elements of QSC converter
only contain MOSFETS and capacitors, the uniform is
helpful to I.C. fabrication future. (ii) An interleaved
current-mode control is employed from battery source
interleaved charging to the series capacitors of the
different cells by the controlled current source, so the
continuous input current comes into being, and then it
results in a good feature: low EMI. (iii) Such a Verilog-
code-based CPLD chip here can really make the
controller design of QSC converter more flexible, simple
and reliable. (iv) Due to high-frequency operation, it
results possibly in low output voltage ripple. (v) Since
source Vs is not directly connected to the load RL any
time, the source variation will not make any immediate
response on output VO and lo. So, it could be with the
better output robustness against source variation or noise.
(vi) Since two cells are complementarily working in anti-
phase, i.e., the duty cycle is fixed at 0.5, such a constant
duty cycle is much useful especially to control design and
theoretical analysis of the converter. (vii) The dominant
pole is located in the left half of s-plane, so it is obvious
that the open-loop QSC converter is locally stable. Thus,
the circuit scheme has an inherent good stability.

1657
 APPENDIX else
begin
The Verilog code of CPLD-Based controller: vdata=v2;
//Definition// end
module end
Switch(clk vo outadcl ,outadc2,outnl ,outn2,sell,sel2) end
input clk sell sel2; 2'bl 1: vdata=vo;
input 7:61 vo' endcase
output [7:0] outadcl,outadc2; //Timing Control//
output outnl,outn2; tmD=tmp+f I
reg [7:0] outadcl,outadc2,vdata,vr; if(tmpp ::::6 K& flag=-O)
reg outnl,outn2; begin
reg vll hb32 ctmpp outn2=-outn2;
end
parameter v5=8'hac,v3=8'hb4,v2=8'hcO; //Table-look-up// if(tmp 6 && flag=1)
begin
always w(negedge clk) outnl=outnl;
begin end
case ( {sel2 sel I}) if(tmp 2 && flag=1)
I/OIP Choice: 5V'II outadc2=vdata;
2'tUU if(tmp 2 && flag=O)
outadc I=vdata;
vo <= 8'hef) if(tmp==7)
begin begin
vdata = 8'hO 1;
end
else if(vo >= 8'hff) begin
begin outadcl=8'hff
vdata= 8'hff; outnl outni;
end end
else if(flag-=0)
be in begin
iT( vo <= 8'hf9) outadc2=8'hff
begin outn2=-outn2;
vr=(8'hfa-vo)* 8; end
vdata= v5-vr; tmp=O;
end end
else if( vo >= 8'hfb) end
begin endmodule
vr = (vo-8'hfb)*8; I/Gain: Kp=8//
vdata= v5+vr;
end ACKNOWLEDGEMENT
else
begin The research of circuit theory and application of Yuen-
vdata= v5;
end Haw Chang is supported by National Science Council,
end Taiwan, R.O.C., under NSC 95-2221-E-324-005.
end
I/OIP Choice: 3.3VII
2bUl
2,Tb) l:I
in=
begin
8'h93) REFERENCES
vdata=8'hO 1; [1] H. Chung and A. loinovoci, "Switched-capacitor-based
end DC-to-DC converter with improved input current
else if (vo>=8'hb2) waveform," in Proceedings IEEE International Symposium
begin
vdata=8'hff; on Circuits and Systems, Atlanta, USA, pp.541 544, 1996.
end [2] S. V. Cheong, S. H. Chung, and A. loinovici, "Duty-cycle
else
be gn control boosts dc-dc converters," IEEE Circuits and
iT(vo<=8'ha5) Devices Mag., vol.9, no.2, pp.36-37, 1993.
begin [3] H. Chung, "Design and analysis of a switched-capacitor-
yr=(8'ha5-vo)* 8;
vdata=v3-vr; based step-up DC/DC converter with continuous input
end current," IEEE Trans. on Circuits and Systems, vol.46,
else if(vo>=8'ha9)
begin no.6, pp.722-731, 1999.
vr=(vo-8'ha9)* 8; I/Gain: Kp=8// [4] H. S. H.Chung, S. Y. R. Hui, and S. C. Tang,
vdata=v3+vr;
end "Development of a multistage current-controlled switched-
else capacitor step-down DC-DC converter with continuous
begin input current," IEEE Trans. on Circuits and Systems,
vdata=v3;
end vol.47, no.7, pp.1017 1026, 2000.
end [5] H. Chung and Y. H. Mok, "Development of a switched-
end
I/OIP Choice: 2VII capacitor DC/DC boost converter with continuous input
21 0: current waveform," IEEE Trans. on Circuits and Systems,
i=vo< 8'h4c) vol.46, no.6, pp.756-759, 1999.
begin [6] H. S. H. Chung, S. Y. R. Hui, S. C. Tang, and A. Wu, "On
vdata=8'hO 1; the use of current control scheme for switched-capacitor
end
else if (vo>=8'h70) DC/DC converters," IEEE Trans. on Iindustrial
begin Electronics, vol.47, no.2, pp.238-244, 2000
vdata 8'hff;
end [7] H. S. H. Chung, W. C. Chow, and S. Y. R. Hui,
else "Development of a switched-capacitor DC/DC converter
be in
iT(vo<=8'h63) with bi-directional power flow," IEEE Trans. on Circuit
begin and Systems, vol.47, no.9, pp.1383 1390, 2000.
yr=(8'h63-vo)*6; [8] Yuen-Haw Chang, "Design and analysis of power-CMOS-
vdata v2-vr;
else if(vo>=8 h67) gate-based switched-capacitor DC-DC converter with step-
begin down and step-up modes," International Journal of Circuit
vr=(vo-8'h67)*6; H/Gain: Kp=6// Theory and Applications, vol.3 1, pp.483 511, 2003.
vdata=v2+vr;
end

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