CAMP:8085 Peripherals Summary-1

EE309: Computer Organization, Architecture and

MicroProcessors
http://www.ee.iitb.ac.in/∼sumantra/courses/up/up.html

The 8255A: Programmable Peripheral Interface

PROGRAMMER’S VIEW OF THE 8255A

A1
A0
8−BIT PORT A
A0 and A1 select entities:
CONTROL REGISTER

A1 A0 Selection
4−BIT PORT CU 0 0 Port A
CS
4−BIT PORT CL 0 1 Port B
1 0 Port C
1 1 Control Register

8−BIT PORT B
RD
WR
(40−PIN DEVICE: SAME SIZE AS THE 8085!)

COMMAND WORD: I/O MODE

PORT A CU PORT B CL
1 1/0 1/0 1/0 1/0
1: I/O MODE I/O I/O MODE I/O I/O
00: MODE 0 0: MODE 0
01: MODE 1 1: MODE 1
1X: MODE 2
(Intel Recommendation: Don’t Cares: 0, for future compatibility)

COMMAND WORD: BSR MODE

0 X X X S/R
0: BSR BIT NUMBER 1: SET
in Port C 0: RESET

BSR Mode
• To set / reset bits in Port C, the control word is written in the Control
Register
• BSR Control Word affects one bit at a time
• Does not affect the I/O mode

Sumantra Dutta Roy, EE, IITB sumantra@ee.iitb.ac.in

 CAMP:8085 Peripherals Summary-2

8255A MODE 1: INPUT CONFIG 8255A MODE 1: OUTPUT CONFIG

PORT A LINES + HANDSHAKE

PORT A LINES + HANDSHAKE

PORT A INPUT PORT A OUTPUT
INTE A INTE A
PC 4 STB A PC 6 ACKA
PC 5 IBF A PC 7 OBFA

PC 3 INTRA PC 3 INTRA

PORT B INPUT PORT B OUTPUT

PORT B LINES + HANDSHAKE

PORT B LINES + HANDSHAKE

INTE B INTE B
PC 2 STB B PC 2 ACKB
PC 1 IBF B PC 1 OBFB

PC 0 INTRB PC 0 INTRB
RD WR
PC 6,7 I/O PC 4,5 I/O

STATUS WORD STATUS WORD

I/O I/O IBF A INTE A INTRA IBF B INTE B INTRB OBFA INTE A I/O I/O INTRA INTE B OBFB INTRB

(PORT C, WITH STB REPLACED BY INTE) (PORT C, WITH ACK REPLACED BY INTE)

I/O Mode
1. Mode 0
• Simple I/O for Ports A, B, C
• A port is either an input port, or an output port
• Inputs are not latched, outputs are
• Ports do not have interrupt or handshake capability
2. Mode 1
• Ports A and B: a port is either an input port, or an output port
• Each port uses 3 lines of Port C for handshaking, the remaining 2
bits can be used for simple I/O (Mode 0)
• Input and output data are latched
• Interrupt Logic is supported
3. Mode 2
• Port A used as a bidirectional port
• Port B can be used in either Mode 0 or Mode 1
• Port A uses 5 bits of Port C for handshaking: the remaining can be
used for simple I/O (Mode 0) for Port B in Mode 0, or as handshaking
lines for Port B in Mode 1

Sumantra Dutta Roy, EE, IITB sumantra@ee.iitb.ac.in

 CAMP:8085 Peripherals Summary-3

8255A MODE 2 & MODE 0(INPUT) 8255A MODE 2 & MODE 1(OUTPUT)

PORT A LINES + HANDSHAKE

PORT A LINES + HANDSHAKE

PORT A PORT A

PC 4 STB A PC 4 STB A
PC 5 IBF A PC 5 IBF A
PC 6 ACKA PC 6 ACKA
PC 7 OBFA PC 7 OBFA
PC 3 INTRA PC 3 INTRA

WR PORT B INPUT WR PORT B OUTPUT

PORT A LINES + HANDSHAKE

PORT B AND C LINES
PC 2 ACKB
PC 1 OBFB

PC 0 INTRB
RD RD
PC 0−2 I/O

The 8253/4: Programmable Interval Timer

The 6 Modes of the 8253/4
1. Mode 0: Interrupt on Terminal Count
• Rules for OUT:
– After the count reaches 0, OUT goes high
– OUT remains high until a new count or command word is loaded
– Counting temporarily stops when the GATE is disabled, and
continues again when the GATE goes to logic high
• Auxiliary Rules: If count register reloaded while counting is on, then
– After first byte of count written, the current counting stops
– After second byte of count written, the counting restarts with
the new count number
• Rules for GATE
– Low / going low: disables counting
– High: enables counting
– Other cases: no effect
2. Mode 1: Programmable One-Shot / Hardware Retriggerable
One-Shot
• Rules for OUT
– OUT is initially high
– When GATE is triggered, OUT goes low
– After the end of the count, OUT goes high again
• Auxiliary Rule: If new count loaded while output is low, doesn’t
affect duration of one-shot OUT negative pulse until the next trigger
Sumantra Dutta Roy, EE, IITB sumantra@ee.iitb.ac.in
 CAMP:8085 Peripherals Summary-4

PROGRAMMER’S VIEW OF THE 8253/4

A1
A0 CLK 0
COUNTER 0 GATE 0

CONTROL REGISTER
OUT 0 A0 and A1 select entities:

A1 A0 Selection
CLK 1 0 0 Counter 0
CS COUNTER 1 GATE 1
OUT 1 0 1 Counter 1
1 0 Counter 2
CLK 2 1 1 Control Register
COUNTER 2 GATE 2
RD OUT 2
WR
(24−PIN DEVICE)

THE 8253/4 CONTROL WORD

000 to 101: Modes 0 to 5
110 to 111: Modes 2 to 3 (Intel Recommendation:
SELECT Don’t Cares: 0, for future compatibility)
COUNTER MODE

00 to 10: Counter #0 to #2 R/W BCD?

11: Read−Back Command 00: Counter Latch 1:BCD counter
(8254 only !) 01: R/W LSB only 0: Binary Counter
10: R/W MSB only
11: R/W LSB, then MSB

8254 READ−BACK COMMAND 8254 READ−BACK STATUS

OUT
1 1 #2? #1? #0? X

COUNT STATUS COUNTER NULL R/W MODE BCD?

NUMBER COUNT?
0: LATCH THE COUNT 0: LATCH THE STATUS

• The current count can be read anytime, doesn’t affect one-shot pulse
• Rules for GATE
– Rising: Initiates counting, resets OUT on next clock
– Other cases: no effect
3. Mode 2: Interrupt on Terminal Count
• Rules for OUT
– Generate a pulse of width = clock period, at a given interval
– When a count is loaded, OUT goes high and remains high until
count = 1, then goes low for one clock period (at the count of 0)
– Count reloaded automatically, the pulse generated continuously
– count = 1 is not allowed !
• Auxiliary Rule: If count register reloaded while counting is on, then
– The current output pulse timing is not affected
– The next one is, according to the new value of the count
• Rules for GATE
– Low / going low: disables counting, OUT goes high immediately
Sumantra Dutta Roy, EE, IITB sumantra@ee.iitb.ac.in
 CAMP:8085 Peripherals Summary-5

– Rising: Initiates counting

– High: Enables counting
4. Mode 3: Square Wave Generator
• Rules for OUT
– When the count N is loaded, OUT is high
– If N is even, the pulse stays high for the first N/2 clock cycles,
and low for the next N/2. If N is odd, the pulse stays high for
(N + 1)/2 clock cycles, and then low for (N − 1)/2 clock cycles
– When the count should have hit 0 (0 is not counted), OUT goes
low for the next cycle, and the count is reloaded again
– For an even count, the count is decremented by 2
– For an odd count, for the first (high) half, the count is first
decremented by 1, then by 2. For the second (low) half, the
count is first decremented by 3, then by 2.
• Auxiliary Rule: If count register reloaded while counting is on, then
– The current output pulse timing is not affected
– The next one is, according to the value of N
• Rules for GATE
– Low / going low: disables counting, OUT goes high immediately
– Rising: Initiates counting
– High: Enables counting

5. Mode 4: Software-Triggered Strobe

• Rules for OUT
– OUT is initially high
– Goes low for one clock period at the end of the count, and then
goes high after the end of the count
• Auxiliary Rule If count register reloaded while counting is on, then
the new count is initialized on the next clock pulse
• Rules for GATE
– Low / going low: disables counting
– High: Enables counting
– Other cases: no effect
6. Mode 5: Hardware-Triggered Strobe
• Rules for OUT
– OUT is initially high
– Goes low for one clock period at the end of the count
• Auxiliary Rule If count register reloaded while counting is on, then
the new count is initialized on the next clock pulse
• Rules for GATE
– Rising: Initiates counting
– Other cases: no effect

Sumantra Dutta Roy, EE, IITB sumantra@ee.iitb.ac.in