SEMESTER: WINTER, SESSION:2020-2021

Assignment-1
PROBLEMS ON FINITE STATE MACHINE

1. Design a 3-bit Gray code counter FSM with no inputs and three outputs. When reset, the
output should be 000. On each clock edge, the output should advance to the next Gray code.
After reaching 100, it should repeat with 000. Draw a schematic for this counter using T flip-
flops.

2. Design a sequence detector to detect a pattern 1001.Design in both Moore Machine and
Mealy Machine, also consider both overlapping and non-overlapping scenarios.

3. Design a 4-bit sequence detector using state minimization/reduction techniques with the
following specification. The machine has a single input X and output Z. The output is asserted
after each 4-bit input sequence if it consists of one of the binary strings 0110 or 1010. The
machine returns to the reset state after each 4-bit sequence. Assume a Mealy implementation.
X = 0010 0110 1100 1010 0011
Z = 0000 0001 0000 0001 0000
The output is asserted only after the previous four serial inputs match one of the specified
strings. Also, the input patterns do not overlap: the machine makes a decision to assert its
output after each group of 4 bits.

4. Design a mealy machine that scans sequence of input of 0 and 1 and generates output ‘A’ if
the input string terminates in 00, output ‘B’ if the string terminates in 11, and output ‘C’
otherwise.
5. Design a modulo-6 counter, which counts in the sequence 0, 1, 2, 3, 4, 5, 0, 1, . . . . The
counter counts the clock pulses if its enable input, w, is equal to 1. Use D flip-flops in your
circuit.

6. Derive a minimal state table for a single-input and single-output Moore-type FSM that
produces an output of 1 if in the input sequence it detects either 110 or 101 patterns.
Overlapping sequences should be detected.

7. A sequential circuit has two inputs, w1 and w2, and an output, z. Its function is to compare
the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles,
the circuit produces z = 1; otherwise, z = 0. For example

w1 : 0110111000110

w2 : 1110101000111

z: 0000100001110

8. Minimize the number of states for the FSM shown below

 Present Next state Output (Z)
state W=0
W=1
A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0

9. Reduce the following state table to a minimum number of states.