MILITARY COLLEGE OF SIGNALS

HUMAN RESOURCES MANAGEMENT

SUBMITTED TO:
Muhammad Hammad

SUBMITTED By:
GC
GC
GC
GC
Section:
BETE 56-B.
 Lab Experiment 04
INTERFACING RAM IN PROTEUS

Objectives:
In this lab we will study about
• Interfacing RAM and ROM in Proteus
• Data reading and Writing on RAM

Used Components / Software

• Proteus Simulator
• IS61C1024AL-12JI Static RAM
• 27C512 ROM
• 74HC163 4-bit synchronous up Counter

RAM:
Memory unit: Stores binary information in groups of bits called words. Memory word:
group of 1’s and 0’s and may represent a number, character(s), instruction, or other
binary-coded information. Most computer memories use words that are multiples of 8
bits (byte). 32-bit word ‡ 4 bytes. Each word in memory is assigned an address 0 up to
2k – 1 (k = # of address lines).

Steps:
1. Data will be written on RAM using ROM.
2. Counter is used to provide 4-bit address to both RAM and ROM.

1
3. In this Lab we will be using just lower four bit of address (i.e. A0-A3 first 16 locations) of
both RAM and ROM. All other address bits are grounded.
4. 3 types of control signals are required by RAM
a) CE=> Chip Enable. RAM will work only if this pin is activated
b) OE=> Output Enable. Reading is possible from Ram if this pin is activated. OE is
active low. Its value should be 0 for reading and 1 for writing.
c) WE => Write Enable. This pin is also active low, and it should be 0 for writing on
RAM. While using this pin, its value should be opposite to clock pulse. RAM reads
the value on lower pulse. This pin should be provided with a clock pulse opposite to
main clock.

5. Data Pins of ROM are connected trough tristate buffer to the I/O pins of RAM.
6. In the write operation, address is provided from counter to both ROM and RAM and data
from ROM is written on RAM.
7. While Writing on RAM, control signals should be changed as follow.
• OE’ of RAM => 1
• Wbit of RAM => 1, by doing this WR’ of RAM will be 0 (for pulsating output, it
should be connected to clock)
2

• OE’ / CE’ of ROM => 0 to activate the ROM

8. While reading from RAM, control signals should be changed as follow

• OE’ of RAM => 0
• Wbit of RAM => 0, by doing this WR’ of RAM will be 1
• OE’ / CE’ of ROM => 1 to disable the ROM
• If we want to stop the counter and provide addresses manually to RAM while reading,
its ENP and ENT should be 0.

Lab Tasks
Design a schematic that loads data from ROM to RAM starting from FFFFH,0000H,0001H to
FFFEH. At FFFEH it stops loading. Give a ram address you should see the data of
corresponding address will be shown in the output of RAM That means data from ROM has
been saved to RAM.

INPUTS
OUTPUT ON PROTEUS
OUTPUT ON PROTEUS WHEN BINARY NUMBERS IS
CALLED