Performance Analysis of A Positive Output Voltage Dual

Journal of Circuits, Systems, and Computers
Vol. 27, No. 10 (2018) 1850159 (22 pages)

.c World Scienti¯c Publishing Company
#
DOI: 10.1142/S0218126618501591
Performance Analysis of a Positive Output Voltage Dual

Input DC–DC Converter for Hybrid Energy Application¤
Sivaprasad Athikkal†, Gangavarapu Guru Kumar‡,

Kumaravel Sundaramoorthy§ and Ashok Sankar¶
by UNIVERSITY OF NEW ENGLAND on 01/15/18. For personal use only.
J CIRCUIT SYST COMP Downloaded from www.worldscientific.com
Department of Electrical Engineering,

National Institute of Technology Calicut,
Calicut, Kerala 673601, India
†sivanuday@gmail.com
‡
gurukumar537@gmail.com
§
kumaravel _s@nitc.ac.in
¶
ashoks@nitc.ac.in
Received 24 May 2017

Accepted 27 November 2017
Published 12 January 2018
Renewable energy sources and storage devices are combined as a hybrid energy system to
provide reliable electricity to the load. Naturally, such sources have distinct voltage–current
characteristics. In this paper, a dual input positive output voltage DC–DC converter is used as
power electronic interface for integration of the above nature of sources. Di®erent modes of
operation of the above converter such as buck, boost and buck–boost are discussed with nec-
essary circuit and equations. A detailed current and voltage stress analysis of various switching
devices available in the converter is also discussed. This analysis helps to select the switching
devices in an optimized and cost-e®ective manner. The e®ect of equivalent series resistance of
such storage elements on the output voltage is investigated in detail. The MATLAB simulation
of the power converter is carried out, and a prototype of the converter is also fabricated. A
power control strategy is proposed for the power converter with the objective of voltage regu-
lation during the load side and source side disturbances. Di®erent experimental analyses of the
fabricated converter in the laboratory environment have been conducted, and the test results
are presented in this paper.
Keywords: Hybrid energy system; positive dual input DC–DC converter; multi-input DC–DC
converters.
1. Introduction
The dependence on energy sources based on fossil fuel is signi¯cantly falling because
of their shortage and the environmental pollution raised by them. Substitution of
*This paper was recommended by Regional Editor Piero Malcovati.

†Corresponding author.
1850159-1
A. Sivaprasad et al.
such fossil fuel-based energy resources with the nonconventional energy sources is the
one of the potential solutions to the above problem. But the use of standalone re-
newable energy sources such as wind, micro-hydro, solar-PV, etc. is not suggested for
the consistent electricity production because their availability is entirely dependent on
unstable climatic circumstances. Hence, to attain a dependable and clean electricity
generation, the hybridization of nonconventional and renewable energy is necessary.
The hybrid energy system (HES) is a hopeful methodology that shall contain
various renewable energy sources which have distinct or same voltage–current
characteristics to satisfy the changeable urban and rural electricity demands. For the
integration of these energy sources, a power electronic converter interface is com-
pulsory.1,2 Conventionally, single input DC–DC converters which are connected in
parallel are generally used in the hybridization of various input energy sources. But
the cost and complexity associated with these methods are high and their e±ciency is
below par. This has made the power electronic researchers to think about an alter-
native solution to this problem. So, the concept of multi-input DC–DC converters
(MIDCs) is established for the HES integration.
Lower system complexity, simple construction and control, lower cost and good
system reliability are the major merits of MIDCs.3,4 Thus, MIDCs can be an e±cient
replacement for multiple single input DC–DC converters in several applications such
as nonconventional energy source integration, electric vehicle (EV), etc. Di®erent
kinds of MIDCs including nonisolated and isolated MIDCs are already presented in
the literature. A generalized and systematic approach to the development of MIDCs
is presented.5–7 A multi-input DC–DC converter8 working on a buck–boost operation
is discussed. Even though the presented topology is having less number of part
counts, the polarity of the output voltage is negative. The additional arrangements
such as a transformer are required to make the output voltage positive, which may
result in a further drop in the overall e±ciency of the converter.
A dual input DC–DC converter for interfacing the DC sources with the bidirec-
tional power transfer capability is proposed in Ref. 9. However, the major drawback
of the converter is that the system e±ciency is less due to the power losses caused by
the reverse recovery currents of output diodes. Di®erent MIDC topologies for the
integration of renewable energy (wind, solar-PV, etc.) and hybrid EV are reported in
Refs. 9–16. In Ref. 17, the analysis of isolated multi-port bidirectional converter
topology is described. The existence of a transformer for providing the magnetic
coupling results in a bulky size and complex structure.
A large step-up DC–DC converter in the application of solar PV is presented in
Refs. 18 and 19. The switches of the converter topology have less voltage stress, but
for n-input sources, n power switches and inductors are required that makes the
system expensive and complex. The concept of novel multi-input DC–DC converter
for the EV application is discussed in Ref. 20. The major feature of this topology is
the ability for active power sharing among the connected energy storage devices.
In Ref. 21, a multi-input voltage step-up converter topology is presented.
1850159-2
Performance Analysis of a Dual Input DC–DC Converter
The function of the converter relies on the capacitor cells, which are presented in the
input side of the converter. But the number of switches and capacitors will be n for
n-input, which increases the overall system complexity.
In this paper, a dual input positive output voltage DC–DC (DIPDC) converter
topology is introduced for HES integration. The converter can integrate two diverse
energy sources which have similar or dissimilar V –I characteristics. Since the con-
verter has a lower part count and compact structure, the e±ciency of the DIPDC
converter is high in comparison with the other MIDCs detailed in the literature.
2. Dual Input Positive Output Voltage DC–DC Converter

Figure 1 shows the circuit diagram of the DIPDC converter. Two di®erent energy
sources have been opted for the detailed study of the DIPDC converter. The DIPDC
converter circuit consists of two input energy sources, an inductor, a capacitor, three
controller switches (SW1 –SW3 ), and diodes (D1, D2, Da and Db ), which are connected
in parallel with a load. Here, the diodes Da and Db are used to block the large current
°ow due to the voltage di®erence between the input sources. The power delivery from
the input sources and the working states is decided by the switches SW1 and SW2 ,
whereas the operating types (buck, boost, and buck–boost) of the DIPDC converter
are determined by the conduction of the diodes and switch SW3 . Based on the control
of SW1 , SW2 , and SW3 , the probable working states under buck–boost operation of the
converter have been described in Fig. 2, and the brief description of working states
has been depicted in Table 1.
State 1: For state 1 operation of the converter, the equivalent circuit is shown in
Fig. 2(a). The switching pulses are given in such a way that the switches SW1 and SW3
conduct while the remaining power switches are in OFF condition. So, in this state
source V1 charges the inductor for the period d1 T .
State 2: Figure 2(b) shows the state 2 operation of the DIPDC converter. Here, the
conducting switches are SW2 and SW3 and the other switches are in nonconducting
state. In this condition, source V2 charges the inductor for the period d2 T .
Fig. 1. Circuit diagram of the DIPDC converter.
1850159-3
(a) (b)
(c)
Fig. 2. Working states of DIPDC converter (buck–boost): (a) when the source 1 is connected; (b) when
the source 2 is connected and (c) freewheeling of load current.
Table 1. Various working modes of DIPDC converter (buck–boost operation).
Working state Supplying source ON switches VL Inductor status

State-1 V1 SW1 , SW3 V1 Charging
State-3 None D1 , D2 V0 Discharging
Note: VL , inductor voltage.
State 3: For this state, the circuit representation of the converter is illustrated in
Fig. 2(c). Here, all other switches are in OFF state except the diodes. So, the sources
V1 and V2 are detached from the converter and the stored energy in the inductor is
transferred to the load resistance through diode D1 and D2.
Figures 3 and 4 show the working states of the DIPDC converter under buck and
boost operations. The detailed explanation of the DIPDC converter under buck and
boost operations is illustrated in Tables 2 and 3, respectively. In buck operation,
initially, the switch SW1 and the diode D2 are turned ON, whereas the other switches
are in the OFF state so that source V1 simultaneously supplies the load and charges
the inductor. Next, while all other switches are in OFF state, the switch SW2 is
turned ON and diode D2 remains in forward biased condition. During this state,
source V2 simultaneously supplies the load and charges the inductor. Finally, in the
freewheeling period, all the switches, except diodes D1 and D2, are in OFF state,
1850159-4
(a) (b)
(c)
Fig. 3. Working states of DIPDC converter: (a) when source 1 is connected; (b) when source 2 is
connected and (c) freewheeling of load current (buck mode of operation).
(a) (b)
(c)
Fig. 4. Working states of DIPDC converter: (a) when source 1 is connected; (b) when source 2 is
connected and (c) source 2 charges the inductor and simultaneously supplying the load (boost operation).
1850159-5
Table 2. Di®erent working modes of DIPDC converter (buck operation).

State-1 V1 SW1 , D2 V1 V0 Charging
State-3 None D1 , D2 V0 Discharging
Table 3. Di®erent working modes of DIPDC converter (boost operation).


so that the stored energy in the inductor is dissipated to the load through diodes
D1 and D2.
But, during the boost operation, di®erent switching patterns have been adopted
to ensure the active participation to deliver power to the load from both energy
sources V1 and V2 . Initially, the switches SW1 and SW3 are turned ON, and all other
switches are in nonconducting state. Hence, the source V1 charges the inductor. In
the second stage, the switch SW1 is turned OFF, and the switch SW2 is turned ON
while keeping the switch SW3 in ON condition. Finally, the switch SW3 is turned
OFF, whereas switch SW2 remains in conducting state. Here, the diode D2 becomes
forward biased, and the source V2 charges the inductor and the capacitor, and
supplies the load individually.
2.1. Performance analysis of the converter with buck–boost operation

The performance analysis of the converter in the unidirectional mode with buck–
boost operation is conducted for continuous conduction mode (CCM). The varia-
tions in inductor current and voltage due to the transition of operating states have
been presented, as shown in Fig. 5. The three di®erent working states of the DIPDC
converter in buck–boost operation are discussed below.
State 1: When the switch SW1 is turned ON, the inductor is charged by the input
source V1 . As a result, the inductor current increases linearly from the initial value of
the current i.e., ILð0Þ . The expression of the inductor current is given in Eq. (1):
Z
1 d1 T
IL ¼ ILð0Þ þ VL dt ; ð1Þ
L 0
where VL is the voltage across the inductor. By applying KVL to the loop consisting
of voltage source V1 , switch SW1 , inductor L and switch SW3 ,
VL ¼ V1 ; ð2Þ
1850159-6
Fig. 5. Key waveforms of pulse of SW1 and SW2 , inductor voltage and inductor current for buck–boost
operation.
1
IL ¼ ILð0Þ þ ðV Þd T : ð3Þ
L 1 1
State 2: Here, when the switch SW2 is turned ON, the inductor is charged by the input
source V2 . Since V1 V2 , the slope of the inductor current is lower than the previous
interval. The inductor current value in this state is depicted as given in Eq. (4):
Z ðd1 þd2 ÞT
1
IL ¼ ILð1Þ þ VL dt : ð4Þ
L d1 T
After applying KVL,

1
IL ¼ ILð1Þ þ ðV Þd T : ð5Þ
L 2 2
State 3: Here, the energy stored in the inductor is transferred to the load through
diodes. Hence, the inductor current is derived as follows:
Z
1 T
IL ¼ ILð2Þ þ V dt : ð6Þ
L ðd1 þd2 ÞT L
1850159-7
In this case, VL ¼ V0 ; so Eq. (6) becomes

1
IL ¼ ILð2Þ V ½T ð1 ðd1 þ d2 ÞÞ : ð7Þ
L 0
Here the duty ratios d1 and d2 are corresponding to the switches SW1 and SW2 . Since
there is a negative voltage across the inductor (i.e., V0 < 0), the inductor current
decreases from its previous value (i.e., ILð2Þ ).
As per the volt-second balance equation, the average value of inductor voltage is
zero under steady state condition:
V1 d1 þ V2 d2 V0 ð1 d1 d2 Þ ¼ 0 : ð8Þ
By solving the above equation, the output voltage of the DIPDC converter under
buck–boost mode of operation is:
V1 d1 þ V2 d2
V0 ¼ : ð9Þ
ð1 d1 d2 Þ
By neglecting the losses, input power will be equal to output power
Vi Ii ¼ VIo ; ð10Þ
V 1 I1 þ V 2 I2 ¼ V o Io : ð11Þ
From Eq. (11), Io will be

V 1 I1 þ V 2 I2
Io ¼ : ð12Þ
Vo
By substituting Vo from Eq. (9), Eq. (12) becomes

ðV1 I1 þ V2 I2 Þð1 d1 d2 Þ
Io ¼ : ð13Þ
V1 d1 þ V2 d2
The source current average values (I1 and I2 ) can be expressed in terms of IL as
given below:
I1 ¼ d 1 IL ; I2 ¼ d 2 IL :
So, after substituting I1 and I2 expressions in Eq. (13), Io becomes
ðV1 d1 IL þ V2 d2 IL Þð1 d1 d2 Þ
Io ¼ : ð14Þ
V1 d1 þ V2 d2
After solving Eq. (14), Io ¼ IL ð1 d1 d2 Þ; so, IL is

Io
IL ¼ ð15Þ
ð1 d1 d2 Þ
1850159-8
hence
Io Io
I 1 ¼ d 1 IL ¼ d 1 and I2 ¼ d2 IL ¼ d2 :
ð1 d1 d2 Þ ð1 d1 d2 Þ
Therefore
I1 d 1
¼ : ð16Þ
I2 d 2
2.2. Current and voltage stress analysis of the conducting devices

The e±cient and cost-e®ective operation of MIDCs is heavily dependent on the
appropriate selection of the conducting devices (power diodes and switches) available
in the circuit. So, the voltage and current stress analyses of the switching devices
need to be performed for the optimized selection of the switches. Here, source vol-
tages are the maximum value of the voltage across the switches SW1 and SW2 . The
selection of the diodes D1 and D2 and switch SW3 have been conducted based on the
analysis of the current and voltage stress of switches. The value of the voltage stress
of the switches shall be derived as given in Eq. (17):
VstressSWN ¼ VN ; ð17Þ
where VN is general expression for the maximum value of peak voltage across the
switch.
The current stress analysis of the switching devices shall be conducted based on
the working states of the converter. The values of current stress of the switching
devices under buck–boost mode of operation are derived in the following equations:

IL for d1 TS ;
Current through switch SW1 ðISW1 Þ ¼ ð18Þ
0 for ð1 d1 ÞTS ;

IL for d2 TS ;
Current through switch SW2 ðISW2 Þ ¼ ð19Þ
0 for ð1 d2 ÞTS :
The diode currents are given as

IL for ½1 ðd1 þ d2 ÞTS ;
ID1 ¼ ID2 ¼ ð20Þ
0 for ½d1 þ d2 TS :
Hence, the current stress of the switching devices shall be derived as follows:
ðV1 Þd1
ISW1 STRESS ¼ IL þ ð21Þ
Lf
and,
ðV2 Þd2
ISW2 STRESS ¼ IL þ : ð22Þ
Lf
1850159-9
Current stress of the diodes D1 and D2 is
V0 ð1 ðd1 þ d2 ÞÞ
ID1 ¼ ID2 ¼ IL : ð23Þ
Lf
From the current stress analysis, it can be observed that the source voltages have
high impact on the current stress of the power switches of the input sources, whereas
the magnitude of the output voltage decides the current stress of the diodes. So, it is
easy to choose the power switches and diodes required in an optimized and cost-
e®ective manner based on the analysis of the current and voltage stress of the
switching devices.
2.3. Concept of power sharing in DIPDC converter

Based on the output voltage expression in Eq. (9), di®erent combinations of duty
ratios d1 and d2 are possible to achieve a regulated output voltage Vo from the input
voltages. The required output voltage of the converter is generated for the various
combinations of the duty ratios. The following equation shows the amount of power
derived from the input energy sources:

P 1 ¼ V 1 I1 ¼ V 1 d 1 IL
: ð24Þ
P 2 ¼ V 2 I2 ¼ V 2 d 2 IL
By substituting IL from Eq. (15) into Eq. (24), the powers supplied from the input
sources are given as
8
>
> ¼
I0
¼
V0
> 1
< P V d
1 1 V d
1 1
ð1 d1 d2 Þ Rð1 d1 d2 Þ
> : ð25Þ
>
> I0 V0
:P2 ¼ V2 d2 ¼ V 2 d2
ð1 d1 d2 Þ Rð1 d1 d2 Þ
By substituting V0 , which is expressed in Eq. (9), into Eq. (25) and after simpli¯-
cation, the power supplied by the input sources is derived as:
8
> V 12 d 21 þ ðV1 V2 Þd1 d2
>
> P ¼
< 1
Rð1 d1 d2 Þ 2
: ð26Þ
>
> V 2 d 2 þ ðV1 V2 Þd1 d2
>
:P2 ¼ 2 2
Rð1 d1 d2 Þ 2
The expression of the output power of the converter obtained from the input sources
is shown as:
P O ¼ P1 þ P2 : ð27Þ
1850159-10
After substituting P1 and P2 from Eq. (26) in Eq. (27) and oversimpli¯cation, the
output power of the converter is obtained as:
ðV1 d1 þ V2 d2 Þ 2
PO ¼ : ð28Þ
Rð1 d1 d2 Þ 2
Since
V1 d1 þ V2 d2
V0 ¼ ;
ð1 d1 d2 Þ
Eq. (28) can be rewritten as:

V O2
PO ¼ : ð29Þ
R
From the above analysis, it is noted that the load voltage and output power of the
converter are independent of speci¯c duty ratio values. So, the power sharing be-
tween the input energy sources can be controlled by the appropriate tuning of the
duty ratios.
2.4. E®ect of equivalent series resistance (ESR) in the voltage gain

The storage elements such as inductance and capacitance present in the converter
are not ideal. So, a series resistance is added with the inductor and capacitor as a
practical system. This series resistance considered for the capacitor and inductor is
called ESR. Figure 6 shows the circuit diagram of the DIPDC converter with the
ESR. During the period [ðd1 þ d2 ÞT ], the switch SW3 is in condition state. So, the
duty ratio of SW3 is considered as dm ¼ d1 þ d2 .
The volt-second balance expression of the converter given in Eq. (8) shall be
modi¯ed as given in Eq. (30):
Vin dm V0 ð1 dm Þ ¼ 0 ; ð30Þ
Fig. 6. Circuit diagram of the DPIDC converter with the ESR of storage elements.
1850159-11
where Vin dm ¼ V1 d1 þ V2 d2 . Hence, the voltage gain expression of the DIPDC con-
verter is shown below:
V0 dm
¼ : ð31Þ
Vin ð1 dm Þ
The average input voltage of the DIPDC converter in the buck–boost operation is
expressed in the general form as given below:
X
n
Vin dm ¼ Vj dj : ð32Þ
j¼1
Thus, the output voltage V0 after substituting Vin in Eq. (32) is given as:
X
n
1
V0 ¼ Vj dj ; ð33Þ
j¼1
ð1 dm Þ
where n is the number of input voltage sources, and in this work, the value of n is
taken as 2.
(a) Voltage gain of the DIPDC converter with respect to the inductor ESR
The voltage gain of the DIPDC converter is signi¯cantly in°uenced by the in-
ductor ESR. Under the buck–boost operation of the converter, the inductor voltage
with ESR of the inductor is given below:
8
<VL ¼ V1 IL rL esr
> for d1
VL ¼ V2 IL rL esr for d2 ; ð34Þ
>
:
VL ¼ V0 IL rL esr for ð1 d1 d2 Þ
where rL esr is the inductor ESR.

So, the volt-second balance expression of the converter with the inductor ESR is
given below:
dm ðVin IL rL esr Þ þ ð1 dm ÞðV0 IL rL esr Þ ¼ 0: ð35Þ
The average input voltage of the converter is obtained as given in Eq. (36):
V0 ð1 dm Þ þ IL rL esr
Vin ¼ : ð36Þ
ðdm Þ
By substituting the inductor current, IL which is given in Eq. (15), into Eq. (36), the
average input voltage of the converter is obtained as:
I0
V0 ð1 dm Þ þ r
ð1 dm Þ L esr
Vin ¼ : ð37Þ
ðdm Þ
In Eq. (15), let d1 þ d2 ¼ dm .
1850159-12
But, I0 ¼ V0 =R, so Eq. (37) is rewritten as:

1 V0
V0 ð1 dm Þ þ r
ð1 dm Þ R L esr
Vin ¼ : ð38Þ
ðdm Þ
The expression of Vin is obtained as given below:
V0 ½ð1 dm Þ 2 R þ rL esr
Vin ¼ : ð39Þ
Rð1 dm Þðdm Þ
Finally, from Eq. (39), the voltage gain of the DIPDC converter by taking into
account the ESR of the inductor is expressed as:
V0 Rð1 dm Þðdm Þ
¼ : ð40Þ
Vin ð1 dm Þ 2 R þ rL esr
From the voltage gain of the converter which are expressed in Eqs. (31) and (40), it
can be observed that the ESR value of the inductor reduces the voltage gain of the
DIPDC converter signi¯cantly. By substituting the general expression of Vin from
Eq. (32) in Eq. (40), the output voltage V0 is given as:
" #
Rð1 dm Þ X
n
V0 ¼ Vd : ð41Þ
ð1 dm Þ 2 R þ rL esr j¼1 j j
(b) Voltage gain of the DIPDC converter with respect to the capacitor ESR
Similar to the ESR of the inductor, the capacitor ESR also has certain e®ects on
the voltage gain of the converter. The expression of voltage across the inductor after
incorporating the ESR of the capacitor is shown below:

VL ¼ Vin for dm
: ð42Þ
VL ¼ V0 ðIL I0 ÞrC esr for ð1 dm Þ
The volt-second balance expression of the converter with the ESR of the capacitor is
given below:
dm ðVin Þ þ ð1 dm ÞðV0 ðIL I0 ÞrC esr Þ ¼ 0; ð43Þ
where rC esr is the capacitor ESR. By simplifying Eq. (43), the input voltage of the
converter is shown below:
ð1 dm Þ½V0 þ ðIL I0 ÞrC esr
Vin ¼ : ð44Þ
ðdm Þ
By substituting the value of inductor current in Eq. (44), the expression of the input
voltage of the converter is given as:
V0 ½ð1 dm ÞR þ dm rC esr
Vin ¼ : ð45Þ
Rðdm Þ
1850159-13
Finally, the voltage gain of the DIPDC converter after incorporating the capacitor
ESR is extracted as follows:
V0 Rðdm Þ
¼ : ð46Þ
Vin ð1 dm ÞR þ dm rC esr
From the voltage gain of the converter which is expressed in Eqs. (31) and (46), it can
be observed that the capacitor ESR reduces the voltage gain of the DIPDC converter
signi¯cantly. By substituting the general expression of Vin in Eq. (46), the output
voltage V0 is given as:
R X
n
V0 ¼ Vj dj : ð47Þ
ð1 dm ÞR þ dm rC
esr j¼1
2.5. Development of a power control strategy

An MIDC should be capable of extracting various amounts of power from the con-
nected input energy sources while keeping the regulated output voltage across the
load. Hence, a suitable power control strategy is necessary to nullify the issues as-
sociated with the power management of the MIDC. The input energy sources have
di®erent steady state and dynamic responses during the operation of the converter.
So, a power control algorithm that considers the dynamic and steady state char-
acteristics of each input source would be a superior selection for MIDC. Figure 7
shows the overall block diagram of a power control strategy of the DIPDC converter.
Here, the concept of conventional average current mode control which includes
either source side or load side control is considered in the development of the power
control strategy. There are some issues linked with load side control. Here monitoring
Fig. 7. Schematic representation of the power control strategy of the DIPDC converter.
1850159-14
of the inductor current is carried out to get a regulated voltage at the load side. But
in the source side control, the individual source currents are monitored to control the
inductor current indirectly. In the load side control, the sensor requirements are less;
however, the dynamic response of the converter is poor. The source side control o®ers
good steady state and dynamic response. Hence, this control method is well suited for
the e±cient utilization of the input energy source and the same is implemented in
this work.
Here, the voltage error obtained by comparing the output voltage with the ref-
erence voltage is given as input to a voltage controller (VC). The output of VC is
main reference current to calculate the value of individual reference currents of the
input sources based on the scaling factors P1 and P2 . The values of the scaling factors
can be varied between 0 and 1 (i.e., P1 2 ½0; 1, P2 2 ½0; 1).

Finally, the Pulse width Modulation (PWM) pulses for DIPDC converter are
generated by a current controller based on error obtained from the comparison
between the actual source currents and the individual reference currents. Here, the
power extracted from individual sources is dissimilar, as the reference current value
of each source is di®erent. The variation in speci¯c source current from minimum to
maximum value shall be indicated by the variation in the respective scaling factors. If
one of the scaling factors (either P1 or P2 ) is set as 1, the maximum possible current is
supplied from the corresponding input source to regulate the output voltage. Hence,
the duty ratios of the switching devices available in the DIPDC converter shall be
easily controlled using the proposed control strategy, so that a well-regulated output
voltage shall be realized under source side and load side disturbances.
3. Simulation Results of the DIPDC Converter

The software simulation of the DIPDC converter has been carried out in the
MATLAB/Simulink using the power system block sets. Di®erent parameters of
DIPDC converter used in the simulation of the converter are given in Table 4. The
simulation waveforms of DIPDC converter for all the three possible operations
(buck, boost and buck–boost) are depicted in Figs. 8 and 9. Figures 8(a) and 8(b)
show the simulation waveforms of the DIPDC converter in buck operation. The
¯gure shows that for duty cycle d1 , the inductor is charged by a voltage of 42 V (i.e.,
V1 V0 ) and then for duty cycle d2 , it is charged by a voltage of 22 V (i.e., V2 V0 ).
For the remaining period, it is discharged with a voltage of 48 V (i.e., V0 ). Sim-
ilarly, the boost operation of the converter is depicted in Figs. 8(c) and 8(d).
Table 4. Parameters of DPIDC converter used in the simulation.
Output voltage (V)

Source 1 Source 2 Capacitor Inductor Switching
(V) (V) (F) (mH) frequency (kHz) Buck Boost Buck–boost
90 70 470 5 20 48 120 50/78/120
1850159-15
(a) (b)
(c) (d)
Fig. 8. Output waveforms of DIPDC converter obtained from the simulation: (a) inductor current and
output current; (b) inductor voltage and output voltage for buck operation [V1 ¼ 90 V, V2 ¼ 70 V,
d1 ¼ 0:24, d2 ¼ 0:36]; (c) inductor current and output current and (d) inductor voltage and output voltage
for boost operation [V1 ¼ 90 V, V2 ¼ 70 V, d1 ¼ 0:30, d2 ¼ 0:70].
Simulation results of the DIPDC converter in buck–boost operation with duty

ratio (d1 þ d2 ) less than 0.5, equal to 0.5 and greater than 0.5 are shown in Figs. 9(a)–
9(f), respectively. In all the three cases, the inductor is charged from source 1 (i.e.,
90 V) and source 2 (i.e., 70 V) for the duty cycles of d1 and d2 , respectively. However,
(a) (b)
Fig. 9. Output waveforms of the DIPDC converter in buck–boost operation: (a) inductor current and
output current; (b) inductor voltage and output voltage for duty ratio (d1 þ d2 ) less than 0.5; (c) inductor
current and output current; (d) inductor voltage and output voltage for duty ratio (d1 þ d2 ) equal to 0.5;
(e) inductor current and output current and (f) inductor voltage and output voltage for duty ratio
(d1 þ d2 ) greater than 0.5.
1850159-16
(c) (d)
(e) (f)
Fig. 9. (Continued )
it is discharged with the voltages of 50, 78 and 120 V, respectively, for the duty ratio
(d1 þ d2 ) less than 0.5, equal to 0.5 and greater than 0.5. The charging and dis-
charging of the inductor can be noticed from Figs. 8 and 9. So, the inductor and
output currents can be controlled by tuning the duty cycles d1 and d2 .
4. Experimental Results of the DIPDC Converter

The performance analysis of the converter has been veri¯ed on the experimental
prototype of the converter in the laboratory environment. Figure 10 shows the ex-
perimental setup of the DIPDC converter. The two input sources with the voltage
levels, respectively, 90 and 70 V are considered to test the prototype of the converter.
A dSPACE 1104 digital controller is used for generating the PWM pulses and in-
terfacing with the hardware prototype in real time. The switching frequency of
20 kHz is considered for the generation of gate pulses for all the three switches. The
power switches of FGH40N120AN IGBT and MUR 860 fast recovery diodes are used
in the DIPDC converter.
The experimental analysis of the DIPDC converter under steady state condition
has been conducted for CCM of the inductor. The testing of the DIPDC converter is
carried out in buck, boost and buck–boost modes. The output waveforms from the
various parts of the converter are observed during the experimentation using a
1850159-17
Fig. 10. Prototype of the DIPDC converter with dSPACE 1104 real-time controller.
digital storage oscilloscope, and Fig. 11 shows the observed waveforms. Figure 11(a)
shows that the converter produces an output voltage of 48 V for the buck operation.
Figure 11(b) shows 50 V for buck–boost operation with the duty ratio less than 0.5.
Similarly, Fig. 11(c) shows 78 V for buck–boost operation with the duty ratio equal
to 0.5, and Fig. 11(d) shows 120 V for buck–boost operation with the duty ratio >0.5.
Figure 11(e) shows 120 V for the boost operation. The output waveforms obtained
from the experiment of the DIPDC converter closely match with the simulation
results.
A transient analysis of the DIPDC converter is carried out to observe the dynamic
behavior of the converter under source side and load side disturbances. Figure 12
shows the output current and voltage waveforms of the converter for the disturbance
in source and load values. From Fig. 12(a), it can be seen that the output voltage is
regulated at the required value of 120 V under a step change in the load current from
0.4 to 1.2 A. Likewise, the output voltage of the converter is maintained at 120 V
when the load current decreases from 1.2 to 0.4 A.
Figure 12(b) shows the output waveform of the converter during the source side
disturbance. It can be observed from the ¯gure that for a short duration of time the
DIPDC converter is operated with two sources. All of a sudden, the magnitude of the
source 1 voltage is dropped to zero from 90 V and back to 90 V after a short duration
of time. In both the cases, the converter regulates the output voltage with a small
variation. Hence, the transient analysis of the converter shows the e±cient operation
of the designed controller in the experimental platform.
Under di®erent load conditions, the e±ciency of the DIPDC converter is calcu-
lated. The values of e±ciency according to the changes in output power of the
1850159-18
(a) (b)
(c) (d)
(e)
Fig. 11. Output waveforms obtained from the experiment of the DIPDC converter: (a) buck, (b) buck–
boost (duty ratio < 0.5), (c) buck–boost (duty ratio ¼ 0.5), (d) buck–boost (duty ratio > 0.5), (e) boost
(CH1: inductor voltage, CH2: output voltage, CH3: inductor current, CH4: output current). [(a–e):
CH1 ¼ 50 V/div, CH2 ¼ 50 V/div, CH4 ¼ 1 A/div]; [(a) CH3 ¼ 1 A/div, (b and c) CH3 ¼ 2 A/div, (d and
e) CH3 ¼ 5 A/div].
1850159-19
(a) (b)
Fig. 12. The output voltage and load current waveforms of the converter obtained from the experiment:
(a) under load variation and (b) under source variation [CH1 ¼ 50 V/div, CH2 ¼ 1 A/div, 250 ms].
DIPDC converter in all the three modes of operation are shown in Fig. 13. From
Fig. 13, it can be concluded that the DIPDC converter has competitive e±ciency in
all the three modes of operation. The e±ciency pro¯le of the DIPDC converter shall
be improved more by considering the optimum design of the components of the
DIPDC converter. The performance comparison of the DPIDC converter has been
(a) (b)
(c)
Fig. 13. E±ciency versus output power of the DIPDC converter: (a) buck, (b) boost and (c) buck–boost.
1850159-20
Table 5. Comparison of di®erent MIDCs.
Number of Capacitor Inductor Voltage Operating E±ciency

Topology proposed switches (C) (L) stress (V ) modes (%)
Converter in Ref. 2 2N 1 N Vo BD, B 78–88
Converter in Ref. 3 N þ4 1 1 VN BD, b,b-B,B 81–89
Converter in Ref. 8 N þ1 1 1 VN VN1 UD, b-B 80–90
DIPDC converter N þ1 1 1 VN BD, b,b-B,B 86–93
Note: UD, unidirectional; BD, bidirectional; B, boost; b-B, buck-Boost; b, buck.
carried out with other MICs based on the parameters such as e±ciency, total com-
ponent count and voltage stress of the converter and is given in Table 5. From
Table 5, it can be observed that the e±ciency of the DIPDC converter is compara-
tively good when compared with the other converters reported in the literature.
5. Conclusion
A dual input positive output voltage DC–DC converter topology is presented for the
integration of two energy sources in this paper. The analysis of the DIPDC converter
has been carried out for all the three possible operations such as buck, buck–boost
and boost in a detailed manner. The current and voltage stress analysis of the
switching devices available in the converter is carried out to ensure the proper se-
lection of the switching devices. The impact of the inductor and capacitor ESRs on
the voltage gain of the converter is analyzed. The analysis proves that the ESR has a
signi¯cant e®ect on the ouput voltage gain of the converter. The concept of power
sharing among the input energy sources is introduced for the DIPDC converter. A
power control strategy for the DIPDC converter is designed to achieve good steady
state and dynamic response. The performance analysis of the converter is conducted
in the experimental platform to check the opertation of the converter under the load
and source side variation. From the experimental results, it is found that the
designed controller gives satisfactory performance. The e±ciency analysis of the
converter in all the three types of operation has been carried out, and the results are
presented to validate the better performance of the DIPDC converter.
Detailed analysis of the converter in all three modes of operation, current and
voltage stress analysis, e®ect of ESR on the voltage gain, concept of power sharing,
power control strategy for the voltage regulation during load side and source side
perturbations are the signi¯cant contributions of this work.
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Performance Analysis of A Positive Output Voltage Dual

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Performance Analysis of A Positive Output Voltage Dual

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Journal of Circuits, Systems, and Computers

Vol. 27, No. 10 (2018) 1850159 (22 pages)

Performance Analysis of a Positive Output Voltage Dual

Sivaprasad Athikkal†, Gangavarapu Guru Kumar‡,

Department of Electrical Engineering,

Received 24 May 2017

*This paper was recommended by Regional Editor Piero Malcovati.

2. Dual Input Positive Output Voltage DC–DC Converter

Fig. 1. Circuit diagram of the DIPDC converter.

Table 1. Various working modes of DIPDC converter (buck–boost operation).

Working state Supplying source ON switches VL Inductor status

Table 2. Di®erent working modes of DIPDC converter (buck operation).

Working state Supplying source ON switches VL Inductor status

Table 3. Di®erent working modes of DIPDC converter (boost operation).

Working state Supplying source ON switches VL Inductor status

State-3 V2 SW2 , D2 V2 V0 Charging

2.1. Performance analysis of the converter with buck–boost operation

After applying KVL,

In this case, VL ¼ V0 ; so Eq. (6) becomes

By neglecting the losses, input power will be equal to output power

From Eq. (11), Io will be

By substituting Vo from Eq. (9), Eq. (12) becomes

After solving Eq. (14), Io ¼ IL ð1 d1 d2 Þ; so, IL is

2.2. Current and voltage stress analysis of the conducting devices

Current stress of the diodes D1 and D2 is

2.3. Concept of power sharing in DIPDC converter

Eq. (28) can be rewritten as:

2.4. E®ect of equivalent series resistance (ESR) in the voltage gain

where rL esr is the inductor ESR.

In Eq. (15), let d1 þ d2 ¼ dm .

But, I0 ¼ V0 =R, so Eq. (37) is rewritten as:

2.5. Development of a power control strategy

can be varied between 0 and 1 (i.e., P1 2 ½0; 1, P2 2 ½0; 1).

3. Simulation Results of the DIPDC Converter

Table 4. Parameters of DPIDC converter used in the simulation.

Output voltage (V)

Simulation results of the DIPDC converter in buck–boost operation with duty

4. Experimental Results of the DIPDC Converter

Table 5. Comparison of di®erent MIDCs.

Number of Capacitor Inductor Voltage Operating E±ciency

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