EE-222 Microprocessor Systems: DE-41 (EE) Syn C

EE-222 Microprocessor Systems
DE-41(EE) Syn C
Instructor - Lec Aamir Javed
Course Intro + Introduction to Microprocessors
EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

1
Javed
Introduction
• This courses introduces students to microprocessors, microcontrollers
and embedded systems based on them
• Basic architecture of microprocessors will be introduced
• Concepts such as RAM/ROM, ALU etc will be discussed
• Detailed architecture and programming of microcontrollers will be
introduced
• We will study how to program and use various peripherals like timers, ADC,
UART etc
• We will learn how to interface different kinds of devices with microcontrollers
• Students will learn how to design embedded systems using microcontrollers

2
Javed
Textbook
➢ PIC Microcontroller and Embedded Systems, Muhammad Ali Mazidi
➢ The 80x86 IBM PC and Compatible Computers, Muhammad Ali Mazidi
EE-222 Microprocessor Systems (Spring 2021) -

3
Lec Aamir Javed
Outline
Topic
Introduction to microprocessors, including CPU, ALU, program counter, buses, memories and peripherals
Introduction to 8088/86 buses, memory interfacing, address decoding
Introduction to microcontrollers. Microprocessor vs microcontroller architecture, microcontroller vendors,
microchip families, MPLAB IDE, Proteus
Branch, call and delay programming
Microcontroller input/output ports programming
Arithmetic in assembly language
Microcontroller addressing modes
Microcontroller programming in C
Microcontroller Timers/counters programming
Microcontroller Serial Communication programming(RS232)
Interrupts Programming
CCP and ECCP programming
Serial Communication (SPI, I2C)
Microcontroller ADC programming
Electromechanical systems Control : PWM, DC, stepper motors, DC motor, relays.
4
EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir Javed
Basic Concepts (Covered in DLD)
➢ Read Section 0.1 of “The 80x86 IBM PC and Compatible Computers,
Muhammad Ali Mazidi”

5
Javed
Decimal Numbers
• A Decimal Number can be represented by n decimal digits
• Each digit is allowed to take on one of the ten possible values i.e.
0,1,…9.
• 𝐷 = 𝑑𝑛−1 𝑑𝑛−2 … 𝑑1 𝑑0
• Example: 4578 (n = 4)
𝑑3 𝑑2 𝑑1 𝑑0
Value 4 5 7 8
Weight 103 = 1000 102 = 100 101 = 10 100 = 1
6
Decimal Numbers
• Example: 4578 (n = 4)
𝑑3 𝑑2 𝑑1 𝑑0
Value 4 5 7 8
Weight 103 = 1000 102 = 100 101 = 10 100 = 1
• Value:
𝑛−1
𝑉 𝐷 = 𝑑𝑛−1 × 10𝑛−1 + 𝑑𝑛−2 × 10𝑛−2 + ⋯ +𝑑1 × 10 + 𝑑0 = ෍ 𝑑𝑖 × 10𝑖

𝑖=0
• 𝑉 𝐷 = 4 × 103 + 5 × 102 + 7 × 101 + 8 × 100 = 4578
• This is referred to as the positional number representation
7
Binary Numbers
• A Binary Number can be represented by n binary digits (called bits)
• Each bit is allowed to take on only two possible values i.e. 0 and 1.
• 𝐵 = 𝑏𝑛−1 𝑏𝑛−2 … 𝑏1 𝑏0
• Left-most bit (𝑏𝑛−1 ) is known as the most-significant bit (MSB)

• Right-most bit (𝑏0 ) is known as the least-significant bit (LSB)
• A group of four bits is called a nibble. A group of eight bits is called a
byte.
8
Binary Numbers
• Example: 1011 (n = 4)
𝑏3 𝑏2 𝑏1 𝑏0
Value 1 0 1 1
Weight 23 = 8 22 = 4 21 = 2 20 = 1
• Value:
𝑛−1
𝑉 𝐵 = 𝑏𝑛−1 × 2𝑛−1 + 𝑏𝑛−2 × 2𝑛−2 + ⋯ +𝑏1 × 2 + 𝑏0 = ෍ 𝑏𝑖 × 2𝑖

𝑖=0
• 𝑉 𝐵 = 1 × 8 + 0 × 4 + 1 × 2 + 1 × 1 = 11
9
Binary to Decimal Conversion
Convert 110010 2 to decimal
Answer: 110010 2 = 50 10
10
Decimal to Binary Conversion
Convert 857 10 to binary
Answer: 857 10 = 1101011001 2
11
Binary Numbers
12
Octal and Hexadecimal Representation
• 𝐾 = 𝑘𝑛−1 𝑘𝑛−2 … 𝑘1 𝑘0
𝑛−1
𝑉 𝐾 = ෍ 𝑘𝑖 × 𝑟 𝑖
𝑖=0
• 𝑟 = 8 for octal numbers
• Values range from 0 to 7
• 𝑟 = 16 for hexadecimal numbers
• Values range from 0-15. 10, 11, 12, 13, 14 and 15 are represented by A, B, C, D, E, F
respectively
• Octal & Hexadecimal numbers serve as short hand notation for binary
numbers
13
Binary to Octal & Octal to Binary
• Convert 101011010111 2 to Octal
• Convert 5327 8 to Binary
14
Binary to Hexadecimal & Hexadecimal to
Binary
• Convert 1010111100100101 2 to Hexadecimal
• Convert AF25 16 to Binary
15
Decimal to Hexadecimal
16
Hexadecimal to Decimal
17
Summary
• 𝐾 = 𝑘𝑛−1 𝑘𝑛−2 … 𝑘1 𝑘0
𝑛−1
𝑉 𝐾 = ෍ 𝑘𝑖 × 𝑟 𝑖
𝑖=0
• Decimal: 𝑟 = 10, 𝑘 = 0,1, … , 9

• Binary: 𝑟 = 2, 𝑘 = 0,1
• Octal: 𝑟 = 8, 𝑘 = 0,1, … , 7
• Hexadecimal: 𝑟 = 16, 𝑘 = 0,1, … , 9, 𝐴, 𝐵, … , 𝐹
• Unsigned numbers
• ≥0
• Binary numbers are used in computers
• Octal and hexadecimal numbers serve as shorthand
notation for binary numbers
18
Addition of Unsigned Numbers
19
Half Adder
20
Full Adder
21
Full Adder – Diagram
22
Decomposed Full Adder – Diagram
ci s
si
s HA c
xi
HA c ci + 1
yi
ci
si
xi
yi
ci + 1
23
Ripple Carry Adder
xn – 1
yn – 1
x1 y1 x0 y0
c1
cn FA cn ” 1 c2 FA FA c0
sn –1
s1 s0
MSB position LSB position
24
2’s Complement Representation
• Examine bits the number from right to left and taking the following action:
copy all bits that are 0 and the first bit that is 1; then simply complement
the rest of the bits.
• +5 = 0101 2
• −5 = 1011 2
• 10110100 2
• 01001100 2
• 𝑉 𝐵 = (−𝑏𝑛−1 × 2𝑛−1 ) + 𝑏𝑛−2 × 2𝑛−2 + ⋯ +𝑏1 × 2 + 𝑏0

25
ASCII Character
Code
EE-222 Microprocessor Systems (Spring 2021) -

26
Lec Aamir Javed
Addition of Hex Numbers

27
Javed
Subtraction of Hex Numbers

28
Javed
Microprocessor
• The microprocessor is a clock-driven digital integrated circuit
• It accepts binary input
• It processes it according to instructions stored in its memory
• It provides a binary output.
• Microprocessor contains both combinational logic and sequential
logic
• The CPU and other necessary logic is typically included on a single
integrated circuit using VLSI

29
Javed
Microprocessor
• Microprocessor typically includes an arithmetic logic unit (ALU), and a
control logic section.
• The ALU performs addition, subtraction, and operations such as AND
or OR
• The control logic retrieves instruction codes from memory and
initiates the sequence of operations required for the ALU to carry out
the instruction

30
Javed
Microprocessor
• Microprocessor are typically general purpose
• Specialized microprocessors include
• Digital signal processor (DSP)
• Graphics processing units (GPUs)
• Microcontrollers integrate a microprocessor with memory and peripheral
devices in embedded systems
• Systems on chip (SoCs) often integrate one or more microprocessors or
microcontrollers along with modems etc

31
Javed
Intel 80X86
• First part (4 Weeks approx.) of the course will focus on
microprocessors
• We will focus on Intel 80X86 family

32
Javed
Inside the Computer
• Bit is a binary digit that can have a value 0 or 1
• Kilobyte (210 = 1024 bytes)

• Megabyte (220 = 1024 kilobytes = 1,048,576 bytes)
• Gigabyte (230 over 1 billion bytes)
• Terabyte (240 over 1 trillion bytes)

33
Javed
Memory
• RAM (random access memory)
• Used for temporary storage
• Lost when computer is turned off
• Volatile memory
• ROM (read-only memory)
• Not lost when the power is off
• Non-volatile memory

34
Javed
Internal Organization
• CPU (central processing unit) – processes information
• Memory – Used for information (data/code) storage
• I/O (input/output) devices – Used for communicating with CPU
• CPU is connected to I/O and memory through strips of wire called bus

35
Javed
Bus
• Types: Address bus, data bus and control bus
• Each device must have a unique address to be recognized by the CPU
• CPU puts address of device on address bus.
• Decoding circuitry finds the device
• CPU can use the data bus to send/receive data to/from the device
• Control bus is used to provide read or write signals to communicate
when CPU is asking for or sending info
• Address and data bus determine the capability of a given CPU

36
Javed
Bus
• Address and data bus determine the capability of a given CPU
• Data bus is used to carry information in and out of CPU
• More lines in the data bus means more data can be carried in/out
• Cost increases with more lines
• 16-bit bus is twice as fast as 8-bit bus
• Address bus is used to identify and address the devices and memory
connected to CPU
• More lines in the address bus means more memory can be addressed by the
CPU
• 16-bit bus can access 64K bytes
• 20-bit bus can access 1M bytes

37
Javed
Bus

38
Javed
RAM / ROM
• ROM contains fixed and permanent information such as BIOS and
essential programs
• RAM is used for temporary information storage like loading different
applications
• RAM/ROM are called primary memory since CPU can directly access
them
• Hard disk etc are called secondary memory since CPU cannot directly
get information from them

39
Javed
Intel 8086
• 8086 is a 16-bit microprocessor
• All registers are 16-bit wide
• Bus is 16-bit wide to transfer data in and out of the CPU
• External bus (that communicates with peripherals) is 16-bit wide
• 20 address lines (1MB addressable memory)
• Introduced by Intel Corporation in 1978
• Major improvement compared to 8080/8085
Processor 8086 8080/8085
Memory 1MB 64KB
System 16-bit 8-bit
Pipelining Yes No
40
Javed
Intel 8088
• 8088 is almost identical to 8086
• 8-bit external bus width (instead of 16-bit) to communicate with peripherals
• Cheaper motherboard
• IBM PC based on 8088 was released in 1981
• It ran MS-DOS operating system
• It was an open system (compared to Apple computer)
• Documentation and specifications of Hardware and Software were made
public

41
Javed
Intel 80286
• As need grew for more powerful processors, Intel introduced 80286 in
1982
• 16-bit internal and external data bus
• 24 address lines (provides 224 = 16 megabytes of addressable memory)
• Virtual memory
• Provides access to nearly unlimited memory by swapping data between disk storage
and RAM
• Can operate in real and protected mode
• Real mode provides a faster 8088/8086 with 1 megabytes of memory
• Protected mode protects operating system and programs from accidental or
deliberate damage by the user

42
Javed
Intel 80386
• Introduced by Intel in 1985
• 32-bit internal and external data bus
• 32 address lines (provides 232 = 4bytes gigabytes of addressable
memory)
• Virtual memory of 246 = 64 terabytes

43
Javed
Coprocessors
• Intel 80X86 are general purpose processors
• They cannot handle mathematical calculations well
• Math coprocessors: 8087, 80287, 80387, 386SX

44
Javed
80486
• Introduced by Intel in 1989
• 80386, 386SX and cache memory are integrated on a single chip
• Pentium and Core processors are further evolution of 80X86 series

45
Javed
Summary

46
Javed
Internal Architecture of 8086/8088

47
Javed
• 8088/8086 is split into two sections
• Execution unit (EU)
• Bus Interface Unit (BIU)
• The two sections work simultaneously
• EU executes instructions previously fetched
• BIU accesses memory and peripherals (to access data and fetch
instructions)

48
Javed
Pipelining
• EU executes instructions previously fetched
• BIU accesses memory and peripherals (to access data and fetch
instructions)
• Pipelining simply means that CPU can fetch (BIU) and execute
instructions (EU) at the same time
• Without pipelining CPU has to fetch the instruction, then execute and
then fetch the next instruction again
• Memory access requires time
• Pipelining enhances the performance of a processor by the increasing
the rate at which it processes data

49
Javed
Pipelining

50
Javed
• BIU keeps ahead of EU. BIU has a buffer or queue (4 bytes long in
8088 and 6 bytes long in 8086)
• BIU fetches a new instruction whenever there is room for 2 bytes
(8086) or 1 byte (8088)
• BIU flushes the queue in case of jump/branch instructions (results in
branch penalty)

51
Javed

52
Javed
Registers of 8086/80286 by category

53
Javed
Registers of 8086/80286
• The general-purpose registers can be accessed as 16-bit registers (AX,
BX, CX, DX) as well as 8-bit registers (AL,AH,BL, ….)
• AX is used for accumulator
• BX is used for base addressing
• CX is used as counter in loop operations
• DX is used to point to data in I/O operations

54
Javed
Assembly Language
• CPU works in binary (0s and 1s)
• A program that consists of 1s and 0s is known as machine language
• Used in early days of computing
• Assembly languages are human readable/understandable
• Mnemonics are used for machine code instructions
• Make programming faster and less error prone
• Assembler translates the assembly language program to machine code
• Assembly language is referred to as a low-level language
• We have to deal directly with internal structure of CPU

55
Javed
Modern Programming Languages
• Modern languages such as C/C++/Java etc are high-level programming
languages
• No need to deal with internal details of a CPU
• Compiler is responsible for translating the code into machine language

56
Javed
Assembly Language Programming
• Assembly language program consists of a series of lines of Assembly
language instructions
• An instruction consists of a mnemonic, optionally followed by one or
more operands
• Mnemonic represents the operation that will be performed by the CPU on the
operand(s)
• We will study only some basic Instructions to give you an idea of how
microprocessor processes data

57
Javed
MOV Instruction
• MOV instruction copies data from one location to another
• Examples (with 8-bit operands):

58
Javed
MOV Instruction
• Examples (with 16-bit operands):

59
Javed
ADD Instruction
• ADD instruction tell the CPU to add the source and the destination
operands and put the result in the destination

60
Javed
ADD Instruction
• Example (with 8-bit operands):
• There are many ways to write the same program
• Without moving both operands to registers

61
Javed
ADD Instruction
• Example (with 16-bit operands):
• Without moving both operands to registers

62
Javed
Program Segments
• Assembly language program has at least three segments
• Code segment: Contains assembly language instructions
• Data segment: Used to store information (data that needs to be processed by
the instructions in the code segment)
• Stack segment: Used to store information temporarily
• A segment is an area of memory that includes up to 64K bytes and
begins on an address evenly divisible by 16 (i.e address should end
with 0H)
• 8086/8088 can handle a max of 64K bytes of code, data and stack at a
given time
63
Javed
Logical and Physical addresses
• How to cover all 1 megabytes of memory?
• Physical address is the 20-bit address that is put on the address pins
of 8086 and decoded by the memory interfacing circuit
• Range of 00000H to FFFFFH
• This is an actual physical location in RAM or ROM within 1 megabyte memory
range
• Offset address is a location within a 64K-byte segment range
• Can range from 0000H to FFFFH
• The logical address consists of a segment value and an offset address

64
Javed
• The logical address of an instruction consists of a segment value (CS)
and an offset address (IP)
• Shown in CS:IP format
• Conversion to physical address
• First shift the code segment (CS) left by 4-bits (1 Hex digit)
• Then add the offset address (IP)
• Example: 2500: 95F3H

65
Javed
• Conversion to physical address
• First shift the code segment (CS) left by 4-bits (1 Hex digit)
• Then add the offset address (IP)
• For CS = 2500
• Min value (2500:0000H) -- 25000+0000 = 25000H
• Max value (2500:FFFFH) -- 25000+FFFF = 34FFFH
• If desired instruction doesn’t lie in this range?
• Change the value of CS

66
Javed
Code Segment

67
Javed
Code Segment

68
Javed
Data Segment
• Add 5 numbers (data and code are mixed)
• If data changes, the code must be changed

• Alternative: Use data segment

69
Javed
Data Segment
• Data segment uses register DS and an offset value
• Data segment (beginning at 0200H)
• Brackets indicates that the operand is an address

• Now changing the data has no effect on the code

70
Javed
Data Segment
• Use a register to hold offset address
• DS can use BX, DI and SI to hold offset address of data
• INC BX instruction adds 1 (equiv to ADD BX,1)

71
Javed
Data Segment

72
Javed
Big Endian / Little Endian
• Low byte goes to low memory location and the high byte goes to high
memory address
• DS:1500 contains F3H
• DS:1501 contains 35H
• This convention is known as little endian
• In Big endian, low byte goes to high address and the high byte goes to low
memory address
• Intel processors use little endian convention
73
Javed
Extra Segment
• ES is a segment register used as an extra data segment
• Essential for string operations

74
Javed
Memory Map of the IBM PC
• For a program to be executed on the PC, DOS must first
load it into RAM
• 20-bit address allows 8086/8088 a total of 1 megabyte
(1024K bytes) of memory space
• 00000 – FFFFFH
• Memory allocation to various sections of PC is known as
a memory map
• 640K bytes from addresses 00000 – 9FFFFH are set aside
for RAM
• 128K bytes from A0000H to BFFFFH are allocated for
video memory
• Remaining 256K bytes from C0000H to FFFFFH are set
aside for ROM

75
Javed
Memory Map of the IBM PC
• 640K bytes from 00000H to 9FFFFH are referred
to as conventional memory
• 384K bytes from A0000H to FFFFFH are called
UMB (upper memory block)
• The amount of video memory used depends of

video board installed on the PC

76
Javed
RAM
• In 1980s, PCs came with 64K to 256K bytes of
RAM
• Users needed to buy memory expansion boards
to expand memory upto 640K
• DOS allocates RAM for its own use first, then rest
is used for applications
• Values of CS, DS and SS are usually decided by
OS based on various factors
• May be different on different PCs

77
Javed
ROM
• 64K bytes (from F0000H to FFFFFH) are used by
BIOS (basic input/output system) ROM
• Remaining space is used by adaptor cards such
as cards for hard disk

78
Javed
BIOS ROM
• CPU can only execute programs stored in the memory
• RAM is volatile memory. It will be lost of power down
• There must be some permanent (non-volatile) memory to hold the
programs telling the CPU what to do on Power up
• This collection of programs held by ROM is called BIOS
• BIOS stands for basic input-output system
• Function of BIOS is to test all the devices connected to the PC when
the computer is turned on and to report any errors
• BIOS will the load DOS from the disk into RAM and hand over the
control to DOS
79
Javed
Stack Segment
• Stack is a section of read/write memory (RAM) used by the CPU to
store info temporarily
• CPU needs this storage because registers are limited
• SS (stack segment) and SP (stack pointer) register are used to access
stack
• They must be load with appropriate values before any instructions
accessing the stack are used
• All registers except segment registers and SP can to stored and
retrieved from the stack

80
Javed
Stack Segment
• Storing CPU register in the stack is known as push
• Loading the contents from stack into the CPU register is known as pop
• Register is pushed into the stack to store and popped off the stack to
retrieve it
• In 80x86, SP point to memory location at the top of the stack
• As data is pushed onto the stack it is decremented
• It is incremented as data is popped off the stack into the CPU
• Stack grows from upper addresses to lower addresses. This is opposite of
IP, which is incremented as each instruction is executed
• Push/pop work on 16-bit data
81
Javed
Stack

82
Javed
Stack

83
Javed
Stack Segment

84
Javed
Flag Register
• Flag register is a 16-bit register
• Also known as status register

85
Javed
Flag Register

86
Javed
Flag Register

87
Javed
Use of Zero Flag for Looping

88
Javed
80x86 Addressing Modes
• CPU can access operands (data) in various ways
• Known as addressing modes

89
Javed
Register Addressing Mode
• Registers hold the data that is to manipulated by the CPU
• Fast
• No need to access memory

90
Javed
Intermediate Addressing Mode
• Source operand is a constant
• Operand comes immediately after the opcode
• Fast, since no memory access needed
• Can be used to load registers (except segment registers and flag
registers)

91
Javed
Direct Addressing Mode
• Data is in some memory location(s) and the address is specified with
the instruction
• Address is the offset address. Combined with DS to get physical address

92
Javed
Register Indirect Addressing Mode
• Address of the memory location where operand resides is held by a
register. SI, DI and BX are used and combined with DS to get physical
address

93
Javed
Based Relative Addressing Mode
• Base register BX and BP, as well as a displacement value, are used to
calculate the effective address
• Default segments: DS for BX and SS for BP

94
Javed
Indexed Relative Addressing Mode
• Same as previous, except DI and SI hold the offset address

95
Javed
Based Indexed Addressing Mode
• Combining based and indexed addressing modes
• One base register and one index register are used

96
Javed
Offset Registers

97
Javed
Summary of Addressing Modes

98
Javed
8086 / 8088 Pin Diagram

99
Javed
• Pins 2-8 and Pins 35-39 (total 12 bits) are used for address in 8088
• Pins 9-16 (AD0 – AD7) are used for both data and address in 8088
• Pins 35-38 (total 4 bits) are used for address in 8086
• Pins 2-16 and Pin 39 (total 16 bits) are used for both data and address
in 8086
• ALE (address latch enable) is used to indicate whether information on
AD pins is address or data
• The process of separating address and data from AD pins is called
demultiplexing
100
Javed
• The process of separating address and data from AD pins is called
demultiplexing
• When processor sends out an address, it sets ALE high to indicate the
pins are carrying address
• This info must be latched
• Then pins are used to carry data and ALE is set low

101
Javed
Address/Data Demultiplexing

102
Javed
Address bus in 8088
• 8088 has 20 address pins (A0 – A19)
• Can address maximum 1 megabyte of
memory (220 = 1M)
• Latch is used to grab the address bits A0
– A7 from AD0 – AD7
• 74LS 373/573

103
Javed
8088 Control Bus
• 8088 can access both memory and I/O devices for read and write
operations
• 4 signals required

104
Javed
8088 Control Bus
• 8088 can access both memory and I/O devices for read and write
operations
• 4 signals required

105
Javed
8088 Control Bus

106
Javed
Bus Timing of the 8088

107
Javed
Bus Timing of the 8088
• 8088 uses 4 clock cycles for memory and I/O bus activities
• MEMR
• ALE is set high in the 1st cycle
• In 2nd and 3rd cycles, the read signal is provided
• Data is provided by the memory during 3rd cycle
• Data is at the pins of the CPU to be fetched in by the 4th cycle

108
Javed
8088 Pins

109
Javed
Von Neumann vs Harvard Architecture

110
Javed
RISC / CISC
• CISC (complex instruction set computer) processors have a very large
number of instructions dealing with a various operations, including very
complex operations
• Most of them are almost never used by programmers and compilers
• Costly and complex processors
• Highly complex instruction decoding
• Example: 80X86
• RISC (reduced instruction set computer) processors have less number of
instructions
• Simpler instruction decoding
• Less cost and complexity
• Example: ARM

111
Javed
RISC Features
• Fixed instruction size (simpler decoding)
• Use load/store architecture (operands are first brought into CPU
registers, operation performed, them stored into the memory)
• Large number of registers (stack use can be avoided)
• Small instruction set (INC/DEC instructions not avl, complex
instructions not avl)
• Most of the instructions are executed in one cycle
• Separate buses for data and code (Harvard architecture)

112
Javed

EE-222 Microprocessor Systems: DE-41 (EE) Syn C

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

EE-222 Microprocessor Systems: DE-41 (EE) Syn C

Uploaded by

Copyright:

Available Formats

EE-222 Microprocessor Systems

Course Intro + Introduction to Microprocessors

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) -

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

𝑉 𝐷 = 𝑑𝑛−1 × 10𝑛−1 + 𝑑𝑛−2 × 10𝑛−2 + ⋯ +𝑑1 × 10 + 𝑑0 = ෍ 𝑑𝑖 × 10𝑖

• Left-most bit (𝑏𝑛−1 ) is known as the most-significant bit (MSB)

𝑉 𝐵 = 𝑏𝑛−1 × 2𝑛−1 + 𝑏𝑛−2 × 2𝑛−2 + ⋯ +𝑏1 × 2 + 𝑏0 = ෍ 𝑏𝑖 × 2𝑖

Convert 857 10 to binary

Answer: 857 10 = 1101011001 2

• Convert 5327 8 to Binary

• Convert AF25 16 to Binary

• Decimal: 𝑟 = 10, 𝑘 = 0,1, … , 9

MSB position LSB position

• 𝑉 𝐵 = (−𝑏𝑛−1 × 2𝑛−1 ) + 𝑏𝑛−2 × 2𝑛−2 + ⋯ +𝑏1 × 2 + 𝑏0

EE-222 Microprocessor Systems (Spring 2021) -

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

• Kilobyte (210 = 1024 bytes)

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

• Examples (with 8-bit operands):

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

• There are many ways to write the same program

• Without moving both operands to registers

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

• Without moving both operands to registers

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir

EE-222 Microprocessor Systems (Spring 2021) - Lec Aamir