HALF ADDER – DATA FLOW

module dha(a,b, c,s);

input a,b;
output c,s;
assign s=a^b;
assign c=a&b;
endmodule
module TBha_v;

// Inputs
reg a;
reg b;
// Outputs
wire c;
wire s;
dha uut (
.a(a),
.b(b),
.c(c),
.s(s)
);
initial
begin
a = 0;b = 0;
#2 a = 0; b = 1;
#2 a = 1; b = 0;
 #2 a = 1; b = 1;
end
endmodule

ADDER SUBTRACTOR DATA FLOW

module Daddsub(input sel,input [3:0]a,input[3:0]b,output[3:0] result);

assign result = (sel)?(a+b):(b-a);
endmodule

BINARY TO GRAY CODE CONVERTER

module BIN2GARY (DATA_IN ,DATA_OUT );

input [3:0] DATA_IN ;
output [3:0] DATA_OUT ;
assign DATA_OUT [0] = (DATA_IN [0] ^ DATA_IN [1] ) ;
assign DATA_OUT [1] = (DATA_IN [1] ^ DATA_IN [2] ) ;
assign DATA_OUT [2] = (DATA_IN [2] ^ DATA_IN [3] ) ;
assign DATA_OUT [3] = DATA_IN [3];
endmodule

MUX (CONDITIONAL OPERATORS) DATA FLOW

module mux4_1_synth_conditional(w, s, f );
input [3:0] w;
input [1:0] s;
output f;
assignf = s[1]?(s[0]?w[3]:w[2]):(s[0]?w[1]:w[0]);
endmodule
 FULL ADDER(GATE LEVEL)

module Gfulladder(input a,input b,input c,output sum,output carry );

wire s1,s2,s3,s4;
xor a1(s1, a, b);
xor a3(sum, s1, c);
and a4( s2, a, b);
and a5( s3, b,c);
and a6( s4, a, c);
or a7 (carry,s2,s3,s4);
endmodule

4:1 MUX (GATE LEVEL)

module mux4_1_gatelevel( input i0, input i1, input i2, input i3,input s1, input
s0,output out);
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1, i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule
  JK FF(ASYNCHRONOUS RESET)

module jk_behav (input j, k, clk, reset, output qb, output reg q);
assign qb = ~q;
always@ ( posedge clk or posedge reset)
begin
if (reset)
q <= 4'b0;
else
case ({j, k})
2'd0: q <= q;
2'd1: q <= 1'b0;
2'd2: q <= 1'b1;
2'd3: q <= ~q;
endcase
end
endmodule
 D FF

module Dff_sync_reset (D , clk , reset , q );

input D, clk, reset ;
output reg q;
always@(posedge clk)
if (reset) begin
q <= 1'b0;
end
else
q <= D;
endmodule

4 BIT UP-DOWN BINARY COUNTER

module up_dwn_cntr(input up,clk,reset,output reg [3:0]count);

always@(posedge clk)
begin
if (reset)
count <= 4'b0;
else
begin
if (up)
count <= count+1;
else
count <= count-1;
end
end
endmodule