8086 Address/Data buses

RD
WR Control
M/IO

ADO-AD15 ADDR
A16-A19
BHE 74LS373

ALE STB

MEM I/O

OE
DT/R T
8086 8286
Transcei DATA
ver

BITS Pilani, Pilani Campus

 Buffered Systems

Address, Data and control bus buffered to

provide sufficiently strong signals to drive
multiple devices.

Unidirectional/bidirectional

C
A B

C
74LS244 74LS245

BITS Pilani, Pilani Campus

 Memory Chip

Memory location

D
E
C
ADD O
Bus D
E
R

DATA Bus

BITS Pilani, Pilani Campus

 8086 Address/Data buses

A0- A0-
ADO-AD15
AN AN

A16-A19 D0- D0-

D7 D7
BHE
___K x 8 ___Kx 8
ALE
RD RD RD
WR
8086 M/IO
WR WR

BITS Pilani, Pilani Campus

Interface using 2K Memory chips 8 K bytes of
Memory to the 8086 CPU

- Address Space

- No of Memory chips

- Decoding logic

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A19 A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00002H
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 00003H

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 00FFEH
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 00FFFH

4K (2K+2K)
BITS Pilani, Pilani Campus
ADDRESS DATA BUS DATA
TYPE BHE A0 CYCLES LINES
USED
00000 BYTE 1 0 ONE D0-D7
00000 WORD 0 0 ONE D0-D15
00001 BYTE 0 1 ONE D8-D15
00001 WORD 0 1 FIRST D8-D15
1 0 SECOND D0-D7

BITS Pilani, Pilani Campus

A19 A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1 A0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 01000H
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 01001H
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 01002H
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 01003H

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 01FFEH
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 01FFFH

4K (2K+2K) Total 8K
BITS Pilani, Pilani Campus
 MEMW
WR WR
MEMR RD RD
Data Bus
Of CPU

A1-A11 A0-A10 A0-A10

of CPU

Remaining ADD CS CS
Add lines Decoding
Of CPU Logic

BITS Pilani, Pilani Campus

 MEMR
RD
LOGIC MEMW
WR CIRCUIT
IOR
M/IO
IOW

BITS Pilani, Pilani Campus

Ex: Interface 1M of SRAM to 8086. Chips available
are of size 256K each.

A19 A18………………………………………………………A1 A0
0 0 ……………………………………………………… 0 0
512KB
0 1 ……………………………………………………….1 1
1 0 ……………………………………………………….0 0
512KB
1 1 ……………………………………………………….1 1

BITS Pilani, Pilani Campus

 A18 A17 D15-D8
A18 A17 D7-D0
256K
256K

A1 A0
CS A1 A0
CS
VCC VCC
GND GND
7 7
C 4 C 4
B 1 B 1
3 3
A19 A 1 A19 A 1
8 8
0 0

BHE GND A0 GND

BITS Pilani, Pilani Campus
Ex: Interface 4K of ROM to 8086 starting at 80000H.
Chips available are 2716.

A19 A18………………………A11 A10……………………A1 A0

1 0 ………………………..0….0……………………… 0 0
1 0 ………………………..1….1……………………….1 1

BITS Pilani, Pilani Campus

Ex: Interface 16K of ROM to 8086 starting at 80000H. Chips
available are 1KB each.

A19 A18………………………A11 A10……………………A1 A0

1 0 ………………………..0….0……………………… 0 0
2KB
1 0 ………………………..0….1……………………… 1 1
1 0 ………………………..1….0……………………… 0 0
2KB
1 0 ………………………..1….1……………………….1 1

BITS Pilani, Pilani Campus

Ex: Interface 8K of RAM to 8086 starting at
00000H. Chips available are 1KB(4 Chips) and 2KB
(2 Chips).

BITS Pilani, Pilani Campus

Ex: Interface
4K 2716 (ROM) starting at 00000H
8K 6116 (SRAM) starting at 08000H

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Input Device:

Ex: Switch
VCC

S1 A

BITS Pilani, Pilani Campus

 VCC

R B
U
F
I O To data lines
F
S1 Of CPU
E
R

From Add Decoding

Logic

BITS Pilani, Pilani Campus

IN AL, 00H

ROR AL, 1

JC SWITCH OPEN

I/O MAPPED I/O

MOV AL, [0000H]

ROR AL, 1

JC SWITCH OPEN

MEMORY MAPPED I/O

BITS Pilani, Pilani Campus
Output Device

Ex: LED

R
A

BITS Pilani, Pilani Campus

 L R
From A
CPU
T
Data I O
line C
H
E

From Add
Decoding logic

BITS Pilani, Pilani Campus

 To turn the LED on

MOV AL, 01H

OUT 00H, AL

To turn the LED OFF Add Decoding

Logic

MOV AL, 00H

OUT 00H, AL

I/O Mapped I/O

BITS Pilani, Pilani Campus
 Interfacing input devices like switches
require buffers

 Interfacing output devices like LEDs

require latches.

 Programmable Peripheral Interface ( PPI)

provide these features.

BITS Pilani, Pilani Campus

8255

- Three 8 bit ports Port A, Port B, Port C

- Can act as output port / input port

- 8 bit data bus

- 8 bit control register used to program 8255

BITS Pilani, Pilani Campus

RD
PORT A
WR PA0-PA7

D0
PORT B
D7 PB0-PB7

CS
A0 PORT C
A1 PC0-PC7

CONTROL
REG

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
8255 Can Operate in Different Modes

- I/O Modes

MODE 0 - Simple I/O Mode

MODE 1 - Hand shaked I/O Mode

MODE 2 - Bi-directional I/O

- BSR ( Bit Set Reset) Mode

Port A can operate in Modes 0,1,2

Port B can operate in Modes 0,1
Port C can operate in Mode0, BSR mode

BITS Pilani, Pilani Campus

Port C divided into Port C0-PC3 lower port &
PC4- PC7 upper port

Port A and Port C Upper grouped – Group A

Port B and Port C lower grouped - Group B

BITS Pilani, Pilani Campus

Programming is done by writing a control word in
control register.
Control Word

D7 D6 D5 D4 D3 D2 D1 D0

A1A0 - 11 Control Register

A1A0 - 00 Port A
A1A0 - 01 Port B
A1A0 - 10 Port C

BITS Pilani, Pilani Campus

 Control Register

• There are two groups of control blocks in

the 8255A control register
D7 D6 D5 D4 D3 D2 D1 D0

Mode Set Flag

0 - bit set/reset
1 – I/O mode
Group B Mode
Group A Mode 0 - mode 0
00 - mode 0 1 - mode 1
01 - mode 1
1x - mode 2 PORT B
PORT A 0 - output
0 - output 1 - input
1 - input
PORT C (lower)
PORT C (upper) 0 - output
0 - output 1 - input
1 - input
Write the Initialization routine to initialize 8255 as per
the following specifications:

Port A- Input Port – Mode 0

Port B- Output Port - Mode 0

Port Cupper – Input Port - Mode 0

Port C lower – Output Port – Mode 0

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
 vcc

O
U
T
P VCC
O
U
T

O
R
T

IN PORT

BITS Pilani, Pilani Campus

 VCC VCC VCC VCC

C S C S C S C S

P
O
R
T

7447

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 Interfacing Analog to Digital Converter

8-bit ADC
Vin
D0 Vref

D7 Start

EOC Conversion time

To start conversion 20 S EOC = 1
send 2S active high AD 570 indicates
pulse at start
end of conversion

BITS Pilani, Pilani Campus

Interfacing Analog to Digital Converter

I0
8-bit ADC
I7

D0 ALE

D7 A
B
C

EOC
Start
ADC 0809
OE’

BITS Pilani, Pilani Campus