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An optimized high gain CMOS LNA using simulated annealing and modified
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 An Optimized High Gain CMOS LNA using Simulated Annealing
and Modified Genetic Algorithm
Shervin Ehrampoosh *, Ahmad Hakimi **, and Hamid Reza Naji ***
* Kerman Graduate University of Technology (Kerman, Iran), s_ehrampoosh@yahoo.com
** Shahid Bahonar University of Kerman (Kerman, Iran), hakimi@mail.uk.ac.ir
*** Kerman Graduate University of Technology (Kerman, Iran), hamidnaji@ieee.org
Abstract— This paper proposes two simulation-based evolutionary
and statistical approaches for designing a 18 GHz Low Noise
Amplifier (LNA) with using 0.13 µm technology. Based on genetic
algorithm (GA), simulated annealing (SA), the Levenberg-
Marquardt (LM), and circuit simulator, the simulation-based
methods simultaneously optimize the electrical specifications, such
as S-parameters, the noise figure, and the input-referred third-order
intercept point in the process. In the designed LNA, the structure of
one-stage cascode amplifier with source inductive degeneration is
used. This LNA draws 12 mA from the 1.2V power supply. The
LNA demonstrates 17.62 dB for S21 and 18.6 dB for MAG at the
peak gain frequency of 17.49 GHz. The optimized simulation
results show that the proposed LNA has a noise figure (NF) of 1.8
dB in the 17.49 GHz frequency. For large input signal level, P1dB,
OIP3, and IIP3 are: -8 dBm, +23 dBm and +11 dBm, respectively.
Keywords: Low noise amplifier (LNA), Genetic algorithm (GA),
Simulated annealing (SA).
1. Introduction
The advances in CMOS technology have guided the
progress in the wireless communications circuits and
systems area. Various new communication standards are
developed to accommodate a variety of applications at
different frequency bands. The modern wireless technology
is motivated by the global trend of developing technology
for low-cost and multifunction transceivers. One of the
challenging building blocks in receivers is the Low Noise
Amplifier (LNA) [1]. The LNA contributes most of the
noise figures. Therefore, the design and optimization in the
noise figure, gain, and power consumption for a CMOS
LNA becomes the major concern in millimeter-wave
Integrated Circuits. In the conventional designs, the
common-source configuration is usually used to implement
a CMOS LNA. In order to make the best trade-off between
the maximum small signal gain and the minimum noise
figure, the inductive source degeneration structures [2] were
reported. However, a single-stage common-source LNA
cannot provide high gain, especially in millimeter-wide
bands (MMW) [3]. In some reported papers, the LNAs with
the cascode device [4]-[8] become common. The cascode
structure is composed of a common-source and a common-
gate transistor. It has the advantages of high gain and good
performance, as the operation frequency increases to MMW
bands, the common-gate stage will contribute a considerable
noise, and thus results in high noise figure of a cascode or
triple-cascode structure in millimeter wave LNA design.
In [9], the parallel resonant inductor was used to reduce
the noise of the cascade device, but a large inductor and
bypass capacitor were required [3]. Our focus was in 20
GHz frequency that is reported in [11]-[18], but not in the
same technologies. Among them, the single-ended structure
has been used in [12]–[17], whereas the differential
topology has been adopted in [11] and [18]. The inductive
degeneration at the source of the input transistor has been
used previously [11]–[12], [15]–[17] to achieve both noise
and input impedance matching. To obtain high gain, the
multi-stage configuration has been proposed [11], [13]–[17],
however, they generally consume more power and lose the
linearity performance. Generally, the single-ended structure
has the advantage of a good noise figure (NF) and low-
power consumption [19]. In the work reported by Wang et al
[19], a 23 GHz one stage cascode source inductive
degeneration LNA has been designed and fabricated in 45
nm planar bulk CMOS technology with high-Q above-IC
inductors. It has the advantages of low power consumption,
but its gain is weak and noise figure of 4 dB that is more
than usual.
In this work, a one-stage cascode LNA with source
inductive degeneration is designed. it is adopted to achieve
low power dissipation, high linearity, suitable S-parameter
and good noise figure. The calculated LNA figure of merit
of 15.8 makes it suitable among the CMOS LNAs reported
in this frequency range of operation. The optimized
simulation results show that the proposed LNA has a noise
figure (NF) of 1.8 dB in the 17.49 GHz frequency. It also
indicates that the input reflection coefficient (S11), is less
than -10 dB (-12.84 dB), the output reflection coefficient
(S22) is -8.48 dB and the reverse reflection coefficient (S12),
is about -30 dB. By employing the signal flow theory and
the S-parameter, it is found that the LNA is unconditionally
stable. Maximum available gain (MAG) and maximum
stable gain (MSG) are 18.6 dB and 23.75 dB in the
frequency of 17.49 GHz. For this design, P1dBm, output-
referred third-order intercept point (OIP3) and input-
referred third-order intercept point (IIP3) are -8 dBm, +23
dBm and +11 dBm, respectively.
This paper is organized as follows. Section 2 describes
the design techniques of LNAs. Section 3 presents the
proposed one stage cascode LNA. Section 4 and Section 5 3. The one-stage cascode LNA
outline two optimization methods considered in this paper.
Section 6 introduces the Levenberg-Marquardt (LM) method The circuit diagram of the designed one-stage source
to search the local optima. Section 7 addresses simulation inductive degeneration LNA is shown in Fig. 2. The cascode
results and finally, conclusion will be seen in the last amplifier formed by M2 and M1 is employed to reduce the
section. Miller effect of M2 and to obtain good reverse isolation. The
degenerative inductor Ls at the source of M2 is used to
2. The design techniques of LNAs provide the input more resistive and low ohmic for
impedance matching. With Ls, the design goals of both noise
A number of LNA topologies have been proposed to and input impedance matching can be performed
achieve the highest performance i.e. the cascade, the simultaneously. Furthermore, Ls does not seriously degrade
cascode [3], current-reused [21], common-source with the NF performance. However, increasing the value of Ls
inductive source degeneration, common-source with reduces the gain of the amplifier. The value of Ls in this
resistive drain gate feedback and transformer folded-cascode design is set at 0.08 nH. The widths of M1 and M2 are
[10]. All of these designs compromise between gain and chosen as 88.6µm and 34.3µm. The power consumption is
performance, as shown in Fig. 1. For example in cascode designed to be less than 13 mW from a 1.2 V power supply.
amplifiers gain is very high but there is no suitable stability
or even chip area is large. In the design with an inductive
source degeneration, we have low noise and high gain but
stability can be critical for non-differential topologies due to
undesired feedbacks in grounds [20]. A folded-cascode
LNA, which has no cascode transistor, is one of the best
choices for low voltage operations. The reason is, it requires
a supply voltage for only one drain saturation voltage
(VDD>VDS,sat) whereas in Cascode amplifiers it is needed that
(VDD >2VDS,sat) to operate the transistors in linear region, but
folded-cascode circuit requires more inductive, which leads
to an increase in chip area. With employing transformer in a
folded-Cascode design, we can reduce the area of the
inductors and improve the noise performance of the LNA. It
will be done by decreasing the contribution from the noise
of common-gate stage [10].

Fig. 2. Circuit diagram of the one-stage cascode LNA.

The input matching network is designed using Lg, Ls, R1,

C1, and C2. The output is loaded with an inductor Ld to
provide parallel resonance and to increase the gain at the
desired frequency. Fig. 3, shows the small signal equivalent
circuit for the input part of the overall LNA, where Cgs
represent the gate-source capacitance of the transistor M2. In
Fig. 3, a combination of reactive elements is chosen to
resonate at the frequency of interest such that Zin becomes a
real value with ωt Ls being equal to the source resistance
(filter termination). The ωt represents the cutoff frequency
of transistor M2 (ωt =gm2/Cgs2).

Fig. 3. Small signal equivalent circuit at the input.

Fig. 1. Conventional LNA topologies. (a) cascode, (b) current-reused, (c)
common-source with resistive drain gate feedback and inductive source
degeneration, (d) Transformer folded-cascode.
 Fig. 4. Small-signal model of cascode LNA.
The noise factor of a source inductive degeneration
Zin(s) is expressed as follows: cascode LNA shown in Fig. 2 is derived for the small-signal
model in Fig. 5:
⎛ ⎧ ⎛ 1 ⎞⎫ ⎞
⎜ Z 1 (s ) × ⎨sL g + ⎜ R 1 ⎟⎬ ⎟
⎛ 1 ⎞ ⎜
Z in (s ) = ⎜ +
⎩ ⎝ sC 5 ⎠⎭ ⎟
(1) γ.g d 0 .ℑ ( ω )
⎟
⎝ sC 1 ⎠ ⎜ ⎧ ⎛ 1 ⎞⎫ ⎟ F (ω ) = 1 + (7)
2
⎜ Z 1 (s ) + ⎨sL g + ⎜ R 1 ⎟⎬ ⎟ g m R eqi
⎝ ⎩ ⎝ sC 5 ⎠ ⎭ ⎠

1 ⎛⎛ gm ⎞
2
δ ⎞
Where Z1(s) is given by:
⎛ 1 ⎞
ℑ (ω ) = ω
2 2
ℜC gs R eqi + ⎜⎜
ℜ ⎜ ⎝ gd 0
⎟
5γ ⎠
(1 − c ) ⎟⎟
2

⎝ ⎠
⎜ sC gs 2 ⎟⎟ ( t s ) ( s )
Z 1 (s ) = ⎜ + ω L + sL (2)
⎝ ⎠ gm δ ⎧ ⎛ gm δ ⎞⎫
ℜ =1+ . ⎨2 c + ⎜ . ⎟⎬
The output matching network has been designed to gd 0 5γ ⎩ ⎝ g d 0 5γ ⎠⎭
match 50Ω by Ld, C4 and C5. The bypass capacitors is added
between Vg (VDD) and ground in order to stabilize the bias
voltage (supply voltage) and to isolate the bias (supply)
noise from entering the LNA. A simplified equivalent small
signal circuit that is used for obtaining a voltage gain is
presented in Fig. 4.

The voltage gain of this circuit with neglecting Cgd

is calculated as:
Fig. 5. Small-signal noise model of source inductive degeneration LNA.

V out g m 1 g m 2C 1Y s (C 2 R1s + 1)
2
C4 4. Simulated annealing algorithm
AV = = × ( 3)
V in (
ℑ ( s ) .Y d g m2 2 − C gs
2
2 s 2
) C 4 +C5 Simulated annealing as a statistical approach is a
generalization of a Monte Carlo method for examining the
2
( ( ) )
ℑ ( s ) = g m 1C gs 1s + s C 1Y s + C gs 1 Y g +Y s + C 1 g m 1 ...
equations of state and frozen states of n-body systems. The
... +Y g (Y s + g m 1 ) concept is based on the manner in which liquids freeze or
metals recrystalise in the process of annealing. In an
Where Yg, Ys, and Yd are given as follows: annealing process, a melt is initially at high temperature,
disordered, and is slowly cooled so that the system at any
time is approximately in thermodynamic equilibrium. As
⎛ 1 ⎞ 1 ⎛ 1+ sR1C2 ⎞ cooling proceeds, the system becomes more ordered then
Z g = ⎜ R1 ⎟ + sLg ⇒ Y g = =⎜ ⎟ ( 4)
⎝ sC 2 ⎠ Z g ⎜ sLg + R1 1−C2Lg
⎝ ( ) ⎟
⎠
approaches a "frozen" ground state at zero temperature.
Hence, the process can be thought of as an adiabatic
1 1 approach to the lowest energy state. If the initial temperature
Z s = Rss + sLs ⇒ Y s = = ( 5) of the system is too low, the system may become quenched.
Z s Rss + sLs
The original Metropolis scheme was that an initial state of a
(
Y d = sC4 sC5 + ) 1
sLd
⎛ CC
=s ⎜ 4 5 − ⎟
1 ⎞
⎝ C4 +C5 Ld ⎠
( 6) thermodynamic system was chosen at energy E and
temperature T. Holding T constant, the initial configuration
is perturbed and the change in energy, ∆E , is computed. If
the change in energy is negative, the new configuration is
accepted. If the change in energy is positive, it is accepted
with a probability factor exp(-∆E/T). This process is then
repeated sufficient times to give good sampling statistics for
the current temperature, and then the temperature is
decremented and the entire process repeated until a frozen
state is achieved at T=0. When the simulated annealing
schedule is applied to an optimization problem, the energy
function becomes the objective function, and the
configuration becomes the solution configuration of the
parameters. The general procedure for the SA algorithm can
be summarized as follows:
Step 1: Select an initial solution X and an initial temperature T.
Step 2: Find another solution, namely Xnext, by modifying the
last answer X.
Step 3: Calculate the energy differential ∆E=f(Xnext)-f(X)
Step 4: If ∆E < 0 , go to Step 9.
Step 5: Generate a random number, namely R between 0 and 1.
Step 6: If R<exp(-∆E/T), go to Step 9.
Step 7: Repeat Steps 2–6 for a number of optimization steps for
the given temperature.
Step 8: If no new solution, Xnext is accepted then go to Step 10.
Step 9: Decrease the temperature T, replace X with Xnext and go
to Step 2.
Step 10: Reheat the environment with setting T to a higher
value.
Step 11: Repeat Steps 1 through 10 until no further improvement
obtained.
5. Genetic algorithm
The genetic algorithm (GA) approach is based on
Charles Darwin’s survival of the fittest theory, which states
that species evolve through their best genetic variation. In
fact, it is an evolutionary approach. The term evolutionary
algorithms (EAs) stands for a class of stochastic
optimization methods that simulate the process of natural
evolution. In this context best means the strongest, healthiest
and most intelligent genus that is able to adapt to its
surrounding by applying and developing its abilities. As
evolution progresses, the strongest elements become
stronger and the weakest are eliminated. The GA emulates
this process in the following way. In order to search the
problem solution space the GA uses strings of integers
called chromosomes to represent the parameters being
optimized. Each individual integer component is called a
gene. These chromosomes are decoded into the problem
parameters and applied to a simulation of the problem. A
measure of performance of each solution is calculated using
the same cost evaluation as in the SA methods. Once all the
cost values are obtained they are sorted into ascending order
(along with their corresponding chromosomes) so that the
smallest costs are selected as the best. These are then
subjected to the operations of reproduction, crossover and
mutation, which provide different points within the search
space for analysis.
Reproduction is where the best chromosomes of the
present population are kept for the next population. The
remaining individuals are replaced by new chromosomes,
which are formed through the crossover and mutation
processes.
Crossover takes any two chromosomes from the present
generation (these are called the parents), selects a number of
genes from one of the parents and swaps them with the same
number and positioned genes in the other parent. This forms
two new chromosomes called the children. This is repeated
until there are enough children to replace the rest of the
present population that have the poorest cost values.
Mutation is simply the random selection of a percentage
of the new population’s genes and the random alteration of
these genes’ values (i.e. random change of genes in the
range between 0 and 9).
After the chromosomes have been altered to form the
new population, they are evaluated in the same way as the
previous population and cost values obtained for Each
chromosome. The processes of decoding, application,
evaluation and chromosome manipulation are repeated for a
set number of iterations (called generations), by which stage
the GA should have reached an optimal solution. This
number of iterations is called the generation size.
6. The Levenberg-Marquardt (LM) method
The Levenberg-Marquardt LM method is a quasi-
Newton method to accelerate the Gauss–Newton method.
The Gauss–Newton method is the basic algorithm for
solving the nonlinear optimization problem. Due to the
nonlinear property of the problem, a gradient for each
variable can be obtained. It starts from an initial guess, and
follows the direction of the normal of the gradient to find the
optimal solution. Therefore, the initial guess must be chosen
carefully, or the solution may fell into a local optima. Unlike
the Gauss–Newton method has the fixed steps toward the
solution, LM optimization method detects that some regions
with monotonic variation property can be speed up by
increasing the step size. On the other hand, when the
optimization process encounters a sensitive region, the step
should be shorten to avoid skipping the optimum [23].
First of all, the necessary parameters of the LNA circuit
for circuit simulation are loaded. By solving a set of
nonlinear ordinary differential equations, then the circuit
simulator will be performed for the circuit simulation and
specification evaluation. Once the specification meets the S-
parameter constraints, we output the optimized parameters.
Otherwise, we activate the GA for the global optimization;
in the meanwhile, the LM method searches the local optima
according to the results of the GA. We then call circuit
simulator to compute and evaluate newer results until the
specification is matched. This method is also run with
simulated annealing approach, of course, without using LM.
7. Simulation results
The LNA shown in Fig. 2 is designed in a 0.13µm
standard RFCMOS technology. The simulation of this LNA
is performed with the Advanced Design System (ADS)
tools. This LNA draws a current of 12 mA from the 1.2V
power supply. Fig. 6 and Fig. 7, indicate the input reflection
coefficient (S11) and the output reflection coefficient (S22),
respectively.
As it is shown in Fig. 8, The LNA has demonstrated
17.62 dB gain for forward transmission coefficient (S21) at
the peak gain frequency of 17.49 GHz with the 3-dB
bandwidth from 16.33-18.93 GHz. Fig. 8 points the reverse
reflection coefficient (S12) , that is about -30 dB in the worst
case. Figures 10-12 are based on GA optimized values.
 Stability is a very important issue for the LNAs. If a low and +23 dBm. Finally, simulated 1-dB compression point
noise amplifiers is not stable, it will become useless since (P1dB) is about -8 dBm.
major properties including bandwidth, gain, noise, linearity,
DC power consumption and impedance matching can be -20

significantly degraded. For this design, there is a good -30

Initial
stability (unconditionally stable) by employing the signal -40
flow theory and S-parameter, which show the Rollet’s

S12 (dB)
-50
factor, given by [22]: -60
GA
-70
2 2 2 SA
1 + ∆ − S 11 − S 22
K = (8) -80
2. S 12 . S 21 -90
10 12 14 16 18 20 22 24 26

Where ∆ = S11S22 – S12S21 Frequency (GHz)

The unconditional stability requirement of LNA is (K > 1) Fig. 9. Simulation of reverse transmission coefficient (S12).
and (| ∆ | < 1). It is shown in Fig. 10.
Fig. 11 illustrates the noise figure (NF) of LNA which 1.0 3.0
varies from 1.5 dB to 2.2 dB in the whole bandwidth. 0.8 2.5

Delta Magnitude
0
0.6 2.0

K
-5 0.4 1.5
S11 (dB)

GA 0.2 1.0
-10
SA
0.0 0.5
Initial
-15 10 12 14 16 18 20 22 24 26
Frequency (GHz)
-20
Fig. 10. Simulation of Rollet’factor for the cascode LNA.
10 12 14 16 18 20 22 24 26

Frequency (GHz) 8
Fig. 6. Simulated the input reflection coefficient of LNA.
Noise Figure (dB)

0 6
Initial
-5 4
S22 (dB)

-10 2

-15 0
SA 14 15 16 17 18 19 20
GA
-20 Frequency (GHz)
10 12 14 16 18 20 22 24 26 Fig. 11. Simulated the noise figure (NF) of the proposed LNA.
Frequency (GHz)
Fig. 7. Simulated the output reflection coefficient of LNA.

20

10
S21 (dB)

0
GA
-10
SA
&
-20
Initial
-30
10 12 14 16 18 20 22 24 26
Fig. 12. Simulation of the 3rd order intercept point.
Frequency (GHz)
Fig. 8. Simulation of forward transmission coefficient (S21).
As seen in Table I, the LNAs in [11] and [14] have better
Linearity of a circuit is determined by a factor called gains and in [12] and [15] have better power consumption
third-order intercept point (IP3) which is used as IP3 (IIP3) than this work at the cost of higher noise figure for the first
input or IP3 (OIP3) output. They are useful parameters to group and the cost of worse gain for the second group.
predict low-level intermodulation effects. Fig. 12 indicates
this factor. For this case, IIP3 and OIP3 are around +11 dBm
 TABLE I: Performance summary of the LNA and comparison with the existing papers
Ref.–Year Technology Topology FC S21 NF PIIP3 P1dB VDD Power
(GHz) (dB) (dB) (dBm) (dBm) (v) (mW)
[11]-2008 0.13µm Pseudo diff(2-stage) 18 22.4 4.1 -5.6 ----- 1.5 36
[12]-2006 0.13µm Cascode(1-stage) 26.2 8.4 4.8 -13 ----- 1 0.8
[13]-2006 0.09µm Cascode(1-stage) 20 8.4 3.1 +4.8 ----- 1.4 14
[14]-2007 0.09µm CS+Cascode(2-stage) 28.5 20 2.9 -7.5 -17 1 16.25
[15]-2005 0.09µm CS+CS(2-stage) 20 8 5.3 +3.8 ----- 0.66 11
[16]-2004 0.18µm CS+CS(2-stage) 24 13.1 3.9 -0.54 -12.2 1 14
[17]-2004 0.18µm CS+CS+CS(3-stage) 23.7 12.86 5.6 +0.24 -11.1 1.8 54
[18]-2005 0.13µm Diff cascode(2-stage) 20 9 5.5 -4 -11 1.2 24
This work 0.13µm Cascode(1-stage) 18 17.62 1.8 +11 -8 1.2 14

[7] C. H. Doan, et al., “Millimeter-wave CMOS design” IEEE Journal of

8. Conclusion
A 18 GHz, Low Noise Amplifier (LNA) has been designed
using 130 nm technology. In the designed LNA, the structure
of one-stage cascode amplifier with source inductive
degeneration is used. After that, two evolutionary and
statistical approaches are used for LNA. Based on genetic
algorithm (GA), simulated annealing (SA), the Levenberg-
Marquardt (LM), and circuit simulator, the simulation-based
methods simultaneously optimize the electrical specifications
such as S-parameters, the noise figure, and the input-referred
third-order intercept point in the process. The optimized
genetic algorithm simulation results show that the proposed
LNA has a noise figure of 1.8 dB in the 17.49 GHz frequency.
By employing the signal flow theory and the S-parameter, it
was found that, the LNA is unconditionally stable because of
Rollet’s Factor that is more than one, and magnitudes of (S11)
and (S22) are less than one. This LNA draws 12 mA from the
1.2V power supply. The LNA has demonstrated 17.62 dB for
S21 at the peak gain frequency of 17.49 GHz. For this circuit,
P1dB, OIP3, and IIP3 are -8 dBm, +23 dBm, and +11 dBm,
respectively.
Acknowledgment
The authors would like to thank the Education and Research
Institute for ICT (http://www.erict.ac.ir), for support of the
work.
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