NAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING Synchronous Counter Operation @term synchronous refers to events that have a fixed time relationship with each inchronous counter means that all the flip-flops in it are clocked at the same A 2-Bit Synchronous Binary Counter ° © This counte; ‘ent from the 2-bit synchronous counter by connecting both flip- flops directly to and making the FFO control the toggle operation of the FF1 Fig. (10) Shows, i r, While its timing diagram is shown in Fig. (11). HIGH Fig. (11) Timing diagram for the 2-bit synchronous counter. Digital Techniques IT 8 Dr. Ali Al-TemeemyNAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING A 3-Bit Synchronous Binary Counter it synchronous counter is shown in figure below, and its timing diagram is shown (13). \g to the sequence of states shown in table (3). The FF2 is work in toggle ae when Q0 and Q1 are high, therefore AND gate is used to perform this condiitio mic o Fro FR Iniilly ‘on ae) oro) 1 tear 2 Tie aloe) 3 o roo 4 cero! 5 ite eee 6 Par gree 7 Nigga Sores) | 0 00 Table. (3) Binary state sequance for a 3-Bit synchronous binary counter. Digital Techniques IT 9 Dr. Ali Al-TemeemyNAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING A 4-Bit Synchronous Binary Counter it synchronous counter is shown in figure below, and its timing diagram is shown (18). \g to the sequence of states shown in Fig. (15). The FF3, changes only twice wpfortion these two transitions will occur when QO, Q1, and Q2 are all High. © ThigfCondition is decoded by AND gate G2 so that when the clock pulse occurs, FF3 will change state. cH aK Fig. (14) -bifigynchi us counter Qe, QGP, 2,2, Qy2,2, Fig. (15) Timing diagram for the 4-bit synchronous counter. Digital Techniques IT 10 Dr. Ali Al-TemeemyNAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING A 4-Bit Synchronous Decade Counter it synchronous decade counter is shown in figure below, and its timing diagram in Fig. (17) @Fding to the sequence of states shown in table (4). when the counter reaches to 9 the toggle mode for FF3 and disable the toggle mode for the FF1 ® Thy conditions are enabled using the connection shown in Fig. (16). ere aera HIGH FFO FFL IF + is HH a 5 re bc c o Ky t CLK Fig. (16) Decade sy! onus counter. Fig. (17) Timing diagram for the decade synchronous counter. Digital Techniques IT n Dr. Ali Al-TemeemyWAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND CPTOELECTRONICS ENGINEERING Initially l --co mover ones | 9 Pg 19 ecycles) | Table. (4) 7. age ceqianceltar a 4-Bit synchronous decade counter. © The 74HC 163 is "2. counter. The logic diag! © This device has several featu * CLR’: synchronous reset. * LOAD’: counter load the data erHrooceosces Pease eee eooree ecific integrated circuit 4-bit synchronous binary 18) shows, this device with the pin number. ae to the basic functions. These features are: ingae inputs on the next clock pulse. » RCO: ripple clock output goes high When, unter reaches terminal count of fifteen. » ENP & ENT: enable input, must be bath hig| nable counter. Data Raputs Dy D, 3) |) |) | | CTR DIV 16 as) TC=15 |-——Rco lasyfa2|any Po 2% 2 Ka) Data outputs Fig. (18) The 74HC163 4-bit synchronous binary counter. Dugital Techniques I 2 Dr, Ah Al-TemeemyNAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING © Fig. (19) shows a timing diagram of this counter being preset to twelve (11002) and ‘then counting up to its terminal count, fifteen (11112). 1 ' J 1 a Outputs 4 al 1 I t { ' I 1 | Clear Preset Fig. (19) Timing diagram for the 4-bit binary synchronous count © The 74HC160 is an example of synchronous decade counter, which has tht inputs and outputs as the 74HC163. © It preset to any BCD count by the use of LOAD’ . The logic symbol for this | jown in Fig. (20) © Fig. (21) shows the timing diagram for the counter being preset to (0111). Digital Techniques I! B Dr. Ali AL-Temeemy‘NAERAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING Dy DB, DB, Dy CTR DIV 10 as exo RCO QQ, O Os @ 74HC160 synchronous decade counter. inputs ‘Outputs es ' sn & 3 | I Count ———*!+— Inhibit Fig. (20) Timing diagram for the synchronous decade counter. Digital Techmiques 12 4 Dr. Alt A-Temeemy