NAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING Asynchronous Counter Operation asynchronous counter is one in which the flip-flops within the counter do not inge states at exactly the same time, because they do not have a common Ick. ?* A 2-Bit Asynchronous Counter o Thig, counter consists from two flip-flops (FFO & FF1), with are connected for toggle operation (J= 1). The clock is connected to clock input of FFO, which is always 10’ of it is used to triggered FF1 which is the MSB as shown in Fig. (1). © The timing di (Titustrates the change in the flip-flops states is shown in Fig. (2). © This counter exhibits four diffe it states, 2°=4. @ The sequence of counts in table (1). represents a sequence of binary numbers is listed HIGH 2 Ourpurs 4 Qy (LSB) ' | Q, (MSB) Fig. (2) Timing diagram for a 2-Bit asynchronous Counter. Digital Techniques IT 1 Dr. Ali Al-TemeemyNAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENTOF LASER AND OPTOELECTRONKS ENGINEERING reyes Initially 0 0 1 0 1 2 1 0 1 a 4 (recycles) 0 0 Fi ble ary state se quance for a 2-Bit asynchronous Counter. Ze . A2-Bit bi Counter © A 3-bit asynchronous counter is Fig§(3-a). The basic operation is the sarne as that of 2-bit counter, except that the 3-b er has eight states, due to its three flip-flops: @ A timing diagram for eight clock pulses: ‘CO (3-b), and the counter sequence is listed in Table (2) Initially ° a 1 0 0 l 2 0 1 0 3 0 1 1 4 1 0 0 5 1 © 1 6 1 0 i 1 1 1 A (ieeycles) io 0 o Table. (2) Binary state se quance for a 3-Bit asynchronous Counter Digital Tecleriques If 2 Dy. Ali Al-TemeempNAHRAIN UNIVERSITY COLLECE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING 1G) —¢-—__—— ak—}-be mn © tee bt Le, O:(MSB) (by Fig. (3) (a) A 3-Bit Asynchron Ex. For the 4-bit asynchron HIGH. pe Qu sh cK Cc a © Fig. (4) (a) A 4-Bit Asynchronous Counter and (b) its timing diagram for one cycle. Digital Techriques I 3 Dr. Ali Al-TemveemyNAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING Asynchronous Decade Counter \dulus of a counter is the number of unique states that the counter will sequence lh. The maximum possible number of the states of a counter is 2", where n is lumber of the flip-flop in the counter. an also be designed to have a number of states in their sequence that is sithan the maximum of 2". The results sequence is called the truncated sequence. © One common modulus for the counter with truncated sequences is ten (called MOD‘0) © Counter with in their sequence (from zero [0000] through nine [1001]) are called Det ler as shown below. (note NAND used to reset counter at 10103). \), ; ae of. D* le HIGH 7 tien 7 © Fig. (4) (a) An Asynchronous decade Counter and (b) its timing diagram for one cycle. Digital Techniques IT 4 Dr. Ali Al-TemeemyNAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING Ex. Show how asynchronous counter can be implemented having a modulus of twelve with a straight binary sequence from 0000 to 10117 Sol E r flip-flops are required to get No. between 0000 and 1111. n the counter gets to its last state, 1011, it must recycle back to 0000 rather - to its normal state of 1100, as illustrated in figure below. ® O% B® % + cee 2 : : Recycles fi ea d; 1 QO = <— Normal next state ig. 6) Al he Counter states. * From Fig. (6), Q2& Q3 is use he inter by using NAND Gate as showin Fig. 3 Fig.6. 12 decoder [ > (@ Fig. (6-a) An Asynchronous Modulus-12 Counter. Digital Techniques 11 5 Dr. Alt AL TemeerayNABRADI UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOBLECTRONICS ENGINEERING aT LeU eee ee i | : l = t r ' r = = ' | I it ' ' \ Gatch | os 1 1d - Py 1 1 1 1 2, | Ls i Decoder botpat (CLR) » Fig. (6-b) An As\ lous Modulus-12 Counter recycling. © The 74LS93A is an example ic integrated circuit asynchronous binary counter. As the logic diagram it ) shows, this device consists of a single flip- flop and a 3-bit asynchronous is Make it used as: * Divider by 2 if single FF is used. Modulus-8 counter if the three FFs is u * Modulus-16 counter by connecting Q0to C| (see Fig. 8-a). * Decade counter Modulus-10 by using gat inputs. (see Fig. 8-b). D te CLK B CLK A——— 2, % 2% (LSB) a ) Fig. (7) The 74LS93A 4-bit Asynchronous binary Counter. Digital Techniques IT 8 Dr. Ali Al-TemoemyNAHRAIN UNIVERSITY COLLEGE OF ENGINEERING DEPARTMENT OF LASER AND OPTOELECTRONICS ENGINEERING Cc CTRDIVI6 CLK A ——o>cC CTRDIV 10 e CLK B —eo> ¢ ROf1) —» RO;2) Sai ° o 2, 2 Os Q @, 2, @, (a) 74LS934 fa modulus-16 counter (b) 74LS93A connected as a decade counter Fig. (8) Tow sonfi ‘ation of 74LS93A 4-bit Asynchronous binary Counter. Ex. Show how the74693A can be used as a modulus-12 counter? Solution: Digital Techniques 1 1 Dr. Ali A-Temeemy