EEC 3111 - D IGITAL E LECTRONICS IN

C OMMUNICATION S YSTEMS

Dr. Hussein Seleem, PhD

Electronics Engineering and Electrical Communications Department
Faculty of Engineering, Tanta University, Tanta, Egypt

Lecture 4: Digital ICs Logic Families (continued)

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O UTLINE

1 CMOS S ERIES C HARACTERISTICS

2 O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

3 T RISTATE (T HREE -S TATE ) L OGIC O UTPUTS

4 T HE EMITTER - COUPLED LOGIC (ECL) FAMILY

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 CMOS S ERIES C HARACTERISTICS

P OWER D ISSIPATION

Each time a CMOS output Current spikes are drawn from VDD each time the
switches from LOW to HIGH, a output switches from LOW to HIGH.
transient charging current must be
supplied to the load capacitance.
The combined input capacitances
of any loads being driven and the
device’s own output capacitance.

For example, a CMOS NAND gate

that has PD = 10 nW under DC
conditions will have PD = 0.1 mW
at a frequency of 100 kpps, and 1
mW at 1 MHz.

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 CMOS S ERIES C HARACTERISTICS

FAN -O UT

1 CMOS inputs have an extremely large

resistance that draws essentially no
current from the source (1012 Ω ).
2 Each CMOS input, typically presents a
5-pF load to ground.
3 This input capacitance limits the number
of CMOS inputs that one CMOS output
can drive.
4 Although CMOS must drive relatively
large load capacitances, switching speed
is somewhat faster, due to low output
resistance in each state.
5 In CMOS circuit, output resistance in
HIGH state is the RON of P-MOSFET
(Typically 1k Ω or less).

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 CMOS S ERIES C HARACTERISTICS

S TATIC S ENSITIVITY

All electronic devices, to varying degrees, are sensitive to damage by static electricity.
MOS logic families are especially susceptible.

P RECAUTIONS AGAINST E LECTROSTATIC DISCHARGE (ESD)

1 Connect chassis of all test instruments, soldering-iron tips, and your metal
workbench to earth ground.
2 Connect yourself to ground with a special wrist strap.
3 Keep ICs in conductive foam or aluminum foil. So no dangerous voltages
develop between any pins.
4 Avoid touching IC pins by inserting it into the circuit immediately after removing
from the protective carrier.
5 Place shorting straps across the edge connectors of PC boards when the boards
are carried/transported and avoid touching the edge connectors.
6 Do not leave any unused IC inputs unconnected. Open inputs tend to pick up
stray static charges.

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 CMOS S ERIES C HARACTERISTICS

S WITCHING S PEED

1 Unavoidable existence of parasitic (unwanted) PNP and NPN transistors

embedded in CMOS substrate can cause a condition called latch-up.
2 If triggered, they will latch-up (stay ON permanently), and a large current will
destroy the IC.
3 Most modern CMOS ICs are designed with protection circuitry that helps prevent
latch-up
4 It can still occur when the device’s maximum voltage ratings are exceeded.
5 Latch-up can be triggered by high-voltage spikes or ringing at the device inputs
and outputs.

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 CMOS S ERIES C HARACTERISTICS

L OW VOLTAGE T ECHNOLOGY

M AJOR B ENEFITS FROM INCREASED CHIP DENSITY

1 It allows more circuits to be packed onto the chip;
2 With circuits closer together, the time for signals to propagate from one circuit to
another will decrease.

D RAWBACKS OF HIGHER CHIP DENSITY

1 When circuits are closer together, insulating material that isolates one circuit
from another is narrower.
2 So it decreases the amount of voltage that the device can withstand before
dielectric breakdown occurs.
3 power dissipation increases, which can raise chip temperature above maximum
for reliable operation.

The drawbacks can be neutralized by operating the chip at lower voltage levels,

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 CMOS S ERIES C HARACTERISTICS

L OW VOLTAGE T ECHNOLOGY

S EVERAL LOW- VOLTAGE CMOS (LVC) SERIES ARE CURRENTLY AVAILABLE :

1 74LVC series contains widest assortment of SSI/MSI functions of 5V families.
2 74ALVC (Advanced LVC) offers the highest performance.
3 74LV offers many SSI/MSI functions & some popular octal buffers, latches, FFs.
4 74AVC (Advanced Very LVC) is optimized for 2.5V systems. It has many
interface features of BiCMOS that will make it useful in future generations.
5 74AUC (Advanced Ultra LVC) is optimized to operate at 1.8-V logic levels.
6 74AUP (Advanced Ultra-low Power): used in battery-operated portable apps.
7 74CBT (Cross Bar Tech.): high speed bus interface that can switch quickly.
8 74CBTLV (Cross Bar Tech. LV): 3.3V complement to the 74CBT series.
9 74GTLP (Gunning Transceiver Logic Plus) for high speed parallel backplane.
10 74SSTV (Stub Series Terminated Logic) in high speed advanced-memory sys.
11 TS Switch for mixed-signal apps & offers some switching & MUX solutions.
12 74TVC (Translation Voltage Clamp) protect in/out from voltage overshoot.

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 CMOS S ERIES C HARACTERISTICS

L OW VOLTAGE T ECHNOLOGY

B I CMOS FAMILY

1 74LVT (Low-Voltage BiCMOS Technology) contains BiCMOS parts intended for

8- and 16-bit bus-interface applications. Because output levels [VOH (min) and
VOL (max)] are equivalent to TTL levels, they are fully electrically compatible with
TTL.
2 74ALVT (Advanced Low-Voltage BiCMOS Technology) series is an improvement
over the LVT. It offers 3.3-V or 2.5-V operation at 3 ns, pin-compatible with ABT
and LVT, also intended for bus-interface uses.
3 74ALB (Advanced Low-Voltage BiCMOS) is designed for 3.3-V bus-interface
applications. 25 mA output drive & propagation delays of only 2.2 ns.
4 74VME (VERSA Module Eurocard) series is designed to operate with the
standard VME bus technology.

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 CMOS S ERIES C HARACTERISTICS

L OW VOLTAGE T ECHNOLOGY

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 CMOS S ERIES C HARACTERISTICS

L OW VOLTAGE T ECHNOLOGY

Continued development of low-voltage technology promises a

complete revolution from the original 5-V system, to pure 3.3-V, 2.5-V,
or even lower-voltage digital systems.

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 O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

Conventional CMOS or TTL totem pole outputs should never be
connected to the same point.

Two outputs contending for control of a wire.

One solution to problem of sharing common wire among gates is to remove the active
pull-up transistor from each gate’s output circuit. So, none of the gates will ever try to
assert a logic HIGH.

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 O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

TTL/CMOS outputs modified this way are called open-collector/drain

outputs.

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 O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

Wired-AND operation using open-collector gates.

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 O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

...
1 A common use of open-collector/drain outputs is as a buffer/driver.
2 Logic circuit designed to have a greater output current and/or voltage capability
than an ordinary logic circuit.
3 They allow a weaker output circuit to drive a heavy load.

An open-collector buffer/driver drives a high-current, high-voltage load.

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 O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

Open-collector/drain outputs are often used to drive indicator LEDs.

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 O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

O PEN C OLLECTOR /O PEN D RAIN O UTPUTS

IEEE/ANSI symbology uses a distinctive notation to identify

open-collector/drain outputs.

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 T RISTATE (T HREE -S TATE ) L OGIC O UTPUTS

T RISTATE (T HREE -S TATE ) L OGIC O UTPUTS

1 It has high-speed operation of pull-up/pull-down output arrangement.

2 While allowing outputs to be connected together to share a common wire.
3 Tristate: allows three possible states HIGH, LOW, and high-impedance (Hi-Z).
4 Hi-Z is a condition in which both pull-up & pull-down transistors are turned OFF.
5 Output terminal is a high impedance to both ground and power supply.
6 Devices with tristate outputs have an enable input (OE).
7 When OE = 1, It is normal INVERTER and output will be either HIGH or LOW,
depending on input level.
8 When OE = 0, output is disabled (Hi-Z state) both transistors in nonconducting
state. Output is an open circuit (not connected to anything).

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 T RISTATE (T HREE -S TATE ) L OGIC O UTPUTS

T RISTATE (T HREE -S TATE ) L OGIC O UTPUTS

1 Outputs of tristate ICs can be connected

together without sacrificing switching speed.
2 When tristate outputs are connected together,
only one of them should be enabled at one
time.
3 Two active outputs could fight for control of
the common wire.
4 Many ICs are designed with tristate outputs.
74LS374 is an octal D-type FF register IC with
tristate outputs.
5 A tristate buffer is a circuit used to control the
passage of a logic signal from input to output
6 Some tristate buffers invert the signal as
passes.

Tristate noninverting buffers.

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 T RISTATE (T HREE -S TATE ) L OGIC O UTPUTS

T RISTATE (T HREE -S TATE ) L OGIC O UTPUTS

IEEE/ANSI symbology to identify tristate outputs.

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 T HE EMITTER - COUPLED LOGIC (ECL) FAMILY

T HE EMITTER - COUPLED LOGIC (ECL) FAMILY

1 It operates on the principle of current

switching.
2 A fixed bias current less than IC (sat)
is switched from one transistor’s
collector to another.
3 It is also referred to as current-mode
logic (CML).
4 Basic ECL circuit is differential
amplifier
5 It produces complementary outputs:
VOUT 1 , equal to V̄IN , and VOUT 2 ,
equal to VIN .

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 T HE EMITTER - COUPLED LOGIC (ECL) FAMILY

ECL OR/NOR G ATE

The basic ECL circuit can be used as an INVERTER if the output is
taken at VOUT 1 .
ECL CHARACTERISTICS :
1 Very fast switching with typical
propagation delay of 360 ps,
faster than TTL or CMOS.
2 Standard ECL levels are
nominally -0.8 V and 1.7 V for
logical 1 and 0 respectively.
3 Worst-case noise margins
approximately 150 mV.
4 ECL logic gates usually produce
an output and its complement,
eliminating the need for inverters.
5 Current flow remains constant,
eliminating noise spikes

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