IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO.

12, DECEMBER 2016 4701

60-GHz 64- and 256-Elements Wafer-Scale

Phased-Array Transmitters Using
Full-Reticle and Subreticle
Stitching Techniques
Samet Zihir, Member, IEEE, Ozan Dogan Gurbuz, Member, IEEE, Arjun Kar-Roy, Member, IEEE,
Sanjay Raman, Fellow, IEEE, and Gabriel M. Rebeiz, Fellow, IEEE

Abstract— This paper presents 60-GHz wafer-scale transmit

phased arrays with 64- and 256-elements spaced λ/2 apart in the
x- and y-directions, and occupying an area of 21.4 × 22 mm2
(471 mm2 ) and 41.4 × 42 mm2 (1740 mm2 ), respectively. The
64-element phased array is built as a complete reticle and includes
64 independent transmit channels with 5-b phase control,
3-b (9 dB) amplitude control, a saturated output power of 3 dBm
at the antenna port, a 1–64 distribution network with redundant
line amplifiers, and a high-efficiency on-chip antenna at each
element. In addition, redundant serial digital interface and power
strips, dual series metal–insulator–metal capacitors, and multiple
RF inputs are employed for improved yield. The 256-element
array uses the same phased-array blocks as the 64-element
design, but is built using a subreticle stitching technique so as
to result in a chip which is larger than the standard reticle size
(22 × 22 mm2 ). The 64- and 256-element arrays result in a
half-power beamwidth of 12° and 6° in the E- and H-planes,
a directivity of 23 and 29 dB, respectively, and scan to ±55°
in the E- and H-planes with near-ideal patterns and a cross-
polarization level of lesser than −30 dB. The measured equivalent
isotropically radiated power (EIRP) of the 64-element array is
38 dBm at 62 GHz with a 3-dB bandwidth of 61–63 GHz, while
that of the 256-element array is 45 dBm at 61 GHz with a 3-dB
beamwidth of 58–64 GHz. A 1–4-Gb/s communication system is
also demonstrated using the 64-element phased array up to ±45°
scan angles, and at 4-, 30-, and 100-m ranges. To the best of our
knowledge, this paper represents the first demonstration of large
size (64- and 256-element) phased-array transmitters on a single
wafer.
Index Terms— Antenna array, communication link, 5G,
Fig. 1. (a) Phased array based on a small silicon chip on an interposer and
millimeter-wave (mm-wave) circuits, on-chip antennas, phased
multilayer PCB. (b) Wafer-scale phased array.
arrays, SiGe, 60 GHz, subreticle stitching, transmitter, wafer-
scale array.
I. I NTRODUCTION
Manuscript received July 4, 2016; revised September 28, 2016; accepted
October 25, 2016. Date of publication November 17, 2016; date of current
version December 7, 2016. This work was supported by the DARPA MTO
DAHI Program, Daniel Green Program Monitor. An earlier version of this
paper was presented at the IEEE MTT-S International Microwave Symposium,
T HE development of silicon-based phased arrays has
advanced at a very fast pace since its introduction in
the mid-2000s. Silicon core chips provide a high level of
San Francisco, CA, USA, May 22–27, 2016. integration and yield, thus allowing many elements on the
S. Zihir and G. M. Rebeiz are with the Department of Electrical and same chip, and have been demonstrated from 6 GHz to
Computer Engineering, University of California at San Diego, La Jolla,
CA 92093 USA (e-mail: szihir@ucsd.edu; rebeiz@ece.ucsd.edu). >100 GHz on a variety of chips [1]–[37]. Furthermore, the
O. D. Gurbuz is with Analog Devices Inc., Beaverton, OR 97006 USA digital control and transceivers can also be incorporated on the
(e-mail: ogurbuz@ucsd.edu). same chip, allowing for a complete system-on-chip solution
A. Kar-Roy is with Jazz Semiconductor, Newport Beach, CA 92660 USA
(e-mail: arjun.karroy@towerjazz.com). especially at millimeter-wave (mm-wave) frequencies. All-
S. Raman is with the Virginia Polytechnic Institute and State University, RF beamforming [3], [4], [7]–[10], [13], [26], [29]–[35],
Blacksburg, VA 24061 USA (e-mail: sraman@vt.edu). IF beamforming [6], [27], [36]–[38], LO beamforming [2],
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. and digital beamforming [11], [28] were all proposed, and
Digital Object Identifier 10.1109/TMTT.2016.2623948 the All-RF beamforming has been adopted by industry, since
0018-9480 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
4702 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 12, DECEMBER 2016

it eliminates the use of a mixer on every element while

achieving improved performance in the presence of high-level
in-band and out-of-band blockers [8], [10], [13], [16], [17],
[26], [30], [34]. The silicon chips and their implementation
with antenna arrays have been demonstrated at X to Q-band
phased-array systems, 60-GHz communication systems,
77-GHz automotive radars, 94-GHz radars, and a variety of
other systems.
Phased arrays at mm-wave frequencies (60 GHz and above)
suffer from interconnect loss between the silicon chip RF ports
and the antenna elements [Fig. 1(a)]. For a 16-element chip,
a complex distribution network in a multilayer printed-circuit
board (PCB) is used with an average loss of 2 dB at 60 GHz.
Also, industry has typically chosen to build chips as small as
possible, thus lowering the cost of the silicon chip. However,
such chips require a bump spacing of 100–200 μm for the
RF ports and control pins, which forces the chip to be
placed on yet another multilayer organic or ceramic substrate
(interposer) to distribute the chip ports to a ball-grid array of
400–500 μm pitch, with an additional 1–2 dB distribution loss.
Therefore, it is not uncommon to result in a total transition
loss of 3–4 dB between the silicon chip RF port and the
antenna port at mm-wave frequencies. This is present in
both the transmit and receive paths, and results in a 6–8 dB Fig. 2. (a) Cross section of the Jazz SBC18H3 process technology.
(b) Measured CPW transmission-line loss and simulated/measured transistor
system loss in a communication or radar application. fT including interconnects to the top metal layer.
In addition, the multilayer organic boards are expensive to
build and hard to design, thus adding to the system cost and
complexity. used for improved yield are presented in detail. As will
We have proposed the use of wafer-scale phase arrays in be seen, redundancy is an integral part of the wafer-scale
order to eliminate the transmission-line loss and result in design to improve the yield. This paper also presents full
a complete system on a single silicon wafer, as shown pattern measurements, and communication system measure-
in Fig. 1(b) [11], [22]. In this approach, the phased-array ments done with up to 100-m distances and gigabit per
channels are placed on a λ/2 grid on the silicon chip and second link with 16-QAM modulation. The second main part
connected to high-efficiency on-chip antennas, thus eliminat- presents the extension of this paper to a size larger than a full
ing the distribution loss as in the traditional design. The reticle and 256-element (16 × 16) wafer-scale phased array is
RF distribution networks are built on the silicon chip, and demonstrated.
the digital control module is also integrated on-chip using the
II. S YSTEM AND F EED N ETWORK D ESIGN
CMOS transistors in the BiCMOS technology. In addition,
baseband-to-RF transceivers can be integrated on-chip at the A. Technology
array or subarray level, and the chip can be placed on a low- The TowerJazz SBC18H3 SiGe BiCMOS process is used
cost board, since it requires only the baseband (or IF signals), in this paper (Fig. 2). This technology has six metal layers
crystal reference signal (for the local oscillator), and digital (M1 to M6) and employs 0.13-μm SiGe bipolar transistors
control. The penalty paid in the wafer-scale approach is a with an f T and f MAX of 220–230 GHz, respectively, when
large chip size and inefficient use of the silicon area. However, referenced to the top metal layer [39]. It also comes with
knowing that this design eliminates 3-4 dB of distribution loss, 0.18-μm CMOS transistors, which are used for digital control,
a lower number of antenna elements (0.5–0.4 times) is required memory, and biasing. A 50- CPW transmission line has a
to result in the same array gain, and equivalent isotropically measured loss of 0.9 dB/mm at 60 GHz, which results in an
radiated power (EIRP) as the traditional design, and thus a transmission line Q of 18. The SBC18H3 process has been
smaller overall wafer-scale phased array. Also, the design can used extensively in the microwave and mm-wave design.
be extended to entire 200 or 300 mm wafers, resulting in low-
cost phased-arrays with thousands of elements. B. Block and Control Diagram
This paper presents the first 64-element (8 × 8) and Fig. 3 shows the block diagram of the 64-element
256-element (16 × 16) 60-GHz wafer-scale phased-array phased-array transmitter. It consists of four 16-element
transmitters based on full reticle design (22 × 22 mm2 ) phased-array subblocks with a distribution network and line
and on subreticle stitching, and is an expanded version of amplifiers (LAs), and each with its own local serial-peripheral-
papers [32], [33], [37]. The first main part of this paper interface (SPI) controller and a local proportional-to-ambient-
presents the overall system design for the 64-element array temperature (PTAT) current source. The local SPI module
channel design and antenna design, and different techniques controls the gain and phase of each channel in the 16-element
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS 4703

Fig. 3. Block and control diagram of the 64-element chip with four 16-element subarrays.

Fig. 4. Detailed view of the 64-element chip with four 16-element subarrays.

subarray, the LA gain in the subarray distribution network,

and the bias-current level for the subarray (the PTAT reference
current can be controlled by ±30%). An external bias pin is
also present for each subarray for additional current control.
Finally, a master SPI module (a generic microcontroller)
controls each 16-element subarray SPI block.
Each SPI module has several redundant features, which
include one 4-wire SPI control, 4-b address control, one
4-wire redundant SPI control, 10 redundant parallel inputs, and
Fig. 5. (a) Differential Wilkinson divider and (b) BC: layout and simulations.
electrostatic discharge protection and power clamp circuitry. The BC is symmetrical and results in a wideband 90° phase shift between the
This is all implemented in the 0.18-μm CMOS process and two different ports.
SPI interface can run up to 50 MHz (clock frequency) with
no simulated errors over the entire chip.
distribution network on the silicon chip with embedded LAs.
This large network has two RF feeds at the edge of the chip
C. Feed Network Design: Redundancy (to the left and right) for redundancy (Red. RFIN in Fig. 4) in
Fig. 4 shows a detailed view of the 64-element (8 × 8) case one LA in the feed network fails. This necessitates the
feed network. The four 16-element subarrays are fed using a use of an isolated four-port network at the center of the chip,
4704 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 12, DECEMBER 2016

Fig. 6. Distribution loss and P1dB at different locations in the network at 60 GHz.

and a 0°–90° branchline coupler (BC) is selected. The use of

the BC results in some subarrays being at ±90° from each
other, but the phase shifters at the element level can add ±90°
to the required phase at each element to compensate for this
fixed phase shift. The rest of the power dividers are based on
three-port Wilkinson networks.
Note that each of the 16-element subarrays also has two
RF feeds: one feed is attached the main on-chip distribution
network and the other feed is taken to the edge of the chip
for additional redundancy. These additional subarray RF feeds
can be connected to an external 1:4 distribution network in
case one (or several) LAs in the main on-chip feed network
fails, and ensures a higher yield for the array.

D. Feed Network Details: Wilkinson and Hybrid

Networks and Redundant Line Amplifiers
The entire feed network is based on differential
GSSG lines (10/8/8/8/10 μm) with a loss of 0.9 dB/mm at
60 GHz (Fig. 2). A single-ended to differential transformer
is used at all RF ports at the edge of the chip, and
differential 0°–90° BC and Wilkinson couplers are employed
everywhere in the feed network. Fig. 5 shows the layout
and simulated performance of the different components, with
the BC and Wilkinson divider having a division loss of
4.3 ± 0.4 and 4 dB, respectively, at 60 GHz. The BC results
in 90 ± 1° phase difference at 56–64 GHz (measurements on
single-ended Wilkinson and BC agree well with measurements
and are not shown for brevity). The loss of the feed network
Fig. 7. LA with a redundant branch. (a) Block and circuit diagram.
from the common RF port to the input of every channel (b) S11 and S22 for different modes.
is simulated as shown in Fig. 6 and takes into account the
transmission-line lengths, three BCs, and three Wilkinson
dividers. The simulated loss is 43 dB at 60 GHz and is entire chip, or a quadrant of the chip. One way to achieve this
divided as 18-dB power division loss and 25-dB ohmic loss. is to use an SPDT switch and two LAs, but the yield problem
This ohmic loss, in turn, is composed of 7-dB excess loss is then shifted to the SPDT switch and is not improved.
due to the BC (1.3 dB per device) and Wilkinson couplers We decided to use two LAs in parallel with each other and
(1 dB per device), 1.5 dB for the input balun, and 16.7 dB tied together using T-junctions at the input and output ports.
of ohmic transmission-line loss (a total length of 18.6 mm). In normal operation, only one amplifier is turned ON, and if
Three amplifiers, each with 15-dB gain, are placed in the it fails (as an open circuit), then the other amplifier can be
distribution path to compensate for the 43-dB loss and result used (mode 01 or mode 10). An added bonus is that if the
in a distribution-network net gain of 2 dB at 60 GHz. The LA gain is low, or if added gain is needed in the distribution
LAs are designed with an output P1 dB and PSAT network, then the two amplifiers can be turned ON together
of 0 and 2 dBm, respectively, and consume 40 mW for additional gain (mode 11).
each. A total of 21 LAs are used in the distribution network A key issue is to design the input and output matching net-
with a power consumption of 840 mW. works, such that they operate well in modes (01, 10, and 11).
The LA is shown in Fig. 7(a). A major design consideration In the case of mode 01 and 10, the circuit is identical as long as
was that this amplifier be redundant in itself, since a failure the primary and redundant transistors are the same size. In the
or a yield issue in this block can affect the operation of the case of mode 11, the transistor size doubles to 2 × 6 μm,
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS
Fig. 8. (a) Breakout of the LA. (b) Measured S-parameters and output power
for different modes.
affecting both the input and output impedances [Fig. 7(b)].
A capacitor–inductor–capacitor matching network at the input
port and a resistor–inductor–capacitor matching network at the
output port can effectively match both impedances with a small
shift in frequency [Fig. 7(b)]. Note that it is essential to use
a cascode design so as to have a very low S12 (−30 dB at
60 GHz) and to reduce the effect of output-to-input feedback
and matching network interaction.
Measurements on a breakout amplifier [Fig. 8(a)] show that
the amplifier can operate well in all modes with an S11 and
S22 less than −8 dB, and a gain of 17–15 dB at 57–60 GHz in
modes 01, 10, and 11 [Fig. 8(b)]. The LA also operates well
in mode 11 with a gain of 22 dB at 60 GHz. There is a small
shift in frequency between simulations and measurements due
to the metal–insulator–metal (MIM) capacitor model in the
design kit (this is now fixed in the current design kit).
The feed network is simulated using the measured
S-parameters of the LAs together with the simulated
S-parameters of the BCs, Wilkinson dividers, and transmission
lines, and all 64 paths are shown in Fig. 9. At 60 GHz,
the distribution gain, defined as power available per channel
divided by the available input power, is 2 ± 1.2 dB for all
64 paths. The ±1.2 gain variation is due to the BC each having
±0.4-dB difference in their S-parameters. Such a uniformity
in distribution network is not possible using PCBs at 60 GHz,
especially when PCB vias and transitions to the LAs are used.
The peak distribution gain is 13 dB at 55 GHz, since the
measured LA response shifted to 55 GHz. Note that since
three identical LAs are used, the distributed gain drops quickly
to −15 dB at 65 GHz, since each LA gain drops to 9 dB
at this frequency (from 15 dB at 60 GHz). In the future, it
4705
Fig. 9. Simulated distribution network gain from the common RF port to
the input of each channel (64 channels).
would be best to design wideband LAs or stagger the LAs
in their frequency response so as to avoid this penalty in the
distribution gain.
The input return loss at the common RF port is less
than −7 dB at 55–65 GHz and is determined by the input
balun, and the output is well matched at every output port
(S22 < −15 dB, given by the Wilkinson divider). An input
power of −15 dBm at the common RF port dBm and a distri-
bution gain of 2 ± 1.2 dB at 60 GHz results in −13 ± 1.2 dBm
at the input of each phased-array channel at 60 GHz.
E. Additional Redundancy: MIM Capacitors
and PCM Modules
One additional failure mode in the wafer-scale array is a
short circuit in MIM capacitors, which are used throughout
the chip for bias decoupling. In operation, catastrophic failure
occurs when these capacitors breaks down due to a short
circuit, which limits the yield in large-scale chips. In order
to solve this problem, bias-decoupling MIM capacitors are
always placed in series, and in this case, two capacitors must
fail as short circuits together in order for a major dc short
to occur. This reduces the capacitance density by half, but is
acceptable due to the large available area.
Also, since this is an entire reticle, space is left open for
process-control modules as required by TowerJazz. These are
placed far away from the channel and transmission lines and
have no effect on the phased-array operation.
In conclusion, redundancy and improved yield is achieved
using dual-LAs, external and internal bias control for every
16-element subarray, dual SPI (vertical and horizontal), addi-
tional parallel data inputs, dual MIM capacitors and multiple
VDD inputs, and several redundant RF inputs throughout the
chip.
III. P HASED A RRAY C HANNEL
The phased-array channel consists of a vector-modulator
based phase shifter, variable gain amplifier (VGA), and a
power amplifier (PA) for driving the differential antenna
(Fig. 10). The vector modulator consists of an I/Q network
based on differential λ/4 coupled lines and followed by two
gain-controlled amplifiers, which are current summed at their
outputs [Fig. 10(a)] [21], [25]. CMOS switches are used to
control the polarity of the I/Q signals in the vector modulator.
A 5-b phase response is achieved using 5-b DACs attached to
4706 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 12, DECEMBER 2016
Fig. 10. (a) Vector-modulator-based phase shifter. (b) VGA and PA circuits.
the current mirrors at the tail of the differential amplifiers. The
phase shifter results in a simulated gain of 2 dB at 60 GHz
with a 3-dB bandwidth of 7 GHz, for a current consumption
of 10 mA. The simulated rms gain and error are ≤1.2 dB
and ≤9° at 57–63 GHz, respectively.
The VGA and PA are codesigned together for a peak gain
of 16 dB, and both employ differential cascode amplifiers.
The VGA uses a current-steering technique with a 3-b DAC
and a gain control of 9 dB [Fig. 10(b)]. The gain control
compensates for the gain variation in the phase shifter and
allows for a 6-dB amplitude taper to be placed on the array.
The VGA phase changes by <3° over a 3-dB gain control
range, thus allowing the user to compensate for the gain
variation in the phase shifter without any additional phase
calibration. The PA is designed to be in a class A mode with a
simulated output P1 dB and PSAT of 1 and 5 dBm, respectively,
and consumes 40 mW.
Fig. 11. Measured and simulated phased-array channel. (a) Channel details
with microphotograph. (b) Gain and phase response versus 32 phase states.
(c) Gain response with VGA control and output power.
Fig. 11 shows the measured phased-array channel.
Breakouts for the different components are not shown due
to brevity. Note that transformers are used at the input and
output ports to make the measurement single-ended and their
loss is deembedded from the measured results (1.5 dB each)
[Fig. 11(a)]. The measured channel phase response versus
frequency shows a peak gain of 18 dB and an rms gain error
is <1.2 dB at 52–68 GHz. The rms phase error is <8° up
to 64 GHz and is <5.5° at 57–61 GHz showing a 5-b phase
response [Fig. 11(b)]. The channel is wideband with a 3-dB
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS 4707

Fig. 13. Simulated active impedance versus scan angle at 60 GHz using
master–slave boundary conditions in a 2-D phased array.

Fig. 12. High-efficiency differential dipole antenna. (a) Cross section and
top view. (b) Simulated S11 , gain, radiation efficiency, and patterns.

bandwidth of 56–67 GHz. The measured OP1 dB and PSAT are

0 and 3 dBm, respectively, at 60 GHz [Fig. 11(c)]. The PSAT
values are achieved at an input power of −11 to −12 dBm
showing a channel saturated gain of 14–15 dB. There is good
agreement with simulations. The channel consumes 95 mW
from a 2.5 V supply.

IV. H IGH -E FFICIENCY D IFFERENTIAL D IPOLE A NTENNA

The high-efficiency antenna is based on a differential dipole
and is similar to the design shown in [22], [40]. A 100-μm
quartz superstrate is used on top of the silicon wafer and
M1–M4 are employed as the ground plane for the dipole
and cover all the area around the antenna [Fig. 12(a)].
The dipole layout shown in Fig. 12(a) meets all the SiGe
design rules (DRC) and hundreds of isolated metal squares
(22 × 22 μm 2 ) are placed on layers M5 underneath the
antenna and wide transmission lines. These have virtually
no effect on the antenna performance as long as they are
placed 50 μm away from the differential antenna feed edges.
A wide differential feed is used underneath the antenna at
the M6 layer, and the simulated dipole impedance using
Ansoft-HFSS is 1-j9  at the dipole apex. The dipole
impedance is transformed to 50  using a quarter-wave line
at M6 with an impedance of 9  (microstrip transmission line
with a width of 110 μm).
The simulated differential dipole results in a directivity
of 6 dB at 60.5 GHz, an efficiency of 50%, and a gain
of 3 dB [Fig. 12(b)]. The 3-dB gain bandwidth is 59–62 GHz.
The patterns show a 3-dB beamwidth of 100° in both the
E- and H -planes when placed in a 2-D array.
Fig. 14. (a) System-level setup and (b) simulated gain, EIRP, and radiated
power based on measured S-parameters for the phased-array element and
for LAs.
The mutual coupling between the dipole antennas spaced
at 2.5 mm apart is simulated to be less than −23 dB in both the
E- and H -planes at 55–65 GHz, and drops to less than −45 dB
for far-away antennas. The low mutual coupling is due to
the proximity of the ground plane to the dipole antenna
(λd /40), which greatly reduces the T M0 mode excitation. The
simulated active antenna impedance versus scan angle in the
φ = 0°, 45°, and 90° (E-, Diagonal, and H -) planes is shown
in Fig. 13 at 60 GHz and remains within the −10 dB VSWR
circles up to ±60° scan angles in all planes (markers are
placed every 20°). This is done using master–slave bound-
ary conditions in Ansoft HFSS. The wafer-scale 64-element
4708 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 12, DECEMBER 2016
Fig. 15. (a) Picture of the wafer-scale phased-array chip with a quartz
superstrate and as delivered on a 200-mm wafer. (b) Expanded view of the
64-element array with (quadrants A, B, C, and D are labeled).
array (8 × 8) has a directivity of 23 dB at broadside and
drops as cos(θ ) versus scan angle. The 3-dB beamwidth is 12°
at broadside and increases as 1/cos(θ ) versus scan angle. The
simulated phased-array patterns are shown in the measurement
section.
V. P HASED -A RRAY S YSTEM -L EVEL S IMULATIONS
The wafer-scale phased array is simulated with ADS using
the measured S-parameters obtained for the different blocks,
and including the simulated antenna impedance and gain.
The array electronic gain, defined as the available power per
channel at the antenna input divided by the input power, is
shown in Fig. 14 and its bandwidth is determined by the
distribution network as discussed in Section II. The available
power per element is 3 and 0 dBm at PSAT and OP1 dB ,
respectively, and results in a array EIRP of 41 dBm (PSAT )
and 39 dBm (P1 dB), at broadside. All values are at 25 °C.
The entire array consumes 7 W from a 2.5 V supply (2.8 A),
and the power is divided as 850 mW for the LAs, and 6.1 W
for the channels (64 × 95 mW at PSAT ). The digital control
consumes <10 mW of power in the static mode. There are
several VDD inputs on the top and bottom of the chip, and
M5 (1.2 μm thick) and M3 (0.62 μm thick) are used for wide
Fig. 16. (a) Wafer-scale phased array on an FR-4 substrate and
(b) measurement station.
VDD strips over the entire chip, except under the antennas,
channels, and transmission lines. The voltage drop to the
center element is at <0.1 V knowing the resistivity of layers
M5 and M3.
VI. M EASUREMENTS : PATTERNS AND EIRP
The 64-element full-reticle wafer-scale phased array
(21.4 × 22 mm2 ) is shown in Fig. 15(a) together with an
expanded view of the chip, as shown in Fig. 15(b). An 8-in
SiGe BiCMOS wafer resulted in 45 wafer-scale reticle-size
phased arrays and the dc yield was 85%–90%. The wafer was
not thinned and its thickness is 750 μm (30 mil), and has
not effect on the phased-array performance. Note that there
is a lot of unused space in the 5 × 5 mm2 cell, and one
can fit a Tx/Rx module and even a dual-polarized or dual-
beam designs in each cell. A 100-μm-thick quartz substrate
(20 × 20 mm2 ) with 1200-μm-long dipoles is aligned to the
chip under a microscope and glued using standard epoxy at the
edges. The quartz substrate is smaller than the chip and does
not cover the bondpads. The phased-array chip is then placed
on an FR-4 substrate and VDD , SPI, and external bias pins
(optional) are bonded to the FR-4 substrate. The completed
chip is shown in Fig. 16(a).
For all tests in this section, the phased array is placed on a
probe station and a CPW GSG probe is used for the RF feed,
as shown in Fig. 16(b). A 20-dB standard gain horn is placed
40 cm above the array and is attached to a diode detector or
a calibrated power meter. The horn is placed in the far-field
of the array (2D 2 /λ = 16 cm) so as to accurately capture
the sidelobe levels. The horn is mechanically scanned in
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS
Fig. 17. Measured and simulated broadside patterns in (a) E- and
(b) H -planes at 61 GHz.
two planes for E- and H -plane measurements. The signal-
to-noise ratio was >50 dB even when the array was operating
in a back-off mode (OP1 dB −10 dB).
The wafer-scale array turned on correctly and was controlled
using an external SPI unit. All 64 channels were operational
with 100% yield, and the LAs were also all operational in the
01 mode (there was no need to use the 10 or 11 modes to
recover from any yield failures in the distribution network).
The chip consumed 7–8 W from 2.5 V. It was noticed that
the heat sinking from the vias in the FR-4 substrate under-
neath the silicon chip was not adequate (vias under the chip
were not copper filled), and the chip temperature stabilized
at 95 °C during initial measurements. External forced-air
cooling dropped the temperature to 55 °C. The rise in the
chip temperature (and a bit lower gain) was compensated by
increased the PTAT current and the final power consumption
was 7–8 W at 55 °C–95 °C.
Note that the total power dissipation is only 17 mW/mm2
(8 W/471 mm2 ) and is uniformly distributed across the chip.
This is less than a typical SiGe LNA, which can consume
20 mW in an area of 0.5 mm2 (40 mW/mm2 ). Therefore,
it is easy to remove the heat out of the chip using standard
cooling techniques such as forced air or better thermal vias on
the PCB.
The phase shifters in each channel were first set at 0°,
90°, 180°, and 270° so as to compensate for the BC phase
shifts and to result in a broadside pattern. No other gain
or phase calibration is done on the array (near-field cali-
bration and power measurement per channel). It was first
found that the peak response shifted up to 66 GHz and this
was attributed to a small air gap between the antenna and
the silicon substrate. This was solved by building a longer
differential dipole antenna, 1.32 mm instead of 1.25 mm,
4709
Fig. 18. Measured scanned patterns in (a) E- and (b) H -planes at 61 GHz.
All powers are referenced to the broadside peak power.
rebuilding a new quartz substrate, and reassembling the quartz
substrate on the silicon chip. The new the peak EIRP frequency
shifted back to 61–62 GHz and the array was now ready for
measurements.
The measured E- and H -plane patterns at broadside
with uniform amplitude distribution agree well with simu-
lations (Fig. 17). The array results in a 3-dB beamwidth
of 12° and −13 dB sidelobes at 61 GHz. The cross polar-
ization was less than −30 dB in the E- and H -planes
and is not shown. Measurements at 58–64 GHz resulted in
similar normalized patterns. The patterns are obtained with
all channels set to the same gain state, showing that the
distribution network results in a very uniform power and phase
division to all the elements (±1.2 dB). Such patterns would be
virtually impossible using mm-wave PCB-based phased arrays
without element-to-element calibration, and clearly show the
advantages of wafer-scale phased arrays.
The array is then electronically scanned by loading the
phases in each channel using the standard phased-array
equation
Amn − j k sin (mdx cos φ+nd y sin φ)
Imn = e (1)
Io
where k = (2π/λ), Amn = Io for uniform excitation,
(mdx , nd y ) is the location of the (m, n) element on the
x y plane, and dx = d y = 5 mm (0.5λo at 60 GHz). The
E- and H -planes are defined for φ = 0°/180° and 90°/270°,
respectively. The measured patterns at 61 GHz, normalized
to the broadside value, are shown in Fig. 18. The phased-
array scans to ±55° in the E- and H -planes with no grating
lobes, and with sidelobe levels less than −12 dB for most of
the pattern measurements. The dashed line in Fig. 18 is the
4710 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 12, DECEMBER 2016
Fig. 19. Measured EIRP versus (a) frequency at PSAT power levels and
(b) different LA modes at 62 GHz. L and H denote LAs in mode 01 (low gain)
and 11 (high gain), respectively.
Fig. 20. Measured EIRP versus number of elements and measured relative
EIRP between the 4 different subarrays on the chip.
simulated peak value as the array scans. Again, measurements
at 58–64 GHz resulted in similar patterns.
The measured EIRP versus frequency is shown in
Fig. 19 with a maximum value of 38 dBm at 62 GHz. The
3-dB bandwidth is 61–63 GHz, and is determined by the
on-chip antenna. This is 3 dB lower than the simulated value
of 41 dBm at 25 °C, and is attributed to: 1.5-dB additional
antenna loss due to retuning, 0.5-dB additional loss due to the
temperature rise to 55 °C, and 1 dB due to soft compression
in the third LAs (at PSAT ).
The EIRP is then measured at 62 GHz using different
LA settings (mode 01 or 11) for each stage LA, as shown in
Fig. 6. When all LAs are in mode 01 (standard setting, lowest
Fig. 21. Assembled wafer-scale array on an RO4350B+FR4 substrate.
(a) Top view. (b) Back view. The array is fed using a bond-wire transition
from the CPW line on the board.
Fig. 22. Measurement setup for Tx and Rx benches at (a) 4- and (b) 100-m
link distance.
gain in the distribution network), PSAT is achieved at common-
port input power of −11 dBm, which translates to an element
input power of the same value, since the distribution network
gain is ∼0 dB at 62 GHz. If all of the LAs are in the 11 mode
(highest gain), then an input power of −30 dBm is required for
EIRP saturation. This agrees well with the measured LA gains
in Fig. 8(b). Also, the LA output P1 dB in mode 11 is higher
than in mode 01, and an additional 1 dBm is achieved in the
measured EIRP (no compression in the feed network).
The 16-element quadrants [shown in Fig. 15(b)] were also
measured independently, and result in the same EIRP to within
±0.3 dB (Fig. 20). Finally, the channels were turned in a
binary fashion (N = 1, 2, 4, 8, 16, 32, and 64) and the
measured EIRP indicates a clear N 2 increase. There is a 0.5 dB
drop in the relative EIRP between N = 64 and N = 1 and is
most probably due to the array heating up as the channels are
turned on (in this case, an external fan was used and the peak
chip temperature was 55 °C).
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS
Fig. 23. Measurement setup for the 60-GHz communication link.
Fig. 24. Measurement constellations for different modulation schemes, frequencies, and scanning angles at 4-, 30-, and 100-m distances.
VII. M EASUREMENTS : G BPs C OMMUNICATION S YSTEMS
The wafer-scale phased-array transmitter is placed on a
Rogers RO4350 board (6.6 mil, r = 3.48) with an FR-4
backing, as shown in Fig. 21. The RF input signal at 60 GHz
is fed using a 1.85-mm Southwest Microwave connector. Due
to the relatively high power consumption, an aluminum heat
sink and a miniature air fan are also attached on the PCB.
The measurement setups at 4- and 100-m link distances are
shown in Fig. 22. These experiments show that the wafer-scale
phased array works well over frequency and scan angles.
An upconversion/downconversion system was built using
Keysight Technologies equipment and external mixers and
amplifiers to complete the phased-array 60-GHz communica-
tion system. On the transmit chain, differential I/Q baseband
signals with the IEEE 802.11ad standard are first generated
using an arbitrary waveform generator, and upconverted to a
center frequency of 6 GHz using a vector signal generator. The
modulated 6-GHz IF signal is then upconverted to 58–62 GHz
as shown in Fig. 23, and the image is filtered before the
drive amplifier to the phased array. The phased array is set to
operate at an EIRP of 32–33 dBm at 58–62 GHz for back-off
4711
(linearity for 16 QAM modulation) and low adjacent channel
power ratio. The 58–62 GHz received signal is captured in the
far field using a 20-dB waveguide horn antenna, amplified, and
then translated to a 6-GHz IF using a mixer and an LO source
at 52–56 GHz. The image at 46–50 GHz is filtered in the
WR-15 waveguide, and the IF signal is amplified and sent to
digital scope running the Keysight VSA software.
The 60-GHz communication link was first measured at a
4-m range using 20-dB gain horn antennas for the trans-
mit and receive chains, and an EVM of 9% was achieved
at 1–2 GHz bandwidth, even with a high S/N ratio (>30 dB).
The EVM reduced to 4% for bandwidths of 100–200 MHz.
The relatively high EVM of 9% is due to transitions between
the waveguide and coaxial parts, mixer and amplifier nonflat
gain response versus frequency, and group delay ripple in the
IF bandpass filter, and is the best that one can achieve with a
multiple-component system at 60 GHz.
The transmit horn antenna was then replaced by the
64-element transmit phased array. The measured QPSK and
16-QAM constellations at a 4-m range are shown in Fig. 24 for
different scan angles and frequencies. The system S/N ratio
4712 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 12, DECEMBER 2016
Fig. 25. (a) Full reticle and (b) subreticle stitching techniques (adapted from
[41]).
was >30 dB and the phased-array transmitter results in
the same EVM of 9%–10% as a fixed transmit horn with
20-dB gain, even for MCS-11 (3.85 Gb/s). The experiment
was repeated again at 30 m, and up to 2 Gb/s links could
be achieved using QPSK modulation. At this range, there
was a strong reflection from a side wall, which resulted in
a 2–3 bounce channel and compromised the EVM. The third
experiment was done at 100-m range with a calculated system
S/N = 20 dB, and a QPSK of 1.5 Gb/s links could be
achieved over all scan angles.
VIII. 256-E LEMENT P HASED -A RRAY T RANSMITTER
D ESIGN : S UBRETICLE D ESIGN AND S TITCHING
In this section, the extension of wafer-scale phased arrays to
greater than reticle sizes using a subreticle stitching technique
is presented. The idea is to use discrete building blocks, which
are defined on a single reticle mask, and by stitching the
building blocks together in different ways, one can synthesize
any phased-array shape on the wafer using the same reticle
mask.
Silicon integrated circuits are limited by the reticle size
(22 × 22 mm2 ), since this is the largest area that can be
exposed in standard integrated circuit photolithography. With
recent advances in photolithographic techniques, it is now
possible to create large-size circuits onto a single silicon
die using a special technique called stitching. There are two
different stitching methods.
The first one relies on “stitching” entire reticles together
by stepping the reticle across a silicon wafer, as shown in
Fig. 25(a). The reticle-stitching technique connects several
metal layers in the back end of line, thus allowing different
reticles to act as one large electrical circuit. This corresponds
to Metal-1 to Metal-6 layers in the TowerJazz SBC18H3S
process, which is used in this paper. This stitching technique
is commonly used in CMOS imaging arrays to achieve large-
scale focal-plane arrays, and also to stitch readout circuitry to
achieve sizes, which are larger than a single reticle [42].
The second technique relies on using basic building blocks
defined the reticle, called subfields, and stitching them together
Fig. 26. Phased-array subblocks in a 20 × 20 mm2 reticle.
in different configurations to result in any phased-array shape
(rectangular, square, and hexagonal) by using the same reticle
mask. In this technique, only one subfield is exposed and
the unused portion of the reticle is darkened, as shown in
Fig. 25(b). The subfield stitching process is repeated across
the silicon wafer, and in each time, a different subfield is
exposed. The considerable regularity of array-based circuits,
such as CMOS image sensors and mm-wave phased arrays,
allow this very powerful technique to be used [43].
In this paper, subreticle stitching technique is proposed for
256-element phased-array transmitter in which some blocks
are used repeatedly (such as the phased-array channels) and
some blocks are used only once or twice (such as edge
circuits for control and input RF ports with baluns). The
subreticle stitching is done at metals M1–M6 with an overlap
of <0.5 μm for M1 and <1 μm for M6 using special
stitching masks, but not at the polysilicon or diffusion layers.
Therefore, the different blocks are stitched at all metal levels,
but the transistors themselves cannot be stitched (this is not
needed anyways). The 0.5–1 μm overlaps between stitching
fields have insignificant effect on the phased-array grid at
60 GHz (2500 μm).
A study of the 64-element full-reticle phased array (see
Sections II–V) results in the building blocks shown in Fig. 26,
which are used to synthesize any phased array on a single
silicon wafer. The building blocks are as follows.
1) Block A: 4×4 subarray (main block containing channels,
antenna feed, SPI for the subarray, Wilkinson, and
branchhline dividers).
2) Blocks B1/B2, C1/C2: Pads and digital control on the
vertical and horizontal edges.
3) Blocks D1/D2/D3/D4: Additional digital control and
filling.
4) Blocks E1, E2: Vertical transmission lines with and
without a BC.
5) Blocks F1, F2: Redundant LAs with connecting trans-
mission lines (left to right and right to left).
6) Blocks G, H: Center connector with and without a BC.
Fig. 27 shows how the building blocks can be stitched
together to build, for example, a 256-element (16 × 16) as
shown in Fig. 27(a) and a 128-element (16 × 8) array as shown
in Fig. 27(b). Looking at the 256-element phased array in
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS 4713

Fig. 27. Formation of (a) 16 × 16-element phased array with block details and (b) 16 × 8-element phased arrays with block details, both using the subreticle
stitching technique.

Fig. 28. Distribution loss and P1 dB at different locations in the distribution network at 60 GHz.

detail, block A is exposed first using a step-and-repeat function
on the wafer to fill all the instances in the array, while all
other blocks are shadow-masked (dark masked) so as not to
appear on the wafer. Then, blocks E1, E2, F1, F2, G, and
H are exposed on the wafer, each in succession using step-
and-repeat function, to define the transmission lines, LAs, and
connecting squares with and without the BCs. Again, when
exposing a block, all other blocks are shadow-masked. Finally,
the edge blocks such as B1/B2, C1/C2, and D are exposed,
but only half of B1/B2andC1/C2 are needed on each edge of
the wafer-scale phased array. The other part is just diced or
is used as an edge for the neighboring die once the phased
array is completed. Blocks D are used to fill in the outermost
corners. The stitching is done layer by layer (M1–M6), and
the additional work is the use of the shadow masks for the
different exposures. Note that they are only ten different blocks
to form any size phased array and blocks B1/B2, C1/C2, and
D1/D2/D3/D4 are combined together as a single block.
Note that similar to the 64-element full-reticle design, the
256-element implementation has two redundant center inputs
(RFin and Red. RFin at the center) and another four quadrant
RF inputs (Red. RFin for each quadrants). The quadrant
RF inputs can be fed using an external 1:4 distribution network
in case one of the main LAs fails, thereby ensuring a higher
operational yield for the array.
To the best of our knowledge, the stitching technique
has never been applied to RF chips and especially to
mm-wave wafer-scale phased arrays. It is a versatile method
4714 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 12, DECEMBER 2016

Fig. 29. Simulated distribution network gain from the common RF port to
the input of each channel (256-channels).

which allows for tremendous flexibility in building wafer-

scale phased arrays. This technique can result in 1024-element
arrays and even in entire wafer-scale arrays, provided enough
circuit redundancy is included in the design for improved
yield.
IX. I MPLEMENTATION
There are several parts in the 256-element phased-array
transmitter, which are common with 64-element phased array
and will not covered. They are as follows:
1) antenna and quartz superstrate;
2) phased-array channel, 4 × 4 subarray, and its
SPI controller;
3) redundant LA, distribution network, and the BC;
4) redundant vertical and horizontal master SPI con-
troller, parallel inputs, external bias control, and dual
MIM capacitors;
5) redundant RF inputs at the center of the array and for
every 8 × 8 subarrays. Fig. 30. (a) Photograph of the fabricated 256-element phased array on a
200-mm wafer with a quarter and (b) expanded view showing the different
In order to build the 256-element array, some additional subblocks used.
circuit blocks are needed and they are as follows.
1) Two LAs are added in the distribution network to Fig. 29 shows the frequency response of the 1–256 distrib-
overcome the added transmission line loss. ution network based on the measured LA S-parameters in the
2) Vertical and horizontal SPI buffers are added as part 01 mode. As in Section II, the response shifted to 55 GHz.
of the 4 × 4 subarray. This regenerates the SPI control Also note that there is a ±2 dB variation in the network gain
signals, since it must travel over a 400 + 400 mm (X + due to the use of 5 BCs each with ±0.4 dB gain imbalance.
Y distances) from the master controller to a 16-element This ±2 dB variation can easily be compensated by the VGA
(4×4) subarray. The buffers lower the capacitive loading in the phased-array channel.
on the master controller, and drive the SPI signals for an
average line length of only 10 mm. This ensures that the X. 256-E LEMENT P HASED -A RRAY
SPI can operate at 50 MHz even with a large wafer-scale S YSTEM -L EVEL S IMULATIONS
phased array. The 256-element phased array is simulated as in Part I
The details of the 1–256 distribution network at 60 GHz are including the antenna response. The array electronic gain,
shown in Fig. 28, and include five LAs with a gain of 15 dB defined as the available power per channel at the antenna
each, eight BCs and three Wilkinson dividers, and transmission port divided by the input power, is 17 ± 2 dB at 60 GHz
line lengths. The total loss is ∼76 dB and can be divided as; (−0.7 ± 2 dB distribution gain and 18-dB phased-array
24 dB division loss, 9.5 dB BC and Wilkinson divider ohmic channel gain). The 256-element array directivity is D = 29 dB
loss, 1.5 dB the input balun loss, and 41 dB the transmission at 0.5λ spacing with a half-power beamwidth of 6°. The array
line loss. This is compensated by ∼75 dB of aggregated LA gain is 26 dB at 60 GHz due to the −3 dB on-chip differential
gain, resulting in a total distribution gain of ∼0 dB at 60 GHz. antenna efficiency. The available per antenna element is 3 dBm
There are a total of 86 LAs consuming 3450 mW of dc power. at PSAT , and together with an every gain of 26 dB results
Note that in Fig. 27, the LAs connected to the redundant RF I N in an EIRP of 53 dBm (PSAT ) at broadside. All results are
are not turned ON. at 25 °C.
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS
Fig. 31. (a) Zoomed photograph of the phased array showing Wilkinson
dividers, phased-array channel, and on-chip antenna feed and (b) phased-array
center showing BC, LA, and stitching lines.
The entire array consumes 32 W from a 2.3 V supply (14 A),
and the power is divided as 4 W for the LAs, and 28 W
for the channels. The digital control consumes <30 mW of
power in the static mode. There are several VDD inputs on the
top and bottom of the chip, and M5 and M3 (1.2 μm and
0.62 μm thick) is used for wide VDD strips over the entire
chip, except under the antennas, channels, and transmission
lines. In addition, M3 and M2 (both 0.62 μm thick) are also
used as VDD strips under the antennas to achieve low a I × R
drop. The voltage drop to the center element is at <0.2 V
knowing the resistivity of layer M5.
XI. M EASUREMENTS : PATTERNS AND EIRP
A 200-mm SiGe BiCMOS wafer resulted in nine wafer-
scale phased-arrays as shown in Fig. 30(a) and the wafer-
scale 256-element full-reticle phased array (41.4 × 42 mm2 )
is shown in Fig. 30(b). Expanded views of the wafer-scale
phased array are shown in Fig. 31(a) and (b). Note the
two different Wilkinson dividers for the last two stages of
the RF distribution network, the phased-array channel, the
redundant LA, and the antenna feed [Fig. 31(a)]. Fig. 31(b)
shows the center of the array and one can see the stitching
lines, the 4 × 4 SPI module, and the BC in the middle of the
chip.
Four different 100-μm-thick quartz substrates
(20 × 20 mm2 ), each containing 64-element antennas which
4715
Fig. 32. Picture of the wafer-scale 256-element phased array
(41.4 × 42 mm2 ) with four quartz superstrates (quadrants 1, 2, 3, and 4
are shown).
are 1.32 mm long (see Section IV for antenna length) are
then aligned to the chip under a microscope and glued using
standard epoxy at the edges. The phased-array chip is placed
on an FR-4 substrate and VDD , SPI, and external bias pins
are bonded to the FR-4 substrate. The completed chip is
also shown in Fig. 32. To the best of our knowledge, this
is the largest RF chip ever fabricated using any technology
(1740 mm2 ), including microprocessor or memory chips. The
only chips which are larger than proposed design are the
advanced focal-plane imaging arrays [42], [43].
Again, heat sinking due to the vias underneath the silicon
chip was not adequate (vias were not copper filled), and the
chip temperature stabilized at 90 °C during measurements.
External forced-air cooling dropped the temperature to 60 °C.
The rise in the chip temperature (and lower gain) was com-
pensated by increasing the PTAT current and the final power
consumption was 30–32 W. Again, the power consumption
is only 17 mW/mm2 and the heat is easily removed using
forced-air cooling or thermal vias.
The same measurement setup is used, as shown in
Fig. 16(b). The receiving horn antenna is R = 40 cm away,
while the far-field, defined as 2D 2 /λ, is Rff = 64 cm. We have
done calculations on the 256-element array gain and found
that at Rff = 40 cm, the measured gain and EIRP drops by
0.96 (−0.2 dB) of its far-field value. A correction factor of
0.2 dB is therefore used in the measured EIRP value. The
phase shifters in each channel are first set at 0°, 90°, 180°,
and 270° so as to compensate the BC phase shifts and to result
in a broadside pattern. No gain or phase calibration is done on
the array (near-field calibration and power measurement per
channel).
First, each quadrant of the phased array was turned on
separately and measured (Fig. 32). The normalized patterns
were very similar to each other [Fig. 33(a)], but each quadrant
results in a different EIRP versus frequency [Fig. 33(b)]. This
is due to the manual placement of the quartz superstrates on
the array, which result in different (but small) misalignments
and air gaps.
Second, the entire 256-element wafer-scale phased array
was turned on with uniform excitation in the channels
4716 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 64, NO. 12, DECEMBER 2016

Fig. 34. Measured and simulated broadside patterns in (a) E- and

(b) H -planes at 61 GHz.
Fig. 33. Measured (a) patterns and (b) EIRP for the four different 64-element
quadrants in the 256-element wafer-scale phased array. Also shown is the
64-element full-reticle phased-array transmitter chip with a retuned antenna.

(VGAs at maximum gain setting). The entire 256-element

phased array turned on correctly and was controlled by the
SPI at MHz rates. Every channels of the 256-element array
was operational. Also, the LAs were all operational and were
all used in the 01 mode (low gain mode). The measured
E-plane [Fig. 34(b)] and H -plane [Fig. 34(a)] patterns at
broadside with uniform gain on every channel agree well with
simulations, and shows a 3-dB beamwidth of 6° and −11 dB
sidelobes at 61 GHz. The rise in the sidelobe level is due
to the four quadrants not being identical and the ±2 dB
gain variation due to the BCs in the distribution network.
The cross polarization was less than −30 dB and is not
shown. Measurements at 58, 60, 62, and 64 GHz resulted in Fig. 35. Measured and simulated broadside H -plane patterns at (a) 58,
very similar normalized patterns, as shown in Fig. 35(a)–(d), (b) 60, (c) 62, and (d) 64 GHz.
respectively.
The array is then scanned by loading the phases in each value at 80 °C–90 °C (45 dBm) is due to 1.5-dB additional
channel using the SPI controller. The measured patterns antenna loss due to retuning, 1.5–2 dB soft compression in
at 61 GHz, normalized to the broadside value, are shown the last LA in the distribution network, 2–3 dB additional loss
in Fig. 36(a) and (b) for E- and H -planes, respectively. due to the different quartz substrates on the 8 × 8 quadrants,
The phased array scans to ±55° in the E- and H -planes and 2-dB drop due to operating at 80 °C–90 °C (a fan was
with no grating lobes, and with sidelobe levels mostly less not used for these measurements). Still, an EIRP of 45 dBm
than −11 dB. The dashed line is the simulated peak value as is a record at 60 GHz from an mm-wave phased array, and
the array scans. Again, measurements at 58–64 GHz resulted especially with a 6-GHz bandwidth.
in very similar patterns. Finally, a separate 64-element (8 × 8) wafer-scale phased
A peak EIRP of 45 dBm is measured at 61.5–62 GHz, with array with the dimensions of 21.4 × 22 mm2 was also
3-dB bandwidth of 6 GHz (Fig. 37). It is clear that the different fabricated using the subreticle stitching technique. The results
response from each quadrant (8 × 8) has lowered the peak were very similar to 64-element phased array discussed in
EIRP but increased the bandwidth. The difference between the Sections II–VI and are not repeated here. However, this shows
simulated EIRP value at 25 °C (53 dBm) and the measured that for phased-arrays which are smaller than a reticle, one
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS
Fig. 36. Measured and simulated peak scanned patterns in (a) E- and
(b) H -planes at 61 GHz.
Fig. 37. Measured EIRP of the 256-element phased-array transmitter.
can build them using a dedicated reticle or using a subreticle
stitching technique and with similar results.
XII. C ONCLUSION
This paper presented a 60-GHz wafer-scale phased array
transmitter with record performance. The use of the same
silicon wafer for the RF distribution network, power and SPI
distribution, and phased-array channel, and for high-efficiency
antennas, results in a phased array, which scans to ±55° with
near-ideal patterns. The 1–64 distribution network divides the
power equally to all phased-array channels, which being on
the same wafer are very similar to each other. There are no
transitions in and out of the chip, and the antenna is connected
directly to the phased-array channel with no transmission-
line loss, and this results 3–4 dB lower loss performance
than the traditional phased arrays built on multilayer PCBs.
4717
Care is taken to provide several levels of redundancy at the
power supply, SPI, and circuit and system levels, so as to
improve the yield of the wafer-scale arrays. Also, a 60-GHz
256-element wafer-scale phased array transmitter, which scans
to ±55° with near-ideal patterns and with an EIRP of 45 dBm
is presented. A subreticle stitching technique is used to build
the 256-element phased array and results in the largest single-
chip phased array [with a size of 41.4 × 42 mm2 (1740 mm2 )]
ever developed. The proposed method allows the construction
of large-scale (over 1000 elements) phased-array systems,
either on a single wafer or by assembling a few of these
chips together. Future work includes the design of a more
efficient and wideband mm-wave on-chip antenna, integration
of transmit and receive channels, and dual-polarized channels
and an upconversion and downconversion so as to result in a
complete system-on-chip at the wafer-scale level.
ACKNOWLEDGMENT
The authors would like to thank M. Scott, E. Preisler,
S. Stetson, and D. Howard at TowerJazz Semiconductor
and M. Pierpoint, Keysight Technologies, for their continued
support.
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Samet Zihir (S’06–M’15) received the B.Sc.
and M.S. degrees in electronics engineering from
Sabancı University, Istanbul, Turkey, in 2009
and 2011, respectively, and the Ph.D. degree in elec-
trical engineering from the University of California
at San Diego (UCSD), La Jolla, CA, USA, in 2015.
His research interests include RF and millimeter-
wave integrated circuits and antennas in silicon
technologies for phased-array systems and high data-
rate wireless communications.
Dr. Zihir was a recipient of the Analog Devices
Outstanding Student Designer Award in 2015, the Best Student Paper at
SIRF in 2010, and the IEEE Microwave Theory and Techniques Society
Undergraduate/Pre-Graduate Scholarship Award in 2009.
Ozan Dogan Gurbuz (S’12–M’15) received the
B.S. and M.S. degrees in electrical and electronics
engineering from Middle East Technical University,
Ankara, Turkey, in 2008 and 2010, respectively,
and the Ph.D. degree in electrical engineering from
the University of California at San Diego (UCSD),
La Jolla, CA, USA, in 2015.
From 2008 to 2010, he was with the
METU-MEMS Center, Ankara, Turkey, as a
Graduate Student Researcher, where he was
involved with RF MEMS device fabrication and
reliability measurements. From 2010 to 2015, he was a Graduate Student
Researcher with the Telecommunications and Integrated Antennas, Circuits
and Systems (TICS) Lab, UCSD. He is currently a Microwave Design
Engineer with Analog Devices, Beaverton, OR, USA. His research interests
include lens antennas, high-efficiency RF integrated circuit (RFIC) antennas,
tunable microwave circuits for communication systems, mm-wave package
and antenna design.
ZIHIR et al.: 60-GHz 64- AND 256-ELEMENTS WAFER-SCALE PHASED-ARRAY TRANSMITTERS
Arjun Kar-Roy (S’84–M’94–SM’07) was born in
Ranchi, India, in 1967. He received the B.Tech.
degree (Hons.) in electrical and electrical communi-
cations engineering from IIT Kharagpur, Kharagpur,
India, in 1988, and the M.S. and Ph.D. degrees in
electrical and computer engineering from the Uni-
versity of California at Irvine, Irvine, CA, USA, in
1990 and 1994, respectively, in the area of integrated
photonics.
He joined Rockwell Semiconductor Systems,
Newport Beach, CA, USA, in 1996, and has con-
tinued working there through its transitions to Conexant Systems in 1998,
Jazz Semiconductor, Newport Beach, CA, in 2002, and TowerJazz, Migdal
HaEmek, Israel, in 2009. From 1994 to 1996, he was a member of Technical
Staff with Plasma and Materials Technologies, Inc., Los Angeles, CA, USA,
working on high-density plasma etch and deposition semiconductor process
equipment. He has made contributions in process technology development
in mixed-signal CMOS, SiGe BiCMOS, CMOS image sensors, large die
manufacturing methods, and 3-D integrated circuits. He is currently a Senior
Principle Engineer and the Technical Director with the USA Aerospace and
Defense Group, TowerJazz. He is also managing programs from the Air Force
Research Laboratories and Army Night Vision Laboratory. He holds over 50
patents. He has authored technical publications.
Dr. Kar-Roy received the Chancellor’s Fellowship from the University of
California at Irvine.
Sanjay Raman (S’84–M’98–SM’06–F’12) was
born in Nottingham, U.K., on April 25, 1966. He
received the B.S. degree in electrical engineering
(with highest honor) from the Georgia Institute of
Technology, Atlanta, GA, USA, in 1987, and the
M.S. and Ph.D. degrees in electrical engineering
from The University of Michigan at Ann Arbor, Ann
Arbor, MI, USA, in 1993 and 1998, respectively.
From 1987 to 1992, he was a Nuclear Trained
Submarine Officer with the U.S. Navy. In Janu-
ary 1998, he joined the faculty of the Bradley
Department of Electrical and Computer Engineering, Virginia Polytechnic
Institute and State University, Blacksburg, VA, USA, where he is currently
a Professor. He is also currently serving as Associate Vice President,
Virginia Tech National Capital Region, where he is responsible for planning
and executing region-wide initiatives to enhance the university’s research,
education, and outreach missions. He is also a founding member of the VT
Multifunctional Integrated Circuits and Systems (MICS) research group. His
research interests include RF/microwave/millimeter-wave integrated circuits
and antennas, high-speed/mixed-signal ICs, interconnects and packaging,
RF microelectromechanical/nanoelectromechanical (MEMS/NEMS) devices,
and integrated wireless communications and sensor microsystems. From
2007 to 2013, he served as a Program Manager with the Microsystems
Technology Office, Defense Advanced Research Projects Agency (DARPA),
Arlington, VA, USA, where he was responsible for major R&D programs
in the areas of adaptive RF/mixed-signal integrated circuits, RF MEMS, and
3-D/heterogeneous integration technologies.
Dr. Raman has served as an Associate Editor for the IEEE T RANSAC -
TIONS ON M ICROWAVE T HEORY AND T ECHNIQUES . He has served on
the Technical Program Committee of the IEEE Radio Frequency Integrated
Circuits Symposium. He served as Technical Program Co-Chair for the
2014 International Microwave Symposium. He is an Elected Member of the
IEEE Microwave Theory and Techniques Society (MTT-S) Administrative
Committee. He was the recipient of the 2007 Virginia Tech College of
Engineering Faculty Fellow, the 2000 Presidential Early Career Award for
Scientists and Engineers (PECASE) (1999 NSF CAREER Award), Virginia
Tech College of Engineering Outstanding New Assistant Professor Award
(2000), and a 1996-1997 Armed Forces Communications and Electronics
Association (AFCEA) Postgraduate Fellowship. In 2013, he was the recipient
of the Secretary of Defense Medal for Exceptional Public Service for his
service at DARPA.
4719
Gabriel M. Rebeiz (S’86–M’88–SM’93–F’97)
received the Ph.D. degree from the California Insti-
tute of Technology, Pasadena, CA, USA.
From 1988 to 2004, he was with the University of
Michigan, Ann Arbor, MI, USA. He is a member of
the National Academy, and a Distinguished Profes-
sor and the Wireless Communications Industry Chair
Professor of electrical and computer engineering
with the University of California at San Diego,
San Diego, CA, USA. His group has optimized the
dielectric-lens antenna, which is the most widely
used antenna at millimeter-wave and terahertz frequencies. His group also
developed 6-18-, 30-35-, 40-50-, 77-86-, and 90-110-GHz 8- and 16-element
phased arrays on a single silicon chip, the first silicon phased-array chip
with built-in-self-test capabilities, the first waferscale phased arrays with on-
chip antennas, and the first SiGe millimeter-wave silicon passive imager chip
at 85-105 GHz. His group also demonstrated high-performance RF MEMS
tunable filters at 0.7-6 GHz, RF MEMS phase shifters at 1-100 GHz, and high-
power high-reliability RF MEMS metalcontact switches. As a consultant, he
helped develop 24- and 77-GHz singlechip SiGe automotive radars, phased
arrays operating at X- to W-band for defense and commercial applications
(SATCOM, automotive, and point-to-point), digital beamforming systems, and
several industrial RF MEMS switches. He has graduated 64 Ph.D. students
and 21 Post-Doctoral Fellows. He has authored or co-authored over 650
IEEE publications, and authored the book RF MEMS: Theory, Design, and
Technology (Wiley, 2003). He currently leads a group of 18 Ph.D. students and
postdoctoral fellows in the area of millimeterwave RFICs, tunable microwaves
circuits, RF MEMS, planar millimeter-wave antennas, and terahertz systems.
Dr. Rebeiz was a recipient of the IEEE MTT-S 2000 and 2014 Microwave
Prize, the IEEE MTT-S 2010 Distinguished Educator Award, the IEEE
AP-S 2011 John D. Kraus Antenna Award, the 2012 Intel Semiconductor
Technology Council Outstanding Researcher in Microsystems, an Research
and Development 100 2014 Award for this work on phased-array automotive
radars, the 2014 IEEE Daniel E. Noble Field Medal for his work on RF
MEMS, and the IEEE AP-S 2015 Harold A. Wheeler Applications Prize Paper
Award. He was also a recipient of the 1997-1998 Eta Kappa Nu Professor
of the Year Award, the 1998 College of Engineering Teaching Award, and
the 1998 Amoco Teaching Award given to the best undergraduate teacher
at the University of Michigan, and the 2008 Teacher of the Year Award of
the Jacobs School of Engineering, University of California at San Diego.
His students have won a total of 22 Best Paper Awards from the IEEE
MTT-S, Radio Frequency Integrated Circuits, and AP-S conferences. He has
been an Associate Editor of the IEEE T RANSACTIONS ON M ICROWAVE
T HEORY AND T ECHNIQUES , and a Distinguished Lecturer of the IEEE
M ICROWAVE T HEORY AND T ECHNIQUE S OCIETY, the IEEE A NTENNAS
AND P ROPAGATION S OCIETY , and the IEEE S OLID -S TATE C IRCUITS S OCI -
ETY . He was a National Science Foundation Presidential Young Investigator
and the 2003 IEEE MTT-S Distinguished Young Engineer. He was a recipient
of URSI Koga Gold Medal.