TOPIC: Behavioral Modeling, Timing

Controls
COURSE: anddesign
VLSI Verilogusing
Control blocks
Verilog
Latch Vs Flip Flop
CHAPTER: - Five

PPT SL.NO.: - 01

VERSION: - 01 LAST UPDATED ON: 19/06/2020

NIELIT Presentation By: Pragya Sharma

Latch Vs Flip Flop
Latch Flip-Flop
A latch checks the input continuously and A flip-flop is a combination of a clock and
changes the output when there is a change a latch, and its output is changed
in the input. (asynchronous device) according to the clock when there is a
change in the input. (synchronous device)
Building block of sequential circuits Building block of sequential circuits
Latches are built from gates Flip-Flops are built from latches
Latch does not have a clock signal Flip-Flop has a clock signal

Latch is level triggered i.e. the output of Flip Flop are edge-triggered i.e. the output
the present sate and input of the next state and the next sate changes when there is a
depends on the level i.e. binary input 1 or change in clock pulse whether it may be
0. +ive or –ive clock pulse.
Flip-Flops
Flip Flops to be considered are:
SR Flip Flop
JK Flip Flop
D Flip Flop
T Flip Flop
SR Flip Flop:
◻ SR Flip Flop: Basic Flip Flop. Similar to S-R
latch except clk signal and two AND gates. The
circuit responds to the positive edge of clock
pulse to the inputs of S & R.
Flip-Flops
Truth Table of SR Flip Flop
Clock S R Q n+1 State

0 x x Qn
1 0 0 Qn Hold
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 x Invalid

Characteristic Table of SR Flip Flop

S R Qn Qn+1 State
0 0 0 0 Qn (Hold)
0 0 1 1
0 1 0 0 Reset
0 1 1 0
1 0 0 Logic Diagram
1 Set of SR Flip Flop
1 0 1 1
1 1 0 x Forbidden/Invalid
1 1 1 x
SR Flip-Flop using gate modeling
module srff_gate(q, qbar, s, r, clk);
input s,r,clk;
output q, qbar;
wire nand1_out; // output of nand1
wire nand2_out; // output of nand2
nand (nand1_out,clk,s);
nand (nand2_out,clk,r);
nand (q,nand1_out,qbar);
nand (qbar,nand2_out,q);
endmodule
SR Flip-Flop using dataflow modeling

module srff_dataflow(q,qbar,s,r,clk);
input s,r,clk;
output q, qbar;
assign q = clk? (s | ((~r) & q)) : q;
assign qbar = ~q;
endmodule
SR Flip Flop (data flow)
Flip flops are edge-triggered circuits. When we
use a conditional operator, the statement is not
executed at the clock edges(HIGH to LOW or
LOW to HIGH) but the clock level(HIGH and
LOW). Hence, the dataflow model of SR flip flop
will work only as a latch. And not as an authentic
flip-flop that triggers on clock edges.
SR Flip-Flop using behavioral modeling
module SR_flipflop(q,q1,r,s,clk);
output q,q1;
input r,s,clk;
reg q,q1;
initial

//Initial Block is used to set the values of q and q1 initially because then these values will be used
as feedback in the always block. Initial Block is executed only once in the code.
begin
q=1'b0; q1=1'b1; // q is set to 0 and q1 is set to 1.
end
always @(posedge clk)
begin
case({s,r})
{1'b0,1'b0}: begin q=q; q1=~q; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=1'bx; q1=1'bx; end
endcase
end
endmodule
SR Flip-Flop Test Bench
module dff_test;
reg S,R, CLK;
wire Q, QBAR;

//srff_behave dut(.q(Q), .qbar(QBAR), .s(S), .r(R), .clk(CLK)); // instantiation by port name.

SR_flipflop sr1(.q(Q),.q1(QBAR),.r(R),.s(S),.clk(CLK));

initial begin
$monitor("simtime = %g, CLK = %b, S = %b, R = %b, Q = %b, QBAR = %b", $time, CLK, S, R, Q,
QBAR);
clk=0;
forever #10 clk = ~clk;
end
initial begin
S= 1; R= 0;
#100; S= 0; R= 1;
#100; S= 0; R= 0;
#100; S= 1; R=1;
end
endmodule
 Thank you!

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