2018 International Conference on Sensor Networks and Signal Processing (SNSP)

Design and Implementation of VHDL for High Speed Interleaver in Tactical Data
Link

Zhao Heng, Li Guomin, Xia Meng

College of Communition and Information Engineering
Xi’an University of Science and Technology
Xi’an, Shaanxi
e-mail:757911870@qq.com

Abstract—This paper introduces the channel coding of data
link system, and analyzes the principle and algorithm of
interleaved codec in data link. Based on this, a convolutional
interleaving codec for RS (204, 188) code is designed and
implemented by VHDL. The data delay is realized, and the
function of convolutional interleaving is completed. The design
has the advantages of simple implementation and low resource
consumption.
Keywords- data link system, convolutional interleaving,
VHDL
I. INTRODUCTION
At present, the tactical data link mainly provides anti-
interference, secure data communication, and real-time
transmission of detection and sensor information for the
combat platform. Therefore, it can improve the coordination
capability and operational effectiveness of the combat
platform, so the information transmission requirements are
safe and effective. Since the main error in the
communication process is caused by channel noise and
enemy sudden intentional interference, the error may be a
long string or a long sudden error. Therefore, an encoding
technique that can correct the burst error must be adopted[3].
The FEC scheme of error correction coding combined with
the interleaving technique is usually used to deal with burst
errors, that is, the interleaving technique is used to
randomize burst errors, and the error correcting code
technique is used to correct random errors.
As a standard language used in hardware design, VHDL
reduces the difficulty of designing FPGAs and shortens the
design and debugging cycle of the entire system. Interleaving
with FPGA can greatly reduce the size of the circuit and
improve the stability of the circuit, thus achieving the real-
time communication requirements of the data link.
Literature [3] discussed in detail the specific algorithm of
RS codec and its FPGA implementation in data link; In [4],
an efficient convolutional de-interleaving implementation
structure is designed for the integration of the demodulation
chip in the SOC system, which greatly improves the access
efficiency of the convolution and de-interlacing to the bus; In
[5], an RS decoding algorithm with low complexity and
simple hardware implementation is proposed. The
performance curve of the algorithm is simulated by Matlab,
but the feasibility of the algorithm is not verified by FPGA;
In [6] expounds a kind of interlaced coding technology of
Hamming code, and implements and simulates with FPGA
as the platform, but adopts simple block interleaving
technology; Literature [7] and literature [6], based on the
study of interlacing and Hamming code, designed an
interwoven Hamming code.
II. CHANNEL CODING OF DATA LINK SYSTEM
The choice of general error control coding is based on
actual channel characteristics and system error performance
requirements. The RS code is a multi-coded code that can
correct multiple consecutive binary error codes, so it is
especially suitable for correcting bursty error codes in fading
channels. Its coding efficiency is high, and it is suitable for
information transmission occasions with high real-time
requirements. It has been widely used in data links, such as
Link-16, Link-22, deep sea communication, air-to-air missile
telemetry[5]. In this paper, based on the DOCSIS standard,
The error correction coding of the scrambled RS (204, 188)
error protection packet uses a convolutional interleaving
scheme with an interleaving depth of I=12 and M=17.
III. THE BASIC PRINCIPLE OF CONVOLUTIONAL
[9]
INTERLEAVING
Interleaving is a technique used in data processing in a
communication system. Interleaving is essentially a
technique for achieving maximum change in information
structure without changing information content. After the
input sequence of information is interleaved, the order of the
resulting output sequences will change. The inverse process
is de-interlacing, that is, the position of the received
information sequence is restored, and the position of the data
is restored to the order of transmission. There are two types
of synchronous interleaving commonly used in digital
communications:
1) Block interleaving. It is a two-dimensional memory
array N × B, the data is first written in rows, and then read
out in columns to complete the interleaving process;
accordingly, the deinterleaving process is to write data in
columns and then in rows. The block interleaving structure is
simple, but the data delay time is long and the required
memory is relatively large.
2) Convolution interleaving. Convolutional interleaving
is based on the Forney method. The structure of
convolutional interleaving and deinterleaving is shown in
Fig.1[4].

978-1-5386-7413-0/18/$31.00 ©2018 IEEE 392

DOI 10.1109/SNSP.2018.00082

Figure 1. Schematic diagram of convolutional interleaver
and deinterleaver
The input symbol data at the input end of the interleaver
enters the I branch delays in sequence, each delaying a
different symbol period. The first channel has no delay, the
second channel delays M symbol periods, the third channel
delays 2M symbol periods, ⋯⋯, the Ith channel delays (I-1)
M symbol periods. The output of the interleaver
synchronously outputs the delayed data of the corresponding
branch according to the working beat of the input end.
Thedelay tempo of each branch symbol data of the
convolutional interleaver is di=(i-1)MI, i=1, 2, ⋯, I. The
number of delays of the deinterleaver is opposite to that of
the interleaver, that is, the first branch delays (I-1)M symbol
periods, ⋯⋯, the Ith branch has no delay.
IV. VHDL DESIGN OF CONVOLUTIONAL INTERLEAVER
There are two main types of convolutional interleaving
methods: one is to use the shift register method, and the
delay of each branch is directly realized by FIFO. This
method is simple to implement. However, when the values of
I and M are large, a large number of registers need to be
consumed (shown in Figure 2).; the other is the use of RAM
to implement the function of the shift register, by controlling
the read / write address to achieve each branch delay. Fig. 3
shows the function of implementing FIFO using RAM.
Input data Input data
1 2 3 4 5 6
Figure 2. FIFO shift register operation process
Write
address 1
Read
address
2
6
Figure 3. RAM mimics the operation of the FIFO
function
In this paper, the interleaver and deinterleaver are
implemented by RAM shift method. The block diagram of
its circuit implementation is shown in Fig. 4. Since the
interleaving and deinterleaving require regular delay
processing on the data, the input data is first stored in a dual
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port RAM and then read out after a certain delay. This delay
is controlled by the read and write addresses of the dual port
RAM. Therefore, the key to its implementation lies in the
generation and distribution of the dual-port RAM read/write
address, which is not only conducive to finding the change
rule of the address, but also easy to implement the circuit.
One way to generate RAM read and write addresses is to
map the read and write addresses into the ROM. Another
way is to get the read and write addresses through circuit
calculation. The former method is simple and convenient to
implement, but adding ROM will occupy storage resources,
so the latter is generally adopted, and its implementation is
not complicated.
The following is a brief description of the generation of dual-
port RAM address allocation and read-write addresses in this
design. Take an interleaver with I=12 and M=17 as an
example. Since the interleave depth is 12, there are 12
channels. Table 1 lists the address assignments for each
channel. The first row corresponds to the 0th channel of the
interleaver in Fig. 2, the second row corresponds to the first
channel, and the third row corresponds to the second channel,
Figure 4. Logical implementation block diagram of
convolutional interleaver and deinterleaver
⋯⋯, the 12th row corresponds to the 11th channel. The i-th
channel has a total of N=i×M+1 addresses, and the assigned
address is fixed. The RAM read/write address changes
according to the delay rule of each channel in the interleaver,
and the address allocation of the interleaver is as shown in
Table 1[7].
Table 1. Interleaver Address Assignment
When interleaving, the first time read address can be
arbitrary, the write address is 0; the second time read address
is 1, the write address is 18; the third time read address is 54,
the write address is 105, and the fourth time read address is 3,
the write address is 27, the 12th time read address is 946, the
write address is 1133, the 13th time read address can be
arbitrary, the write address is 0, the 14th time read address is
2, the write address is 1, the 15th time read address is 20, the
write address is 19, and the rest is analogized. It can be seen Table 2. Deinterleaver Address Assignment
that the read/write addresses of the 0~11 channels change
according to their respective delay rules, and the i-th channel
read address and write address are cyclically separated by
i×17 units in the right direction of the channel. When
designing the circuit, in addition to the 0th channel, each
channel can use a counter, each counter is independently
counted. Assume that the count value of the i-th channel
counter is ai, the first address of the channel is bi, and the tail
address is ci, thus obtaining the change rule of the read-write
address of the RAM:
The i-th channel read address: ai+bi; (1)
The i-th channel write address: ai+bi-1, ai Į0;
ci, ai=0; (2) The above describes the implementation of the read and
The address allocation of each channel during write generator, it can be said that the module is successfully
deinterleaving is shown in Table 2. Since deinterleaving and implemented, the interleaver is basically finished.
interleaving are mutually reciprocal processes, the delays of
the two channels are opposite. Therefore, the address V. DESIGN SIMULATION RESULTS
allocation of the deinterleaver can be obtained by simply The read/write address generation scheme of the second
inverting the address allocation of the interleaver. That is, the chapter is implemented in VHDL language. The read/write
address allocation of the 0th channel of the interleaver address generation module w_r_addcreat.vhd is designed.
becomes the 11th channel of the deinterleaver, and the The corresponding deinterleaving read/write address
address allocation of the 11th channel becomes the 0th generation module is de_w_r_addcreat.vhd. The
channel of the deinterleaver. Counter 0 is changed from 11 to implementation of RAM uses the RAM module that comes
0, and the other parts remain unchanged. Therefore, both the
with Quartus. In order to observe the output of the
interleaver and the deinterleaver can be implemented in
deinterleaver, the sequential sequence generation module
Fig. 4, except that the counter 0 is counted differently.
seq.vhd is designed. The waveforms obtained by ModelSim
simulation are as follows:

Figure 5. interleaver read and write address output

Figure 6. Deinterleaver read and write address output

Figure 7. Interleaving and Deinterleaver Data Output

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 From the simulation results, Fig. 5 shows that the
interleaver write address sequentially outputs 0, 1, 19, 54,
106, 175, 261, 364, 484, 621, 775, 946, 0, 2, 20, 55.....
repeatedly repeating this cycle, and the read address lags by
one (except for the 0th channel); Fig. 6 shows that the
deinterleaver write address sequentially outputs 0, 188, 359,
513, 650, 770, 873, 959, 1028, 1080, 1115, 1133, 1, 189....,
the read address is one beat behind; Fig. 7 shows that the
data output by the deinterleaver is random until the data in
the interleaver's RAM is filled. and then the deinterleaver
outputs the correct data after a delay of 12 × (12-1) × 17 =
2244 clock cycles. The above design is consistent with the
original intention.
VI. CONCLUDING REMARKS
In this paper, the VHDL language design and
implementation of the convolutional interleaver and
deinterleaver are carried out according to the RS (204, 188)
code in the DOCSIS standard. Theoretically, the minimum
memory cell occupancy is I × M × (I -1) / 2 = 1122, and the
address bus number is 11b. The memory unit used in this
scheme is 1134, and the address bus number is 11b, which is
close to the minimum storage unit occupancy. Compared
with block interleaving, convolutional interleaving can save
memory resources, reduce interleaving delay, and simplify
circuit structure. It has the advantages of flexible design,
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reliable performance, and high integration. Therefore, it can
be applied in data link systems.
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