EE-341 Microelectronic Design

Assignment No. 3
Due Date: Mar. 3rd (On LMS 11:55pm)

Total Marks=60

Unless stated otherwise, in the following questions take V bias=1V, W/L=5, Vt =0.3V,
µn, upCox = 100µA/V2

Problem 1:
Design the MOS differential amplifier of Fig. 1 to operate at Vov = 0.2 V and to provide a trans-
conductance gm of 1 mA/V. Specify the W/L ratios and the bias current. The technology available
provides Vt = 0.8 V and μnCox = 90μA/V2. [10 Marks]

Fig. 1.

Problem 2:
Calculate the differential voltage gain of the circuits depicted in Fig. 2. Assume perfect symmetry and λ >
0. [15 Marks]

Fig. 2
Problem 3:
Calculate the common-mode gain of the circuit depicted in Fig. 3. Assume λ > 0, gmrO >> 1, and use the
relationship Av = -GmRout. [5 Marks]

Fig. 3

Problem 4:
Design the MOS differential pair of Fig. 4 for ΔVin,max = 0.3 V and a power budget of 3 mW. Assume
RD = 500Ω, λ = 0, unCox = 100 uA/V2, and VDD = 1.8 V. [10 Marks]

Fig. 4
Problem 5: In the circuit of Fig. 5, W/L = 10 um/0.18 um for M1-M4. Assume an input CM level of 1.2
V. [20 Marks]

Fig. 5

Determine
(a) The output dc level through DC analysis.
(b) The small-signal gains Vout/(Vin1 - Vin2) and VX/(Vin1 - Vin2).
(c) The change in the output dc level if W4 changes by 5%.