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SG2525A SG3525A: Regulating Pulse Width Modulators
SG2525A SG3525A: Regulating Pulse Width Modulators
® SG3525A
.. INTERNAL SOFT-START
PULSE-BY-PULSE SHUTDOWN
INPUT UNDERVOLTAGE LOCKOUT WITH
. HYSTERESIS
LATCHING PWM TO PREVENT MULTIPLE
DIP16 16(Narrow)
. PULSES
DUAL SOURCE/SINK OUTPUT DRIVERS
DESCRIPTION
The SG3525A series of pulse width modulator inte- turn off through the PWM latch with pulsed shut-
grated circuits are designed to offer improved per- down, as well as soft-start recycle with longer shut-
formance and lowered external parts count when down commands. These functions are also control-
used in designing all types of switching power sup- led by an undervoltage lockout which keeps the out-
plies. The on-chip + 5.1 V reference is trimmed to ± puts off and the soft-start capacitor discharged for
1 % and the input common-mode range of the error sub-normal input voltages. This lockout circuitry in-
amplifier includes the reference voltage eliminating cludes approximately 500 mV of hysteresis for jitter-
external resistors. A sync input to the oscillator al- free operation. Another feature of these PWM cir-
lows multiple units to be slaved or a single unit to be cuits is a latch following the comparator. Once a
synchronized to an external system clock. A single PWM pulses has been terminated for any reason,
resistor between the CT and the discharge terminals the outputs will remain off for the duration of the pe-
provide a wide range of dead time ad- justment. riod. The latch is reset with each clock pulse. The
These devices also feature built-in soft-start circuitry output stages are totem-pole designs capable of
with only an external timing capacitor required. A sourcing or sinking in excess of 200 mA. The
shutdown terminal controls both the soft-start circu- SG3525A output stage features NOR logic, giving a
ity and the output stages, providing instantaneous LOW output for an OFF state.
THERMAL DATA
Symbol Parameter SO16 DIP16 Unit
Rth j-pins Thermal Resistance Junction-pins Max 50 °C/W
Rth j-amb Thermal Resistance Junction-ambient Max 80 °C/W
Rth j-alumina Thermal Resistance Junction-alumina (*) Max 50 °C/W
* Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 × 20 mm ; 0.65 mm
thickness with infinite heatsink.
BLOCK DIAGRAM
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SG2525A-SG3525A
ELECTRICAL CHARACTERISTICS
(V# i = 20 V, and over operating temperature, unless otherwise specified)
SG2525A SG3525A
Symbol Parameter Test Conditions Unit
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
VREF Output Voltage Tj = 25 °C 5.05 5.1 5.15 5 5.1 5.2 V
∆VREF Line Regulation Vi = 8 to 35 V 10 20 10 20 mV
∆VREF Load Regulation IL = 0 to 20 mA 20 50 20 50 mV
∆VREF/∆T* Temp. Stability Over Operating Range 20 50 20 50 mV
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SG2525A-SG3525A
SG2525A SG3525A
Symbol Parameter Test Conditions Unit
Min. Typ. Max. Min. Typ. Max.
PWM COMPARATOR
Minimum Duty-cycle 0 0 %
• Maximum Duty-cycle 45 49 45 49 %
• Input Threshold Zero Duty-cycle 0.7 0.9 0.7 0.9 V
Maximum Duty-cycle 3.3 3.6 3.3 3.6 V
* Input Bias Current 0.05 1 0.05 1 µA
SHUTDOWN SECTION
Soft Start Current VSD = 0 V, VSS = 0 V 25 50 80 25 50 80 µA
Soft Start Low Level VSD = 2.5 V 0.4 0.7 0.4 0.7 V
Shutdown Threshold To outputs, VSS = 5.1 V 0.6 0.8 1 0.6 0.8 1 V
Tj = 25 °C
Shutdown Input Current VSD = 2.5 V 0.4 1 0.4 1 mA
* Shutdown Delay VSD = 2.5 V Tj = 25 °C 0.2 0.5 0.2 0.5 µs
OUTPUT DRIVERS (each output) (VC = 20 V)
Output Low Level Isink = 20 mA 0.2 0.4 0.2 0.4 V
Isink = 100 mA 1 2 1 2 V
Output High Level Isource = 20 mA 18 19 18 19 V
Isource = 100 mA 17 18 17 18 V
Under-Voltage Lockout Vcomp and Vss = High 6 7 8 6 7 8 V
IC Collector Leakage VC = 35 V 200 200 µA
tr* Rise Time CL = 1 nF, Tj = 25 °C 100 600 100 600 ns
tf* Fall Time CL = 1 nF, Tj = 25 °C 50 300 50 300 ns
TOTAL STANDBY CURRENT
Is Supply Current Vi = 35 V 14 20 14 20 mA
* These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
• Tested at fosc = 40 KHz (RT = 3.6 KΩ, CT = 10nF, RD = 0 Ω). Approximate oscillator frequency is defined by :
1
f=
CT (0.7 RT + 3 RD)
. DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL where RL is the resistance
from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded.
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SG2525A-SG3525A
TEST CIRCUIT
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SG2525A-SG3525A
•
⋅
( ) Range over which the device is functional and parameter limits are guaranteed.
Figure 1 : Oscillator Charge Time vs. R T Figure 2 : Oscillator Discharge Time vs. R D
and C T . and C T .
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SG2525A-SG3525A
PRINCIPLES OF OPERATION
SHUTDOWN OPTIONS (see Block Diagram) ately set providing the fastest turn-off signal to the
Since both the compensation and soft-start termi- outputs ; and a 150 µA current sink begins to dis-
nals (Pins 9 and 8) have current source pull-ups, charge the external soft-start capacitor. If the shut-
either can readily accept a pull-down signal which down command is short, the PWM signal is termi-
only has to sink a maximum of 100 µA to turn off the nated without significant discharge of the soft-start
outputs. This is subject to the added requirement of capacitor, thus, allowing, for example, a convenient
discharging whatever external capacitance may be implementation of pulse-by-pulse current limiting.
attached to these pins. Holding Pin 10 high for a longer duration, however,
will ultimately discharge this external capacitor, re-
An alternate approach is the use of the shutdown cir- cycling slow turn-on upon release.
cuitry of Pin 10 which has been improved to en-
hance the available shutdown options. Activating Pin 10 should not be left floating as noise pickup
this circuit by applying a positive signal on Pin 10 could conceivably interrupt normal operation.
performs two functions : the PWM latch is immedi-
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SG2525A-SG3525A
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SG2525A-SG3525A
Figure 8. Figure 9.
For single-ended supplies, the driver outputs are In conventional push-pull bipolar designs, forward
grounded. The VC terminal is switched to ground by base drive is controlled by R1 - R3. Rapid turn-off
the totem-pole source transistors on alternate oscil- times for the power devices are achieved with
lator cycles. speed-up capacitors C1 and C2.
Figure 10. Figure 11.
The low source impedance of the output drivers pro- Low power transformers can be driven directly.
vides rapid charging of Power Mos input capaci- Automatic reset occurs during dead time, when both
tance while minimizing external components. ends of the primary winding are switched to ground.
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SG2525A-SG3525A
mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA
a1 0.51 0.020
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
DIP16
Z 1.27 0.050
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SG2525A-SG3525A
mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA
A 1.75 0.069
a2 1.6 0.063
C 0.5 0.020
c1 45˚ (typ.)
e 1.27 0.050
e3 8.89 0.350
M 0.62 0.024
SO16 Narrow
S 8˚(max.)
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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SG2525A-SG3525A
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quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-
croelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
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