An Efficient Scheme to Diagnose Scan Chains
Sridhar Narayanan and Ashutosh Das
Sun Microelectronics
Sun Microsystems Inc.
Mountain View, CA 94043-1100
Abstract
The scan chain needs to operate correctly to utilize
the scan features in a design. The presence of defects
in the chain can invalidate the test and debug method-
ology for a design. In this paper we present a novel
strategy t o eficiently diagnose a scan chain. The main
i d e a is to a d d circuitry t o a scan f l o p to enable its
scan-out port to be either set or reset. Use of this cir-
cuitry requires no additional control signals, and has
no impact on the timing of the design. Based on this
set/reset feature, we then present a global strategy t o
eficiently incorporate it in a scan design. This strategy
takes into account disparities in the defect probabilities
and controllability/observability attributes of f l o p s an a
scan chain. A n algorithm t o optimally modify a subset
of the flops to maximize diagnostic resolution is de-
scribed. Experimental results on two devices highlight
the advantages of the proposed strategy.
1 Introduction
The use of scan design techniques to efficiently test
and debug sequential circuits is a widely accepted in-
dustrial practice. In scan design, some or all sequen-
tial elements or flip-flops in a circuit are linked into
one or more scan chains [1]. This permits data to be
serially shifted into and out of these flip-flops, greatly
enhancing the controllability and observability of in-
ternal nodes in the design. In using scan to test and
debug a design, it is imperative that the scan chain(s)
not be defective. This will prevent reliable data from
being shifted in and out of the chain and invalidate the
testing of other parts of the logic.
If the scan chain is found to be defective, the exact
location of the defect should be diagnosed. Rapidly
identifying root causality of failure is vital to enable
correction and subsequent use of the scan chain for
test/debug purposes. The problem becomes all the
more important with decreasing feature sizes and in-
creasing device complexity. This leads to designs with
a large number of scan flip-flops. For example, the
UltraSPARC-I1 processor has greater than 22000 scan
flops connected in a single scan chain [a].Similarly
UltraSPARC is a trademark of Sun Microsystems Inc.
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there exist designs in which the logic circuitry associ-
ated with scan occupies as much as 30% of the area [3].
The main focus of this paper is on a novel scheme t o
efficiently diagnose defects in a scan chain. The basic
idea is to provide a reset/set capability t o the scan-out
port of a flop. This reset/set capability is achieved by
means of simple circuitry added to the scan flop. In
Section 3, we describe the details of this circuitry and
its use in diagnosing a scan chain. Ideally this circuitry
can be added to every scan flop to provide maximum
diagnostic resolution. However if the area overhead is
found to be unacceptable, we provide ways to trade-
off diagnostic resolution with the associated area over-
head. An algorithm is designed to modify only a subset
of the scan flops while maximizing the diagnostic reso-
lution. A key feature of this algorithm is that it takes
into account the non-uniform probabilities of poten-
tial defects in a scan chain, as well as disparit,ies in the
controllability and observability attributes of flops.
The presence of random or systematic defects in the
scan chain depend on a number of parameters. Some
of these parameters, such as the underlying technology
and process features, also influence potential defects
in non-scan related logic. In addition defects in the
scan chain are a function of parameters such as the
design o f the scan flops, the placement and routing
configuration of the scan chain, and the density of scan
flops in particular blocks in the design. As will be
described in Section 4.1, our diagnosis scheme takes
into account these parameters in trading off diagnostic
resolution against the area overhead.
Defects in the scan chain can manifest in a number
of ways. In this paper we abstract potential defects in
the chain into a fault model based on single stuck-at
faults [4]. This model assumes that nets (or wires) con-
nected to the scan-in or scan-out ports of a scan flop
are inadvertently tied to ground or the supply volt-
age. Our current work is focussed on extending the
diagnosis scheme to different fault models.
2 Previous Work
The most common way to diagnose a defective scan
chain is by means of E-beam probing. A binary
search scheme can be employed to potentially locate
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 the faulty node in logaN steps, where P i represents the
number of flops in the scan chain [5]. The e-xtremely
limited observability in today’s multi-layer metal tech-
nologies however places constraints on its use. Any
form of deprocessing to enhance observability could
inadvertently damage the part and invalidate the di-
agnosis effort.
To minimize test application time, a common design
practice is to break a single scan chain into multiple
scan chains [6]. This also enhances the diagnosability CLH
SE I 1
of the overall scan configuration. Limited I/O avail-
(b)
ability as well as tester capabilities however place con.-
straints on the number of such multiple chaias. In [7],
the use of flush and shift tests are advocated to test the Cyde Number
S””,values

integrity of the scan chain. In this paper, we employ m o p 1 Flap2 Flop3 Flap4 Flop5
a variation on the flush test as a means to boiih detect 0 x x X X X
I o x X X X
and diagnose scan chain failures. The use of the shift 2 0 0 X X X
test t o diagnose defects other than stuck-at faults is 3 0 0 1 X X
A 0 0 0 1
currently being investigated. 5 0 0 0 1
X
I + FaullDetecled
In [8], scan chain diagnosability is achieved at the Clock Held Low and SE pulsed I“1->0->1
expense of introducing complex XOR. gates between 5* 0 0 1 0 0
6 0 0 1 1 0
consecutive flops in a scan chain. A significant cost 7 0 0 1 1 1 t- Fault Dmgmosd
of the technique is the use of an additional control
signal that needs to be routed to the scan fjip-flops. (4
This increases both the routing area overhead and the Figure 1: (a) Dual-clock scan flop design, (b) Example
control complexity. A unique feature of our design scan chain of five flops with a single stuck-at-1 fault,
scheme is the sole use of existing signals being routed (c) Scan chain state in detection and diagnosis phases
to each scan flop. This in turn ensures no impact on
the routing overhead and control complexity. circuitry used to diagnose the scan chain. The basic
In [3], a combination of primary inputs/outputs concept can be applied to other variations of scan flop
along with the combinational logic is used to diag- designs.
nose the scan chain. Although no area overhead is
In Figure l ( b ) , we show an example scan chain of
introduced, the diagnosis procedure involves the use
five scan flops. To test whether the scan chain is work-
of complex test generation software. The use of such
ing properly, both a sequence of “Os” and a sequence
software could potentially increase the diagnosis time.
of ‘1s” are shifted into the chain. This is done in the
In addition, all defects in the chain are not guaranteed
following manner: the scan enable signal is set t o 1,
t o be diagnosed and any defects in the combinational
and a sequence of 0’s are applied to the SI port while
logic could invalidate the diagnosis.
pulsing the clock five times. At the end of the fifth
clock, a 0 should be observed at SO. Similar steps are
3 Flop-based Diagnosis followed when shifting in a sequence of 1’s.
Defects in the scan chain however will invalidate this
3.1 Diagnosing a Scan Chain test. In Figure l ( b ) , we show the scan output of flop
Incorporating scan in a circuit requires that the 3 being stuck-at-1. Hence when shifting in O’s, while
design of flip-flops be modified to enable data to be a fault-free scan chain will output a 0 at SO after five
shifted from one flop t o the next in a scan chain. A clocks, the chain in Figure l(b) will output a 1. At
large number of variations exist in incorporaiing scan this point, although we have detected a fault in the
functionality to a flip-flop [l, 2, 4,91. In Figure L(a), scan chain, the exact location of the fault is unknown.
we show one possible implementation of a x a n flip- Note that the stuck-at-1 fault could be located at the
flop based on selecting clocks locally. The scan enable scan outputs of any of the five flops.
signal (SE) which is routed to every scan flop is used Let us assume that all five flops in the chain had an
t o demultiplex the clock locally into a functional clock asynchronous reset control signal that could reset their
(DCLK) and a scan clock (SCLK). When SE is equal scan-out ports to 0. After shifting 0’s and detecting a 1
t o 0, the flop accepts input from D,, as a result of a at SO after five clocks, we assert this reset signal while
clock pulse at DCLK. Similarly when SE is equal to 1, keeping the clock inactive. The clock is now restarted
the flop accepts input from S,, as a result of a clock with SE equal to 1 and with 0’s input at SI. On the
pulse at SCLK. This dual-clock flip-flop will be used first clock a 0 is obtained at SO. However on the next
to illustrate the underlying principle of the set/reset clock, a 1 is obtained at SO due to the stuck-at fault

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at the scan output of flop 3. The presence of the 1
identifies that the defect is located between flop 3 and
flop 4 in the scan chain.
A similar sequence of steps can be used to detect
a single stuck-at-0 fault in the scan chain. In such a
case, a 0 would be detected at SO after shifting 1’s
for five clocks, and an asynchronous set signal would
need t o be provided for each flop. As pointed out ear-
lier, we need t o avoid the routing overhead and control
complexity of providing each flop with a reset or set
control signal. This is done by means of the circuitry
shown in Figure 2(a) for an example dual-clock scan
flop. The circuitry added t o reset the scan-out port is
shown in the dotted box
Let us now assume that all five flops in the scan Last shift clock edge in detection phase First shift clock of diagnosis phase
chain of Figure l ( b ) are modified as shown in Fig-
ure 2(a). After a 1 is detected at SO after five clocks,
the following sequence of operations is performed. The
clock is held low after the fifth clock, and SE is pulsed
from 1 t o 0 and back again t o 1. The net result of this
signal transition on SE is t o force the scan-out ports of
all flops t o reset t o 0. The diagnosis can now be per-
SE s
formed by restarting the clock with 0’s applied at SI.
The table in Figure l(c) shows the scan-out values at
all five flops in the detection and diagnosis phases. The
(b)
x’s represent unknown values since the initial state of
the scan chain is non-deterministic. The 5’ cycle rep- Figure 2: (a) Reset/set circuitry in dual-clock scan
resents the state of the scan chain after pulsing the SE flop, (b) Timing diagram of scan signal transitions
signal with the clock in a low state.
In the diagnosis scheme, we have made the implicit However when SCLK is held low and the scan enable
assumption that both the clock and the scan enable signal transitions from 1 t o 0, a pulse of width Tdelay
signal can be controlled. If these signals are being is generated at the output of the NOR gate and this
generated by an IEEE 1149.1-compatible TAP con- is sufficient to activate the pulldown path and reset
troller [lo], the required signal transitions can be gen- the scan-out port. The timing diagram in Figure 2(b)
erated in an unused state of the TAP state diagram. shows the transitions of the key signals. It is this tran-
On the other hand if control of these signals is being sition on the scan enable signal with the clock in a low
provided from device pins, the required transitions can state that is used in the diagnosis.
easily be generated.
The addition of this circuitry enables the scan-out
3.2 Details of Set/Reset Circuitry port of a flop to be either set or reset. If the scan-
out port needs to be set to 1, the pulldown circuitry
In this section, we briefly elaborate on the design is attached to the alternate node in the j a m latch, i.e.,
modifications required in the scan flop t o either set or node 2 instead of node 1 in Figure 2(a). This will en-
reset the scan-out port. Consider the design shown in able diagnosis of stuck-at-0 faults in the scan chain.
Figure 2(a) consisting of a dual-clock scan flop. As The additional circuitry used in Figure Z(a) can be
part of the design, the path from the Q output to the easily adapted for other scan flop designs. The details
scan slave portion is controlled by SCLK. The addi- of how it can be incorporated will depend on the spe-
tional circuitry t o reset the scan-out port consists of cific design of the flop. As an example in Figure 3(a)
just twelve transistors. This can potentially be reduced we show a multiplexed data scan flop design with a
to eight transistors by merging the three inverters into separate scan slave latch [4]. In Figure 3(b) we show
a single one. how the circuitry is incorporated in the flop to reset
During functional modes (when SE is equal t o 0) or the scan-out port.
during scan shifting (when SE is equal t o l ) ,the output A 1 to 0 transition on the scan enable signal also oc-
of the NOR gate (marked A) is 0 and the pulldown curs when test patterns are shifted into the scan chain,
path is disabled. The pulldown path is also disabled and applied to the non-scan logic via the Q ports of
when the scan enable signal transitions from 0 to 1 the flops. The only caveat when incorporating the cir-
for modes such as a dump of the scan chain or when cuitry for any generic flop is to ensure that the Q port
shifting out the results of scan test patterns. does not get inadvertently set or reset when applying

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CLK
(9)
“ The probability of a defect occurring at nets tied
Data/scan mmter
and data slave
.
extra circuitry to reset acan-out port
Al!
I flops that are more likely to have defects in their
I scan nets.
,--__-
_---____
(b)
Figure 3: (a) Multiplexed data scan flop design, (b)
Reset/set circuitry incorporated in design
such test patterns. Such a case might occur when both
the Q port and scan-out port in a flop share the same
slave latch. In these cases one should ensure that scan
enable only toggles with the clock high when applying
test patterns. In the scan designs of Figures 2 arid 3,
note that the added circuitry only affects the itimiiig in
the scan portion of the flop, and has no timing impact
on the functional path.
4 Global Methodology
One way of incorporating the set/reset circuitry to
a scan design is t o modify all flops in the scan chain.
Every adjacent pair of flops in the cha,in can be rnod-
ified with a reset and set option respectively. In this
way any single stuck-at-0 or stuck-at-1 fault can be
diagnosed down t o a pair of flops. Assuming that 10
transistors are added per flop, this would require to-
tal of approximately 220K transistors for a design such
as the UltraSPARC-I processor.
Adding the set/reset circuitry should therefore be
done on a selective basis so as to optimize the diagnos-
ability of the chain. In deciding which flops t o modify,
we require a way t o evaluate the diagnosablility of a
scan chain. Prior t o doing so, we make the observa-
tion that all flops in the chain should not be treated
equally with respect t o diagnosis. In the next section
we discuss how certain flops by virtue of their defect
probability and/or controllability and observabi1it:y at-
tributes are more “important” than otlhers when cliag-
nosing the scan chain.
4.1 Measures of flop diagnosatbility
In the scan chain of a device, certain flops (aremore
susceptible to defects as compared to others. Simillarly
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certain flops are more easily observed and controlled
with regard to diagnosis than others. These dispari-
ties, both in defect probability as well as in the control-
lability/observability attributes of the flop, need t o be
considered in any diagnosis scheme for the scan chain.
We outline some examples of the underlying reasons
for such disparities.
o
t o the scan-in and scan-out ports of a flop is a
function of the length and other routing features
of these nets. For example inter-block scan nets
are in general longer than intra-block scan nets.
Even within a block, the routing congestion and
length of scan nets provides a way to identify scan
o Dynamic scan flops or static flops that lie in dy-
namic logic blocks are in closer proximity to clock
routing and more susceptible to noise glitches,
coupling and other crosstalk effects.
ab Scan flops that lie in areas of high power density
due to routing and placement congestion are more
likely to be affected by process and power supply
variations. Power analysis either through simula-
tion or with thermal imaging of actual silicon can
potentially identify such “hot” flops.
ai The placement and layout methodology used in
different blocks also influences flop disparities
with regard to diagnosis. For example in data-
path and certain standard-cell blocks, flops are
often placed in groups, rows or as registers. The
scan chain routing for flops within a flop group is
often done through abutment, and explicit scan-
in and scan-out nets are only used for the flops at
the ends of the flop group. The ”end” flops are
thus better candidates for adding the reset/set cir-
cuitry.
(11 The physical location of scan flops in the design
influences their observability attributes. For ex-
amples, flops in the center of the die and with less
clock and power routing above them are easier to
observe during failure analysis.
a Scan flops that are directly fed by primary inputs,
or flops that have observability from probe pads or
directly feed primary outputs are inherently more
controllable and/or observable. Enhancing the di-
agnosability of such flops should be of a lower
priority. Conversely flops embedded deep within
logic should be given higher priority. A control-
labilitylobservability analysis [4,111 could poten-
tially be used to quantify these attributes.
In modifying flops with the set/reset feature, we
must factor in the above mentioned disparities as well
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 1 2 3 A 5 6 I 8
I I I 1 I I
Weigh&! 1 1 1 1 1 1 1 1
(8)
1 2 3 4 5 6 1 8
Weights 1 3 2 1 1 1 1 1
(b)
Figure 4: (a) Scan chain of eight equal weight flops,
(b) Scan chain of eight flops with different weights
as other disparities particular to the scan flops in a
given design. In the context of this paper we ab-
stract these disparities into a model based on assigning
weights to the flops in the scan chain. These weights
reflect the relative ”importance” of the flops when di-
agnosing the scan chain. For example flops with a
higher weight are either more likely to possess defects
and/or more difficult t o control or observe. The num-
ber of different weights assigned t o the flops and their
relative values will depend on the characteristics of
the design. Our global methodology imposes no con-
straints on the actual values (fractional or integer) of
the weights, or the number of such weights assigned to
the different flops in the scan chain.
4.2 Scan Chain Diagnosability
Using the concept of flop weights, let us consider
a way to evaluate the diagnosability of a scan chain.
As a first step, we partition this into two separate
cost functions based on the fault being diagnosed, i.e.
SAl-diagnosability and SAO-diagnosability. The SA1-
diagnosability is a measure of a chain’s diagnosability
with respect t o a single stuck-at-1 fault. It is a func-
tion of the number and location of flops enhanced with
the reset feature. Similarly the SAO-diagnosability de-
pends on the number and location of flops enhanced
with the set feature. We restrict our discussion to SA1-
diagnosability; similar results can be derived for SAO-
diagnosability.
Consider the scan chain of eight flops shown in Fig-
ure 4(a) in which all flops have an equal weight of 1.
Use of an all-zero test sequence can only detect the
presence of a stuck-at-1 fault in one of the nine nets
between the scan-in and scan-out ports of the flops. No
diagnosability information is provided. To enhance the
SAl-diagnosability, let us now add the reset circuitry
t o two flops in the scan chain. Intuitively the “best”
flops t o modify are flop 3 and flop 6 (these are shaded
in the figure). This divides the scan chain into three
segments of approximately equal length.
In the detection phase, the all-zero sequence will
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Flop Weight Scan-in Scan-out Total
No (Wt) count count count
1 3
1 1 1 2
2 1 2 1 3
6 1 3 0 3
7 1 1 1 2 1 3
8 1 1 2 1 1 3
output a 1 at SO after eight clock cycles if there exists
a single stuck-at-1 fault in the chain. After pulsing the
scan enable signal, we enter the diagnosis phase. If a 0
is obtained at SO after two clock cycles of the diagnosis
phase, this informs us that the stuck-at-1 fault is not
located in the segment between the scan-out of flop 6
and the SO port. If however a 1 is obtained at SO
after five clock cycles of the diagnosis phase, we have
diagnosed the stuck-at-1 fault to be in the segment
between the scan-out port of flop 3 and the scan-in port
of flop 6. Thus adding the reset circuitry to flops 3 and
6 enables any single stuck-at-1 fault to be diagnosed
to one of the three segments.
To quantify the chain diagnosability, let us analyze
how placing the reset circuitry at flops 3 and 6 makes
the chain more “diagnosable” than placing them at two
other flops. The basic idea is to evaluate two counts for
each flop: (1) the number of nets between a controlla-
bility point and the flop’s scan-in port, referred to as
its scan-zn count, and ( 2 ) the number of nets between
the flop’s scan-out port and an observability point, re-
ferred to as its scan-out count. The sum of these two
counts is referred to as the flop’s total count. The total
count of a flop is a measure of its diagnosability in the
scan chain. The lower the total count of a flop, the
more diagnosable it is within the chain, i.e., its scan-in
port is more easily controlled and its scan-out port is
more easily observed.
In addition to the device scan-in pin (a controllabil-
ity point) and the device scan-out pin (an observability
point), the scan-out ports of flops modified with the re-
set circuitry act as both controllability and observabil-
ity points. For example with flop 4 in Figure 4(a), one
net exists between the scan-out port of flop 3 (a con-
trollable point) and its scan-in pin, and two nets exist
between its scan-out port and the scan-out port of flop
6 (an observable point). Similarly for flop 2, two nets
exist between the device SI and its scan-in port, and
one net exists between its scan-out port and flop 3’s
scan-out port (an observable point). With flops 3 and 6
modified with reset circuitry, the scan-in, scan-out and
total counts for each of the eight flops in Figure 4(a)
are shown in Table 1.
The SAl-diagnosability is given by the sum of the

Flop Weight Scan-in
No (Wt) count
+-E-/
1 1 1 1
2 3 2 O 2-
3 2 1 --
4 1 2 1
5 1 3 0
6 1 1 3 4
7 1 2 2 4
8 1 3 1 4 4
Table 2: Counts for 8 Aops in scan chain of Fig. 4(b)
total counts for all flops in the scan chain. I[n the ex-
ample of Figure 4(a), this evaluates i,o a value of 24.
This in fact is the mznzmum over all 28, i.e., ‘(5’2, cliffer-
ent ways in which two flops can be modified with the
reset circuitry. Our goal is t o determine such optimal
configurations by adding reset circuitry to minimize
the value of the SAl-diagnosability, and hence maxi-
mize the diagnostic resolution. If no reset ciircuitry is
added to the scan chain in Fig 4(a), the value of the
SAl-diagnosability is equal to 72 since every flop has a
total count of 9. Conversely, if all eight flops are mod-
ified with the reset circuitry, the SAJ-diagnosabilil,y
equals 9 since flops 1 t o 7 will have a total count of 1,
and flop 8 will have a total count of 2.
In Figure 4(b), we show another scan chain of eight
flops with the only difference being that flops 2 and 3
have weights of 3 and 2 respectively, as compared to
a weight of 1 in Figure 4(a) . This scan chain with
no reset circuitry is inherently more daflcult t o diag-
nose than the scan chain in Figure 4(a) with no re-
set circuitry. This difference is reflected in the SAIL-
diagnosability value by multzplyzng the total count
(TC) of each flop by its corresponding weight. For
the scan chain in Figure 4(b), this leads to a SAIL-
diagnosability value of 99 with no reset circuitry. As a
comparison, the scan chain in Figure 4(a) has a SAIL-
diagnosability of 72 with no reset circuitry. If two flops
in a scan chain have equal total counts, multiplying the
total count by their respective weights allow us to dis-
tinguish the relative importance of the two flops with
respect t o diagnosis. By capturing this in the SAI-
diagnosability value, we can target the flop with the
higher weight as a better candidate for the reset cir-
cuitry.
If two flops in the chain of Figure 4(b) are to be
optimally modified with the reset circuitry, the “best”
flops t o modify are flops 2 and 5 (these are shaded in
the figure). In Table 2, we show the counts for each flop
in the scan chain of Figure 4(b) for the case where flops
2 and 5 are modified with reset circuitry. By modify-
ing flops 2 and 5 the SAl-diagnosability is equal to 3%.
This is the minimum value over all 28 different ways in
which two flops can be modified, and thus represents
an optimal solution. On the other hand, if flops 2 and
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6 are modified with reset circuitry, as was the optimal
case in Figure 4(a), the SAl-diagnosability would be
equal to 36. Note how the flop weights skew the posi-
tions of the “best’) flops to modify in minimizing the
SAl-diagnosability.
5 Optimization Algorithm
5.1 Problem Statement
To establish a simple mathematical framework in
which to discuss the optimization problem, we make
use of the following terminology. Let the scan chain
in a design consist of a set of N flops { f i , f 2 , . . . , fiv}
ordered from the device scan-in to the device scan-out.
The weight Wi of a scan flop fi (1 5 i N ) IS <
‘ a mea-
sure of its relative “importance” in the scan chain with
respect to diagnosis. Note that the number of different
weights must be less than or equal to N .
Statement of Optimization Problem
-
Given a scan design with N flops { fi , f2, . . . , f ~ and
}
V i 1 5 i _< N , the weight of fi is Wi, and given that
k (1 5 k 5 N ) flops are to be modified with the reset
circuitry, determine the location of the flops so as to
minimize the SAl-diagnosability, and hence maximize
diagnostic resolution.
Formulating the optimization problem in the above
manner provides an efficient way t o tradeoff diagnos-
ability with the area overhead of the reset circuitry.
The problem can be solved for different values of k to
study the associated tradeoffs. The first step in solving
the problem is to simplify the evaluation of the SAl-
diagnosability. Given a scan chain with k flops modi-
fied with the reset circuitry, the SAl-diagnosability is
evaluated by determining the total count for each flop,
multiplying this count by the flop’s weight and sum-
ming up this product for all flops. An alternate way to
evaluate the SAl-diagnosability that is more amenable
to analysis is through the use of chain segments.
Dc$nition 1 - A chain segment CS is an ordered set
-
of flops starting either at the device scan-in port or at
the first flop after a ”modified” flop, and ending at a
”modified” flop or at the device scan-out port.
-
Dt$nition 2 - The length Lj of a chain segment CSj
is given by the number of flops in the segment, and the
weight WSj of the chain segment is the sum of the
weights of all flops in the segment.
Consider the scan chain with two modified flops
shown in Figure 4(b). The scan chain consists of
three segments: (1) CS1 consisting of flop 1 and 2
with L1 = 2 and WS1 = 4, ( 2 ) CS2 consisting of
flops 3, 4 and 5 with L2 = 3 and WS2 = 4, and (3)
CS3 consisting of flops 6 , 7 and 8 with L3 = 3 and
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709
W S , = 3 . Given any scan chain in which k flops are
modified with the reset circuitry, one can easily evalu-
+
ate the IC 1 chain segments (CS1, CS,, . . . , CSs+l}.
The SAl-diagnosability is given by the following equa-
tion:
j=k
C(Lj* WSj) + WSk+l(Lk+l+
j=1
The equivalence of the above equation with our ear-
lier scheme for evaluating SAl-diagnosability can be
easily seen from the following observations. All flops
in a chain segment have identical total counts equal
to the length of the segment. Adding the weights of
the flops in the segment and multiplying by the length
of the segment is equivalent to individually multiply-
ing the total count of each flop in the segment by its
corresponding weight, and summing over all flops in
the segment. The second term in the above equation
deals with the last chain segment where the "+1" ac-
counts for the net between the last flop and the device
scan-out port. Based on the above equation the SA1-
diagnosability for the scan chain in Figure 4(b) is given
+
by 2(4) 3(4) +
3(4) = 32.
5.2 Use of Dynamic Programming
A brute force approach t o solve the optimization
problem for a given value of k is to enumerate all NCk
different options and use equation 1 to evaluate the
SAl-diagnosability for each one. The configuration
with the minimum value of SAl-diagnosability is cho-
sen as the optimal. Such an approach would lead to an
algorithm of complexity O ( N k ) . This would be com-
putationally expensive for large values of k .
A more elegant and computationally efficient way
t o solve the problem is through the use of dynamic
programming [ 121. Dynamic programming makes use
of two aspects in our optimization problem. The first
is that an optimal solution t o the complete problem
contains within it optimal solutions to subproblems.
Assume that in an optimal solution, we know that the
position of the first "modified" flop closest to the de-
<
vice SI is at x (1 5 x N ) . Based on this we can evalu-
ate the contribution of CS1 to the SAl-diagnosability.
This is done by adding the weights of all flops from 1
to x and multiplying it by 2. What remains in solving
the problem is t o modify k - 1 flops in the remaining
N - a flops in the scan chain. This subproblem needs
t o be optimally solved to ensure that the complete so-
lution is optimal. This optimal substructure is essential
to the use of dynamic programming [12].
The second aspect in using dynamic programming is
that solutions t o subproblems can be evaluated, stored
and reused when determining an optimal solution to
the complete problem. For example consider the scan
chain of Figure 4(b). In determining a solution with
le = 2, one option considered would have been t o mod-
ify flop 3 and flop 4. Based on this we evaluate the
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710
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Weights 1 3 2 1 1 1 1 1
1) (1)
I
Figure 5: Dynamic programming table for scan chain
in Figure 4(b)
sum of the contributions of the three segments t o de-
termine the SAI-diagnosability. Instead of evaluating
the SAl-diagnosability from scratch for other possible
solutions, such as flop 3 and flop 5, or flop 3 and flop
6 , a more effective way is to store the contribution of
modifying flop 3 . Note that once flop 3 is modified,
the first chain segment is fixed and its contribution
to the SAl-diagnosability is independent of the second
flop chosen to be modified. This reuse of solutions t o
subproblems is exploited in the dynamic programming
technique. The optimization technique based on dy-
namic programming used in this paper has similarities
to the technique described in [6].
5.3 Details of Algorithm
To illustrate the use of dynamic programming, let
us consider how an optimal solution is obtained for
the scan chain in Figure 4(b), assuming two flops are
to be modified with the reset circuitry, i.e., k = 2.
The dynamic programming technique makes use of the
table shown in Figure 5 consisting of 3 rows and 8
columns. In general, the number of rows will corre-
+
spond to IC 1, the number of chain segments, and the
number of columns will correspond to N , the number
of scan flops. The scan chain from Figure 4(b) with
no modified flops is reproduced above the table in Fig-
ure 5.
The columns in the table are ordered from 1 t o N
identical to the order of the flops in the scan chain.
Associated with column j (1 5 j 5 N ) is the weight
of the flop at position j in the scan chain. The rows in
the table are numbered from 1 to k 1 and each row +
+
i (1 5 i 5 IC 1) corresponds t o the set of segments
(CS1, . . . , CSi}. The table is filled starting from row
1 to determine the different possible configurations for
CS1. The position of the first flop closest to SI that
can be "modified" with reset circuitry can range from
flop 1 to flop 7 . Flop 8 is not a viable candidate since
we need to modify a second flop as well. In each of the
possible cases, we evaluate the contribution of CS1
assuming the corresponding flop is to be modified.
For example, in row 1 and column 4 (shaded in the
 table), we store the contribution of CS1 assuming flop
4 is the first flop closest to SI t o be modifed. Th.is
is evaluated by multiplying the length of CS1, i.e., 4
by the sum of the weights of the first four flops in the
chain, i.e., 7. Hence a value of 28 is evaluated for the
corresponding location in the table. This is stored as
a 2-tuple (4, 28) where 4 represents the length of CS1
and 28 is the contribution of CS1 t o the overall SA1-
diagnosability. Similarly all columns from 1t o 7 can be
filled in row 1. The algorithm then fills up the second
row to determine possible locations for the seconld flop
t o be modified, and hence the contributions of both
CS1 and CSZ.
Consider the location in row 2 and column 5 (shaded
in the table), where we assume that flop 5 is thi-= sec-
ond flop closest t o SI to be modified. If flop 5 is the
second flop t o be modified, the first flop can lie in any
position ranging from 1 t o 4. We eva,luate the contri-
butions of CS1 and CSZfor each of these four possible
options, and pick the one with the minimumvalue. For
example, if flop 3 and flop 5 are to be modified, the
total contribution is evaluated as ( L z * W S ~ ) I +
(stored
contribution of CS1). Here L2 is equal to 12, i.e., (5-
3); WS2 is the sum of the weights of flops 4 and 5 ,
and the stored contribution of CS1 is availa,ble in the
third column in row 1. This evaluates to 2*2 18 =
22. Similarly this is evaluated for the remaining three
options, i.e., flop 1 and flop 5, flop 2 and flop 5 , and
flop 4 and flop 5 . The minimum occurs when ilop 2
and flop 5 are modified, and this is stored as a 2-tuple
(3, 20) where 3 represents the length of CS2 and 20
represents the contribution of both CS1 and CS2 to
the overall SAl-diagnosability. In this way, all entries
in row 2 for columns 2 to 8 are respectively evaluated
and stored.
As discussed in the previous section, we optimally
solve subproblems in the course of arriving at a solu-
tion to the complete problem. For example the (3, 20)
in row 2 and column 5 represents an optimal solution
to the subproblem of optimally modifying two flops
with flop 5 being the second flop. Similarly by storing
the optimal solutions t o these subproblems, we save on
recomputation at later stages in the a1goritb.m.
The single entry in row 3 corresponds to the csntri-
butions of CS1, CS, and CS3, and hence repiresen ts an
optimal solution t o the complete problem. In evduat-
ing this entry, we consider all the {CSI,CS;!}OF t'ions
stored in row 2 of the table. This is equivalent to as-
suming the second modified flop lies in the range 2: t o 8,
and determining the additional contribution of CS3 i,n
each case. The minimum value over these seiven cases
represents an optimal solution t o the problem. For ex-
ample, if we assume that the second "modified" flop is
flop 4, the contribution of CS3 is given by W&(L:~+l),
i.e., 4(4 +l ) , which equals 20. This is added t'o the
contribution of CS1 and CSz stored in row 2 and col-
umn 4, leading t o a total SAl-diagnosability value of
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20+ 14 = 34. In this way, the SAl-diagnosability value
is evaluated for all 7 options. The minimum value of
32 for the SAl-diagnosability is obtained when flops
2 and 5 are modified. This is stored as a 2-tuple (3,
341) in the third row, where 3 represents the length of
C S , in the optimal solution and 32 is the value of the
optimal SAl-diagnosability.
Complexity Analysis
To generate an optimal solution for a scan chain
of N flops in which k flops are to be modified, a
table of /e +
1 rows and N columns is used. The
weights of the flops are preprocessed and stored in
a cumulative weight array { a l ,~ 2 , . .. , a ~ such
} that
a, is the sum of the weights of flops 1 to i, i.e.,
+ +
a, = W1 + Wz . . . Wi. Generating this array is
of time complexity O ( N ) . Filling an entry in row 1 of
the table for any column is of constant time complex-
ity. It involves multiplying the column number with
the corresponding entry in the cumulative weight ar-
ray. To fill an entry in row i (2 i 5 k ) and column
j (2 5 j 5 N ) requires in the worst case N differ-
ent options to be evaluated. Evaluating the value of
each option is of constant time complexity since it in-
vches a multiplication followed by adding the stored
+ contribution in the previous row. Hence choosing the
minimum over N options and filling the corresponding
entry is of order O ( N ) . Since there are a maximum of
klV entries in the table, the complexity of the dynamic
programming algorithm is O ( k N 2 ) .
6 Experimental Results
The dynamic programming algorithm was imple-
mented in the Perd programming language, and used
to analyze the diagnosability of a single scan chain
of 2813 flops in ASIC-I. The order of scan flops in
the chain was decided as part of the design process of
the ASIC device. The ASIC has a number of FIFO
structures and register buffers, as well as a number of
complex control blocks. The scan chain encompasses
all scan flops in the blocks within the device as well
as scan flops at the 1/0 pins. To apply our diagnosis
methodology, the weights of flops in the scan chain are
abstracted as follows: (a) all scan flops at the I/Os
are assigned a weight of 0.5; (b) all scan flops at block
bclundaries involved in inter-block scan routes are as-
1 signed a weight of 5 ; (c) all scan flops with an existing
reset capability are assigned a weight of 0; (d) all scan
flaps within a complex control block are assigned a
wcight of 10, and (e) every other scan flop is assigned
a weight of 1. The weight factors reflect the relative
inxportance of the scan flops with respect to diagnos-
ability as discussed in Section 4.1. For example flops
at the I/Os are given a low weight since they are ob-
servable at the pins, and similarly flops in the single
complex control block are given a higher weight based
on their controllability/observability attributes.
Paper 29.3
71 1
 Number of Optimal SA1
modified flops Diagnosability
(4
Table 3: SAl-diagnosability values for scan chain in ASIC-I
If none of the flops are modified with the reset cir-
cuitry, the SAl-diagnosability of the chain is equal to
11568720. In Table 3 we show the results of using
the methodology in this paper t o optimize the SA1-
diagnosability of the chain. The number of flops mod-
ified with the reset circuitry ( k ) is varied from 1 t o 10.
In the second column in Table 3, we show the asso-
ciated optimal SAl-diagnosability based on the use of
the dynamic programming algorithm. In the third col-
umn, the SAl-diagnosability of the chain is shown as-
suming k flops are modified at equal intervals along the
scan chain. The next column shows the percentage im-
provement in SAl-diagnosability in using an optimal
solution as compared to modifying flops at equal in-
tervals along the chain, i.e., the improvement reflected
in column 2 over the value in column 3. This is ex-
pressed as a percentage of the SAl-diagnosability value
for equal length segments.
In the last column, we show the percentage of maxi-
mum diagnostic resolution achieved by optimally mod-
ifying k flops. The maximum scan chain diagnos-
tic resolution or equivalently the minimum value of
SAl-diagnosability is obtained by modifying all 2813
flops in the scan chain with reset circuitry. This mini-
mum value of the SAl-diagnosability is equal t o 4085.5
for the scan chain in ASIC-I. The following ratio is
evaluated for each row in Table 3; the difference be-
tween the SAl-diagnosability with no modified flops
and the value in the second column divided by the dif-
ference between the SAl-diagnosability with no flops
and the minimum value of SAl-diagnosability with
2813 modified flops. This ratio is expressed as a per-
centage in the last column in Table 3. For example
with 3 modified flops, this percentage is evaluated as
(11568720 - 2620972) * 100/(11568720 - 4085.5) which
is equal t o 77.4%.
A number of observations can be made based on
the data in Table 3. By optimally modifying k flops as
compared to modifying k flops at equal intervals along
the chain leads to an average improvement of 11% for
the ASIC device. In general this improvement in SA1-
diagnosability is a function of the relative weights of
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SAl-diagnosability Percentage Percentage of
(equal length improvement maximum chain
segments) I (equal length) I diagnosability I
the scan flops and “skews” in their respective posi-
tions in the scan chain. The improvement will increase
both with a larger disparity in flop weights, and if the
higher weight flops are not positioned uniformly in the
scan chain. Note that optimally modifying 4 flops is
sufficient to attain 80% of the maximum possible di-
agnostic resolution. As the number of modified flops
is increased, diminishing returns are obtained with re-
spect to diagnosis. Modifying 10 flops further increases
the value to 92%; a 12% increase over the optimal case
with 4 modified flops. The table clearly illustrates the
tradeoffs available between scan chain diagnosability
and the area overhead of the reset circuitry.
In Table 4. we show results for a section of the single
scan chain in the UltraSPARC-I processor as the num-
ber of modified flops varies from 1 t o 6. As mentioned
earlier, the UltraSPARC-I has greater than 22000 flops
and the section chosen for Table 4 includes about one
fifth of the scan flops. The weight distribution cho-
sen is similar to that used for the ASIC device. Flops
at the I/Os are assigned a weight of 0.5; flops within
some control and datapath blocks in the grouping logic
unit are assigned a weight of 8 (due to the density of
placement and routing); flops with probe pads at their
scan ports or with reset signals are given a weight of
0; flops within a particular RAM are assigned a weight
of 4 (based on observability attributes); and all other
flops are assigned a weight of 1.
7 Conclusion and Future Work
In this paper, we have presented a comprehensive
methodology to efficiently diagnose a scan chain for
single stuck-at faults. Use of the reset/set circuitry in
concert with the dynamic programming algorithm is
an effective way to enhance the diagnosability of the
scan chain. Although we have restricted our discussion
to SAl-diagnosability, similar results can be obtained
for SAO-diagnosability. A different set of flop weights
could potentially be used when optimizing the SAO-
diagnosability. For example flops modified with the
reset circuitry to optimize SAl-diagnosability must be
given a weight of 0 since they cannot be modified with

1 11918380
2 7273312
3 5464645
4 4056150
5 3461938
6 2883166
Table 4: SAl-diagnosability values for section of scan chain in UltraSPARC-I
the set circuitry as well. Similarly the weights of other
flops can be changed t o reflect their importance with
regard to stuck-at-0 fault diagnosis.
T~ enhance the diagnosis scheme, current work is
focussed on the following aspects.
The set/reset circuitry can potentially be used to
diagnose other defects such as bridging, coupling
and delay faults. For example use of two adja-
cent flops modified with the set and reset circuitry,
respectively, provides a way to introduce a ”10”
within the scan chain. This feature can be used 1,o
detect and diagnose other scan chain fault modes
The use of IDDQ-based diagnosiis is being inves-
tigated. For example if the scan output of it flop
with a stuck-at-1 fault is reset, a crowbar current
is induced based on the time required to reset the
scan output. Sensitive IDDQ circuitry could po-
tentially detect this increase in power supply cur-
rent.
The assignment of weights to flops has been done
in an ad-hoc basis in this paper. A more quantita-
tive approach t o determine weights based on flop
characteristics with respect to diagnosis needs to
be studied.
In our diagnosis scheme we have assumed that a
single stuck-at fault exists in the chain. To diag-
nose multiple stuck-at faults would require some
form of reconfiguration so that the scan-out ports
of flops within a scan chain can be dil-ectky ob-
served at the device scan-out pin.
In this paper, we have assumed a fixed ordering of
flops in the scan chain. Diagnosibility can be im-
proved by reordering the flops to make i,he dlistri-
bution of higher weight flops moire uniform dong
the chain.
References
[l] E.B. Eichelberger and T . W . Williams. Alogiic de-
sign structure for testability. In Proc., 14th Design
Automation Conf.,pages 462-468, June 1977.
[2] M. E. Levitt et al. Testability, Debuggaibility and
Manufact urability Features of t hle U1t ra SPARC-I
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Percentage Percentage of
improvement maximum chain
(equal length) diagnosability
nigi9022
-7944751
5960066
4766454
3973378
3405465
Microprocessor. In Proc. IEEE Int’l Test Conf.,
pages 157-166, October 1995.
[.3] s. Kundu. On Diagnosis of Faults in a Scan Chain.
In Proc. IEEE VLSI Test Symp., pages 303-308,
Ami1 1993.
[4]M. Abramovici, M. A. Breuer, and A. D. Fried-
man. Digital Systems Testing and Testable De-
sign. IEEE Press, 1990.
[5] Kaushik De and A. Gunda. Failure Analysis
for Full-scan Circuits. In Proc., IEEE Int’1 Test
Conf., pages 636-645, October 1995.
[6] S. Narayanan, R. Gupta, and M.A. Breuer. Op-
timal configuring of multiple scan chains. IEEE
Trans. on Computers, 42(9):1121-1131, Septem-
ber 1993.
[7] R.G. Bennetts. Design of Testable Logic Circuits.
Addison-Wesley Publishing, 1984.
[8] S. Edirisooriya and G. Edirisooriya. Diagnosis of
Scan Path Failures. In Proc. IEEE VLSI Test
Symp., pages 250-255, April 1995.
[!,I H. Ando. Testing VLSI with random access scan.
In Proc., COMPCON, pages 50-52, 1980.
[lo]IEEE Standard 1149.1-1990. IEEE Standard
Test Access Port and Boundary Scan Architec-
ture. IEEE Standards Board, New York, N.Y.,
1990.
[l’l] L.H. Goldstein. Controllability and observability
analysis of digital circuits. IEEE Trans. Circuzts
and Systems, 26:685-693, 1979.
[12] F. Cormen, C. E. Leiserson, and R. L. Rivest. In-
troduction to Algorithms. The MIT Press, Cam-
bridge, Massachusetts, 1990.
Paper 29.3
713