VISHAL RAI

A91005119002

B. Tech ECE

Digital Electronics

Experiment 1: Familiarization with the logic gates.

OR Gate

• IC Number: 7432

• IC Diagram

• Truth Table:

INPUT 1 INPUT 2 OUTPUT

0 0 0
0 1 1
1 0 1
1 1 1
 Circuit:

• Output:
AND Gate

• IC Number: 7408

• IC Diagram:

• Truth Table:

INPUT 1 INPUT 2 OUTPUT

0 0 0
0 1 0
1 0 0
1 1 1
• Circuit:

• Output:
NOT Gate

• IC Number: 7404

• IC Diagram:

• Truth Table:

INPUT OUTPUT
0 1
0 1
1 0
1 0
• Circuit:

• Output:
NAND Gate

• IC Number: 7400

• IC Diagram:

• Truth Table:

INPUT 1 INPUT 2 OUTPUT

0 0 1
0 1 1
1 0 1
1 1 0

• Circuit:
• Output:
NOR Gate

• IC Number: 7402

• IC Diagram:

• Truth Table:

INPUT 1 INPUT 2 OUTPUT

0 0 1

0 1 0

1 0 0

1 1 0
• Circuit:

• Output:
XOR Gate

• IC Number: 7486

• IC Diagram:

• Truth Table:

INPUT 1 INPUT 2 OUTPUT

0 0 0
0 1 1
1 0 1
1 1 0

• Circuit:
• Output
XNOR Gate

• IC Number: 747266

• IC Diagram:

• Truth Table:

INPUT 1 INPUT 2 OUTPUT

0 0 1

0 1 0

1 0 0

1 1 1
• Circuit:

• Output:
 Experiment 2: Simplifying Boolean Expressions

Expression 1 : F1 = xy + xy’

Simplification :

Schematic Diagram:
Truth Table:

x y F1 Simplified Expression : x

0 0 0 0

0 1 0 0

1 0 1 1

1 1 1 1

Simulation Result:
Expression 2 : F2 = (x+y)(x+y’)

Simplification :

Schematic Diagram:
Truth Table:

x Y F2 Simplified Expression : x

0 0 0 0

0 1 0 0

1 0 1 1

1 1 1 1

Simulation Result:
Expression 3: F3 = xyz+x’y+xyz’

Simplification :

Schematic Diagram:
Truth Table:

x y z F3 Simplified Expression : y
0 0 0 0 0
0 0 1 0 0
0 1 0 1 1
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 1

Simulation Result:
Expression 4: F4 = zx+zx’y

Simplification :

Schematic Diagram:
Truth Table:

X y z F4 Simplified Expression : z(x+y)

0 0 0 0 0

0 0 1 0 0

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 1 1

1 1 0 0 0

1 1 1 1 1

Simulation Result:
Expression 5: F5 = (x+y)’(x’+y’)’

Simplification :

Schematic Diagram:
Truth Table:

x y z F5 Simplified Expression :
0
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 0 0

Simulation Result:
Expression 6: F6 = y(wz’+wz) + xy

Simplification :

Schematic Diagram:
Truth Table:

x y z w F6 Simplified Expression :
y(w+x)
0 0 0 0 0 0

0 0 0 1 0 0

0 0 1 0 0 0

0 0 1 1 0 0

0 1 0 0 0 0

0 1 0 1 1 1

0 1 1 0 0 0

0 1 1 1 1 1

1 0 0 0 0 0

1 0 0 1 0 0

1 0 1 0 0 0

1 0 1 1 0 0

1 1 0 0 1 1

1 1 0 1 1 1

1 1 1 0 1 1

1 1 1 1 1 1
Simulation Result:
Expression 7: F7 = abc+a’b’c+a’bc+abc’+a’b’c’
Simplification :

Schematic Diagram:
Truth Table:

a b c F7 Simplified Expression :
ab+bc+a’b’
0 0 0 1 1

0 0 1 1 1

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 0 0

1 1 0 1 1

1 1 1 1 1
Simulation Result:
Expression 8: F8 = bc+ac’+ab+bcd
Simplification :

Schematic Diagram:
Truth Table:

a b c d F8 Simplified Expression : bc+ac’

0 0 0 0 0 0

0 0 0 1 0 0

0 0 1 0 0 0

0 0 1 1 0 0

0 1 0 0 0 0

0 1 0 1 0 0

0 1 1 0 1 1

0 1 1 1 1 1

1 0 0 0 1 1

1 0 0 1 1 1

1 0 1 0 0 0

1 0 1 1 0 0

1 1 0 0 1 1

1 1 0 1 1 1

1 1 1 0 1 1

1 1 1 1 1 1
Simulation Result:
 Simplifying Boolean Expressions (Contd.)

Expression 1: xy + x’y’z’+x’yz’

• Simplification :

• Schematic Diagram :
Truth Table :

X y z F1 Simplified Expression :
xy+x’z’
0 0 0 1 1

0 0 0 1 1

0 0 1 0 0

0 0 1 0 0

0 1 0 1 1

0 1 0 1 1

0 1 1 0 0

0 1 1 0 0

1 0 0 0 0

1 0 0 0 0

1 0 1 0 0

1 0 1 0 0

1 1 0 1 1

1 1 0 1 1

1 1 1 1 1

1 1 1 1 1
• Simulation Result :
Expression 2: A’B+BC’+B’C’

• Simplification :

• Schematic Diagram :
Truth Table :

A B C F2 Simplified Expression :
A’B+C’

0 0 0 1 1

0 0 0 1 1

0 0 1 0 0

0 0 1 0 0

0 1 0 1 1

0 1 0 1 1

0 1 1 1 1

0 1 1 1 1

1 0 0 1 1

1 0 0 1 1

1 0 1 0 0

1 0 1 0 0

1 1 0 1 1

1 1 0 1 1

1 1 1 0 0

1 1 1 0 0
• Simulation Result :
Expression 3: a’b’+bc+a’bc’

• Simplification :

Schematic Diagram :
Truth Table :

A b c F3 Simplified Expression :
a’+abc

0 0 0 1 1

0 0 0 1 1

0 0 1 1 1

0 0 1 1 1

0 1 0 1 1

0 1 0 1 1

0 1 1 1 1

0 1 1 1 1

1 0 0 0 0

1 0 0 0 0

1 0 1 0 0

1 0 1 0 0

1 1 0 0 0

1 1 0 0 0

1 1 1 1 1

1 1 1 1 1
• Simulation Result :
Expression 4 : xy’z+xyz’+x’yz+xyz

• Simplification :

• Schematic Diagram :
Truth Table :

X y z F4 Simplified Expression :
xy+yz+xz
0 0 0 0 0

0 0 0 0 0

0 0 1 0 0

0 0 1 0 0

0 1 0 0 0

0 1 0 0 0

0 1 1 1 1

0 1 1 1 1

1 0 0 0 0

1 0 0 0 0

1 0 1 1 1

1 0 1 1 1

1 1 0 1 1

1 1 0 1 1

1 1 1 1 1

1 1 1 1 1
• Simulation Result :
Expression 5 : A’D+DB+B’C+B’AD

• Simplification :

Schematic Diagram :
Truth Table :

A B C D F5 Simplified Expression :
D+B’C
0 0 0 0 0 0

0 0 0 1 1 1

0 0 1 0 1 1

0 0 1 1 1 1

0 1 0 0 0 0

0 1 0 1 1 1

0 1 1 0 0 0

0 1 1 1 1 1

1 0 0 0 0 0

1 0 0 1 1 1

1 0 1 0 1 1

1 0 1 1 1 1

1 1 0 0 0 0

1 1 0 1 1 1

1 1 1 0 0 0

1 1 1 1 1 1
• Simulation Result :
Expression 6 : ABD+A’C’D’+A’B+A’CD’+AB’D’

• Simplification :

• Schematic Diagram :
Truth Table :

A B C D F6 Simplified Expression :
BD+BA’+B’D’

0 0 0 0 1 1

0 0 0 1 0 0

0 0 1 0 1 1

0 0 1 1 0 0

0 1 0 0 1 1

0 1 0 1 1 1

0 1 1 0 1 1

0 1 1 1 1 1

1 0 0 0 1 1

1 0 0 1 1 1

1 0 1 0 0 0

1 0 1 1 0 0

1 1 0 0 0 0

1 1 0 1 1 1

1 1 1 0 0 0

1 1 1 1 1 1
• Simulation Result :
Expression 7 : K’LM’+K’M’N+KLM’N’+LMN’

• Simplification :

• Schematic Diagram :
Truth Table :

K L M N F7 Simplified Expression :
LN’+K’M’N

0 0 0 0 1 1

0 0 0 1 0 0

0 0 1 0 1 1

0 0 1 1 0 0

0 1 0 0 1 1

0 1 0 1 1 1

0 1 1 0 1 1

0 1 1 1 1 1

1 0 0 0 1 1

1 0 0 1 0 0

1 0 1 0 1 1

1 0 1 1 0 0

1 1 0 0 0 0

1 1 0 1 1 1

1 1 1 0 0 0

1 1 1 1 1 1
• Simulation Result :
Expression 8: A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D

• Simplification :

• Schematic Diagram :
Truth Table :

A B C D F8 Simplified Expression :
B’D’+A’BD+ABC’
0 0 0 0 1 1

0 0 0 1 0 0

0 0 1 0 1 1

0 0 1 1 0 0

0 1 0 0 0 0

0 1 0 1 1 1

0 1 1 0 0 0

0 1 1 1 1 1

1 0 0 0 1 1

1 0 0 1 0 0

1 0 1 0 1 1

1 0 1 1 0 0

1 1 0 0 1 1

1 1 0 1 1 1

1 1 1 0 0 0

1 1 1 1 0 0
• Simulation Result :
Expression 9 : x’z+w’xy’+wx’y+wxy’

• Simplification :

• Schematic Diagram :
• Truth Table :
w x y z F9 Simplified Expression :

0 0 0 0 0 0

0 0 0 1 1 1

0 0 1 0 0 0

0 0 1 1 1 1

0 1 0 0 1 1

0 1 0 1 1 1

0 1 1 0 0 0

0 1 1 1 0 0

1 0 0 0 0 0

1 0 0 1 1 1

1 0 1 0 1 1

1 0 1 1 1 1

1 1 0 0 1 1

1 1 0 1 1 1

1 1 1 0 0 0

1 1 1 1 0 0
• Simulation Result :
 Experiment 3: Realization of Adder Circuits

Half Adder –

Schematic Diagram:

o Using XOR Gate

Simulation Result:
 o Without Using XOR Gate

Simulation Result:
Truth Table :

A B SUM CARRY

(A⊕B) From (AB) From

Simulation Simulation
0 0 0 0 0 0
0 1 1 1 0 0
1 0 1 1 0 0
1 1 0 0 1 1

Analysis :

The result of the truth table and that obtained by simulating the designed circuit, are both
ending up to be the same. Thus confirming that the design of the half adder circuit is correct.
Full Adder –

Schematic Diagram and Simulation Result :

o Using XOR Gate

Simulation Result:
o Without using XOR Gate
Truth Table :

A B C SUM CARRY

(A⊕B⊕C) From (A⊕B).C + AB From

Simulation Simulation
0 0 0 0 0 0 0
0 0 1 1 1 0 0
0 1 0 1 1 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 0
1 0 1 0 0 1 1
1 1 0 0 0 1 1
1 1 1 1 1 1 1

Analysis :

The result of the truth table and that obtained by simulating the designed circuit, are both
ending up to be the same. Thus confirming that the design of the full adder circuit is correct.
 Experiment 4: Realization of Full Subtractor Circuit

Schematic Diagram:

Simulation Result :
Truth Table :

Bin A B DIFFERENCE BORROW

(A⊕B⊕Bin) From ((A⊕B). Bin)’+ A’B From

Simulation Simulation
0 0 0 0 0 0 0
0 0 1 1 1 1 1
0 1 0 1 1 0 0
0 1 1 0 0 0 0
1 0 0 1 1 1 1
1 0 1 0 0 1 1
1 1 0 0 0 0 0
1 1 1 1 1 1 1

Analysis :

The result of the truth table and that obtained by simulating the designed circuit, are both
ending up to be the same. Thus confirming that the design of the full subtractor circuit is
correct.
 Experiment 5: Realisation of Adder Circuit with a Carry Lookahead Generator

• Schematic Diagram :
• Truth Table :

i=3 i=2 i=1 i=0

Ai 1 1 1 0
Bi 0 1 1 0
Input Carry (Ci) 1 1 0 0
Sum (Si) 0 1 0 0
Output Carry (Ci+1 ) 1 1 1 0

• Simulation :
Inputs for A – A0 , A1 , A2 , A3 (From top to bottom)

Inputs for B– B0 , B1 , B2 , B3 (From top to bottom)

Outputs – S0 , S1 , S2 , S3 , C4 (From top to bottom)

 Experiment 6: Realisation of Multiplexer Circuit

2 x 1 Multiplexer

• Schematic Diagram :

o S – Select Line
o Io – Input 1
o I1– Input 2

• Truth Table:

S Output of MUX
0 I0
1 I1

• Simulation :
 U4 – Output of 2 x 1 MUX
DSTM3 – I1
DSTM2 – I0

4 x 1 Multiplexer

• Schematic Diagram :

o S0 – Select Line 1
o S1 – Select Line 2
o Io – Input 1
o I1– Input 2
o I2– Input 3
 o I3– Input 4

• Truth Table:

S1 S0 Output of MUX

0 0 Io
0 1 I1
1 0 I2
1 1 I3

• Simulation :
U14 – Output of 4 x 1 MUX
DSTM9 – I3
DSTM8 – I2
DSTM6 – I1
DSTM5 – I0
8 x 1 Multiplexer

• Schematic Diagram :

o S0 – Select Line 1
o S1 – Select Line 2
o S2 – Select Line 3
o Io – Input 1
o I1– Input 2
o I2– Input 3
o I3– Input 4
o I4– Input 5
o I5– Input 6
o I6– Input 7
o I7– Input 8
• Truth Table:

S2 S1 S0 Output of MUX
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

• Simulation :
U26 – Output of 8 x 1 MUX
DSTM20 – I7
DSTM19 – I6
DSTM18 – I5
DSTM17 – I4
DSTM16 – I3
DSTM15 – I2
DSTM14 – I1
DSTM13 – I0
 Experiment 7: Realisation of De-Multiplexer Circuit

1 x 2 De-Multiplexer

• Schematic Diagram :

o S – Select Line
o Do – Output 1
o D1– Output 2

Truth Table:

S D0 D1
0 I0 0
1 0 I1

• Simulation :
U6 – Do
U7 – D1
U4 – Input to DeMUX
 4 x 1 Multiplexer

• Schematic Diagram :

o S0 – Select Line 1
o S1 – Select Line 2
o Do – Output 1
o D1– Output 2
o D2– Output 3
o D3– Output 4

• Truth Table:
 S1 S0 D0 D1 D2 D3

0 0 Io 0 0 0

0 1 0 I1 0 0

1 0 0 0 I2 0

1 1 0 0 0 I3

• Simulation :
U17 – Do
U18 – D1
U20 – D2
U21 – D3
U14 – Input to DeMUX
8 x 1 Multiplexer

• Schematic Diagram :

o S0 – Select Line 1
o S1 – Select Line 2
o S2 – Select Line 3
o Do – Output 1
o D1– Output 2
o D2– Output 3
o D3– Output 4
o D4 – Output 5
o D5– Output 6
o D6– Output 7
o D7– Output 8
Truth Table:
S2 S1 S0 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 I0 0 0 0 0 0 0 0
0 0 1 0 I1 0 0 0 0 0 0

0 1 0 0 0 I2 0 0 0 0 0
0 1 1 0 0 0 I3 0 0 0 0
1 0 0 0 0 0 0 I4 0 0 0
1 0 1 0 0 0 0 0 I5 0 0
1 1 0 0 0 0 0 0 0 I6 0
1 1 1 0 0 0 0 0 0 0 I7

• Simulation :
U30 – Do
U31 – D1
U32 – D2
U34 – D3
U35 – D4
U36 – D5
U37 – D6
U38 – D7
U26 – Input to DeMUX
 Experiment 8: Realisation of Encoder Circuit

4 x 2 Encoder

• Schematic Diagram :

• Truth Table:

D0 D1 D2 D3 A B

1 0 0 0 0 0

0 1 0 0 0 1

0 0 1 0 1 0

0 0 0 1 1 1
• Simulation :
U8 - A
U9- B
8x 3 Encoder
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

• Schematic Diagram :

• Truth Table:

• Simulation :
U19 - A
U18- B
U17- C
 Experiment 9: Realisation of Decoder Circuit

2 x 4 Decoder

• Schematic Diagram :

A B D0 D1 D2 D3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1
• Truth Table:
• Simulation

3 x 8 Decoder

• Schematic Diagram :
• Truth Table:

A B C D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

• Simulation :