Programmable Logic Array (PLA)

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One way to design a combinational logic circuit it to get gates and connect them with wires. One
disadvantage with this way of designing circuits is its lack of portability.

You can now get chips called PLA (programmable logic arrays) and "program" them to implement
Boolean functions. I'll explain what it means to program a PLA.

Fortunately, a PLA is quite simple to learn, and produces nice neat circuits too.


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The first part of a PLA looks like:

Each variable is hooked to a wire, and to a wire with a NOT gate. So the top wire is
and the one
just below is its negation, 
.

Then there's  and just below it, its negation,  .

The next part is to draw a vertical wire with an AND gate. I've drawn 3 of them.

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Truth table:

  

 

  
  
 
 
   

Each of the vertical lines with an AND gate corresponds to a minterm. For example, the first AND
gate (on the left) is the minterm: 
  .

The second AND gate (from the left) is the minterm: 

 .

The third AND gate (from the left) is the minterm:

  .

I've added a fourth AND gate which is the minterm:

 .

The first three minterms are used to implement . The third and fourth minterm are used to
implement  .

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Now you might complain. How is it possible to have a one input AND gate? Ho w can three inputs be
hooked to the same wire to an AND gate? Isn't that invalid for combinational logic circuits?

That's true, it is invalid. However, the diagram is merely a simplification. I've drawn the each of AND
gate with three input wires, which i s what it is in reality (there is as many input wires as variables).
For each connection (shown with a black dot), there's really a separate wire. We draw one wire just
to make it look neat.

The vertical wires are called the AND plane. We often leave ou t the AND gates to make it even
easier to draw.

We then add OR gates using horizontal wires, to connect the minterms together.

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Again, a single wire into the OR gate is really 4 wires. We use the same simplification to make it
easier to read.

The horizontal wires make up the OR plane.

This is how the PLA looks when we leave out the AND gates and the OR gates. It's not that the
AND gates and OR gates aren't there ---they are, but they've been left out to make the PLA even
easier to draw.

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‰iven  variables, it would seem necessary to have

 vertical wires (for the AND gates), one for
each possible minterm. However,
 grows VERY quickly. So, sometimes there aren't
 vertical
wires.

You can generally get around the problem by n ot connecting the wire to each of the three variables.
For example, you could just have a product term
 or even simply  .

For the purpose of implementing truth tables, we'll usually tell you not to simplify, and to let each
vertical line be a minte rm.

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What does it mean to program a PLA? See the black dots? Those are connections made between
wires. In effect "programming" the wires means to make the connections within the PLA.
Configurable might be a better word than programmable, but that's the name that stuck.

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Programming a PLA is pretty simple. It simply involves filling out black dots for the minterms in the
AND plane and connecting the minterms together in the OR plane.

A cc (PLA) is a programmable device used to implement combinational

logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of

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programmable OR gate planes, which can then be con ditionally complemented to produce an
output. This layout allows for a large number of logic functions to be synthesized in the sum of
products (and sometimes product of sums) canonical forms.

One application of a PLA is to implement the control over a datapath. It defines various states in an
instruction set, and produces the nex t state (by conditional branching). [eg. if the machine is in state
2, and will go to state 4 if the instruction contains an immediate field; then the PLA should define the
actions of the control in state 2, will set the next state to be 4 if the instructi on contains an immediate
field, and will define the actions of the control in state 4]. Programmable Logic Arrays should
correspond to a state diagram for the system.

Other commonly used programmable logic devices are PAL, CPLD and FP‰A.

Note that the use of the word "programmable" does not indicate that all PLAs are field-
programmable; in fact many are mask -programmed during manufacture in the same manner as a
mask ROM. This is particularly true of PLAs that are embedded in more complex and numerous
integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are
called FPLA (Field -programmable PLA).

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MMI PAL 16R6 in 20 -pin DIP

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AMD 22V10 in 24-pin DIP

The term cc (PAL) is used to describe a family of programmable logic

device semiconductors used to implement logic functions in digital circuits introduced by Monolithic
Memories, Inc. (MMI) in March 1978. [1] MMI obtained a registered trademark on the term PAL for
use in "Programmable Semiconductor Logic Circuits". The trademark is currently held by Lattice
Semiconductor.[2]

PAL devices consisted of a small PRO M (programmable read -only memory) core and additional
output logic used to implement particular desired logic functions with few components.

Using specialized machines, PAL devices were "field -programmable". Each PAL device was " one-
time programmable" (OTP), meaning that it could not be updated and reused after its initial
programming. (MMI also offered a similar family called HAL, or "hard array logic", which were like
PAL devices except that they were mask -programmed at the factory.)

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Before PALs were introduced, designers of digital logic circuits would use small-scale integration
(SSI) components, such as those in the 7400 series TTL (transistor-transistor logic ) family; the 7400
family included a variety of logic building blocks, such as gates (NOT, NAND, NOR, AND, OR),
multiplexers (MUXes) and demultiplexers (DEMUXes), flip flops (D-type, JK, etc.) and others. One
PAL device would typically replace dozens of such "discrete" logic packages, so the SSI business
went into decline as the PAL business to ok off. PALs were used advantageously in many products,
such as minicomputers, as documented in Tracy Kidder's best-selling book "The Soul of a New
Machine."

PALs were not the first commercial programmable logic devices; Signetics had been selling its field
programmable logic array (FPLA) since 1975. These devices were completely unfamiliar to most
circuit designers and were perceived to be too difficult to use. The FPLA had a relatively slow
maximum operating speed (due to having both programmable -AND and programmable -OR arrays),
was expensive, and had a poor reputation for testability. Another factor limiting the acceptance of
the FPLA was the large package, a 600 -mil (0.6", or 15.24 mm) wide 28-pin dual in-line package
(DIP).

The project to create the PAL device was managed by John Birkner and the actual PAL circuit was
designed by H. T. Chua.[3] In a previous job, Birkner had developed a 16 -bit processor using 80
standard logic devices. His experience with standard logic led him to believe that user
programmable devices would be more attractive to users if the devices were design ed to replace
standard logic. This meant that the package sizes had to be more typical of the existing devices,

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"variable") series, the types of OLMCs available in each PAL were fixed at the time of manufacture.
(The PAL16L8 had 8 combinational outputs and the PAL16R8 had 8 registered outputs. The
PAL16R6 had 6 registered and 2 combinational while the PAL16R4 had 4 of each.) Each output
could have up to 8 product terms (effectively AND gates), however the combinational outputs used
one of the terms to control a bidirectional output buffer. There were other combinations that had
fewer outputs with more product term per output and were available with active high outputs. The
16X8 family or registered devices had an XOR gate before the register. There were also similar 24 -
pin versions of these PALs.

This fixed output structure often frustrated designers attempting to optimize the utility of PAL
devices because output structures of different types were often required by their applications. (For
example, one could not get 5 registered outputs with 3 active high combinational outputs.) So, in
June 1983 AMD introduced the 22V10, a 24 pin device with 10 output logic macrocells. [5] Each
macrocell could be configured by the user to be combinational or registere d, active high or active
low. The number of product term allocated to an output varied from 8 to 16. This one device could
replace all of the 24 pin fixed function PAL devices. Members of the PAL "V" ("variable") series
included the PAL16V8, PAL20V8 and PA L22V10.

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PALs were programmed electrically using binary patterns (as JEDEC ASCII/hexadecimal files) and
a special electronic programming system available from either the manufacturer or a third -party,
such as DATA/IO. In addition to single -unit device programmers, device feeders and gang
programmers were often used when more than just a few PALs needed to be programmed. (For
large volumes, electrical programming costs could be el iminated by having the manufacturer
fabricate a custom metal mask used to program the customers' patterns at the time of manufacture;
MMI used the term "hard array logic " (HAL) to refer to devices programmed in this way.)

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Though some engineers programmed PAL devices by manually editing files containing the binary
fuse pattern data, most opted to desi gn their logic using a hardware description language (HDL)
such as Data I/O's ABEL, Logical Devices' CUPL, or MMI's PALASM. These were computer-
assisted design (CAD) (now referred to as "design automation ") programs which translated (or
"compiled") the designers' logic equations into binary fuse map files used to program (and often
test) each device.

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The PALASM (from "PAL assembler") language was used to express boolean equations for the
outputs pins in a text file which was the n converted to the 'fuse map' file for the programming
system using a vendor-supplied program; later the option of translation from schematics became
common, and later still, 'fuse maps' could be 'synthesized' from an HDL (hardware description
language,) such as Verilog.

The PALASM compiler was written by MMI in FORTRAN IV on an IBM 370/1 68. MMI made the
source code available to users at no cost. By 1983, MMI customers ran versions on the DEC PDP-
11, Data ‰eneral NOVA, Hewlett-Packard HP2100, MDS800 and others.

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Data I/O Corporation released ABEL.

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Logical Devices, Inc. released the Universal Compiler for Programmable Logic (CUPL), which ran
under MSDOS on the IBM PC.

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Popular device programmers included Data I/O Corporation 's Model 60A Logic Programmer an d
Model 2900.

One of the very first PAL Programmers was the Structured Design "SD-20". They had the PALASM
software built-in and only required a CRT terminal to enter the equations and view the fuse plots.
After fusing, the outputs of the PAL could be verified if test vectors were entered in the source file.

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A  !"c or c!c (PLL) is a control system that tries to generate an output
signal whose phase is related to the phase of the input "reference" signal. It is an electronic circuit
consisting of a variable frequency oscillator and a phase detector. This circuit compares the ph ase
of the input signal with the phase of the signal derived from its output oscillator and adjusts the
frequency of its oscillator to keep the phases matched.The signal from the phase detector is used to
control the oscillator in a feedback loop.

Frequency is the derivative of phase. Keeping the input and output phase in lock step implies
keeping the input and ou tput frequencies in lock step. Consequently, a phase -locked loop can track
an input frequency, or it can generate a frequency that is a multiple of the input frequency. The
former property is used for demodulation, and the latter property is used for indirect frequency
synthesis.

Phase-locked loops are widely used in radio, telecommunications, computers and other electronic
applications. The y may generate stable frequencies, recover a signal from a noisy communication
channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a
single integrated circuit can provide a complete phase -locked-loop building block, the technique is
widely used in modern electronic devices, with output freque ncies from a fraction of a hertz up to
many gigahertz.


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For a practical idea of what is going on, consider an auto race. There are many cars, and each of
them wants to go around the track as fast as possible. Ea ch lap corresponds to a complete cycle,
and each car will complete dozens of laps per hour. The number of laps per hour (a speed) is a
frequency, but the number of laps (a distance) corresponds to a phase. At one instant, car 3 may
have gone 37.23 laps.

During most of the race, each car is on its own and is trying to beat every other car on the course.
However, if there is an accident, a pace car comes out to set a safe speed. None of the race cars is
permitted to pass the pace car (or the race cars in front of them), but each of the race cars wants to
stay as close to the pace car as it can. While it is on the track, the pace car is a reference, and the
race cars become phase-locked loops. Each driver will measure the phase difference (a distance in

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laps) between him and the pace car. If the driver is far away, he will increase his engine speed to
close the gap. If he's too close to the pace car, he will slow down. The result is all the ra ce cars lock
on to the phase of the pace car. The cars travel around the track in a tight group that is a small
fraction of a lap.

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Phase can be proportional to time, [1] so a phase difference can be a time difference. Clocks are,
with varying degrees of accuracy, phase -locked (time-locked) to a master clock.

Left on its own, each clock will mark time at slightly different rates. A wall clock, for example, might
be fast by a few seconds per hour compared to the reference clock at NIST. Over time, that time
difference would become substantial.

To keep his clock in synch, each week the owner compares the time on his wall clock to a more
accurate clock (a phase comparison), and he resets his clock. Left alone, the wall clock will continue
to diverge from the reference clock at the sam e few seconds per hour rate.

Some clocks have a timing adjustment (a fast -slow control). When the owner compared his wall
clock's time to the reference time, he noticed that his clock was too fast. Consequently, he could
turn the timing adjust a small amou nt to make the clock run a little slower. If things work out right,
his clock will be more accurate. Over a series of weekly adjustments, the wall clock's notion of a
second would agree with the reference time (within the wall clock's stability).

An early mechanical version of a phase -locked loop was used in 1921 in the Shortt-Synchronome
clock.

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Automatic synchronization of electronic oscillators was de scribed in 1923. [2] Earliest research
towards what became known as the phase -locked loop goes back to 1932, when British researchers
developed an alternative to Edwin Armstrong's superheterodyne receiver , the Homodyne or direct-
conversion receiver. In the homodyne or synchrodyne system, a local oscillator was tuned to the
desired input frequency and multiplied with the input signal. The resulting output signal included the
original modulation information. The in tent was to develop an alternative receiver circuit that
required fewer tuned circuits than the superheterodyne receiver. Since the local oscillator would
rapidly drift in frequency, an automatic correction signal was applied to the oscillator, maintaining it
in the same phase and frequency as the desired signal. The technique was described in 1932, in a
paper by Henri de Bellescize, in the French journal „
 
 .[3][4][5]

In analog television receivers since at least the late 1930s, phase -locked-loop horizontal and ve rtical
sweep circuits are locked to synchronization pulses in the broadcast signal. [6]

When Signetics introduced a line of monolithic integrated circuits that were complete phase -locked
loop systems on a chip in 1969, [7] applications for the technique multiplied. A few years later RCA
introduced the " CD4046" CMOS Micropower Phase-Locked Loop, which became a popular
integrated circuit.

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Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both
implementations use the same basic structure.

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Phase-locked loops are widely used for synchronization

   purposes; in space communications for
coherent demodulation and threshold [    ] extension, bit synchronization, and symbol
synchronization. Phase-locked loops can also be used to demodulate frequency-modulated signals.
In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a
reference frequency, with the same stability a s the reference frequency.

Other applications include:

a Demodulation of both FM and AM signals

a Recovery of small signals that otherwise would be lost in noise ( lock-in amplifier)
a Recovery of clock timing information from a data stream such as from a disk drive
a Clock multipliers in microprocessors that allow internal processor elements to run faster than
external connections, while maintaining precise timing relationships
a DTMF decoders, modems, and other tone decoders, for remote control and
telecommunications

·!cc

Some data streams, especially high -speed serial data streams (such as the raw stream of data from
the magnetic head of a disk drive), are sent without an accompanying clock. The receiver generates
a clock from an approximate frequency reference, and then p hase-aligns to the transitions in the
data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to
work, the data stream must have a transit ion frequently enough to correct any drift in the PLL's
oscillator. Typically, some sort of redundant encoding is used; 8B10B is very common.

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Many electronic systems include proce ssors of various sorts that operate at hundreds of megahertz.
Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a
lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the
processor. The multiplication factor can be quite large in cases where the operating frequency is
multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.

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All electronic systems emit some unwanted radio frequency energy. Various regulatory agencies
(such as the FCC in the United States) put limits on the emitted energy and any interference caused
by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating
frequency of the device, and a few harmonics). A system designer can use a spread -spectrum PLL
to reduce interference with high -Q receivers by spreading the energy ove r a larger portion of the
spectrum. For example, by changing the operating frequency up and down by a small amount
(about 1%), a device running at hundreds of megahertz can spread its interference evenly over a
few megahertz of spectrum, which drastically reduces the amount of noise seen on broadcast FM
radio channels, which have a bandwidth of several tens of kilohertz.

·!c"

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Typically, the reference clock enters the chip and drives a phase locked loop ( ), which then
drives the system's clock distribution. The clock distribution is usually balanced so that the clock
arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. Th e
function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the
phase and frequency of its output until the reference and feedback clocks are phase and frequency
matched.

PLLs are ubiquitous ²they tune clocks in systems several feet across, as well as clocks in small
portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all,
but rather a data stream with enough transitions that the PLL is able to recover a regular clock from
that stream. Sometimes the reference clock is the same frequency as the clock driven through the
clock distribution, other times the distributed clock may be some rational multiple of the reference.

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One desirable property of all PL Ls is that the reference and feedback clock edges be brought into
very close alignment. The average difference in time between the phases of the two signals when
the PLL has achieved lock is called the 

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(also called the 
" 

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). The variance between these phases is called
!c&

. Ideally, the static phase offset
should be zero, and the tracking jitter should be as low as possible.

Phase noise is another type of jitter observed in PLLs, and is caused by the oscillator itself and by
elements used in the oscillator's frequency control circuit. Some technologies are k nown to perform
better than others in this regard. The best digital PLLs are constructed with emitter -coupled logic
(ECL) elements, at the expense of high power con sumption. To keep phase noise low in PLL
circuits, it is best to avoid saturating logic families such as transistor -transistor logic (TTL) or CMOS.

Another desirable property of all PLLs is that the phase and frequency of the generated clock be
unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the
voltage of the substrate on which the PLL circuits are fabricated. This is called substrate and supply
noise rejection. The higher the noise rejection, the be tter.

To further improve the phase noise of the output, an injection locked oscillator can be employed
following the VCO in the PLL.

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In digital wireless communication systems (‰SM, CDMA etc.), PLLs are used to provide the local
oscillator for up-conversion during transmission and down-conversion during reception. In most
cellular handsets this function has been largely integrated into a single integrated circuit to reduce
the cost and size of the handset. However, due to the high performance required of base station
terminals, the transmission and reception circuits are built with discrete components to achieve the

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For instance, the frequency mixer produces harmonics that adds complexity in applications where
spectral purity of the VCO signal is important. The resulting unwanted (spurious) sidebands, al so
called "reference spurs" can dominate the filter requirements and reduce the capture range and lock
time well below the requirements. In these applications the more complex digital phase detectors
are used which do not have as severe a reference spur co mponent on their output. Also, when in
lock, the steady-state phase difference at the inputs using this type of phase detector is near 90
degrees. The actual difference is determined by the DC loop gain.

A   charge pump phase detector must always have a ""c" where the phases of
inputs are close enough that the detector detects no phase error. For this reason, bang -bang phase
detectors are associated with significant minimum peak -to-peak jitter, because of drift within the
dead band. However these types, having outputs consisting of very narrow pulses at lock, are very
useful for applications requiring very low VCO spurious outputs. The narrow p ulses contain very
little energy and are easy to filter out of the VCO control voltage. This results in low VCO control line
ripple and therefore low FM sidebands on the VCO.

In PLL applications it is frequently required to know when the loop is out of loc k. The more complex
digital phase -frequency detectors usually have an output that allows a reliable indication of an out of
lock condition.

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The block commonly called the PLL loop filter (usually a low pass filter) generally has two distinct
functions.

The primary function is to determine loop dynamics, also called stability. This is how the loop
responds to disturbances, such as changes in the ref erence frequency, changes of the feedback
divider, or at startup. Common considerations are the range over which the loop can achieve lock
(pull-in range, lock range or capture range), how fast the loop achieves lock (lock time, lock -up time
or settling time) and damping behavior. Depending on the application, this may require one or more
of the following: a simple prop ortion (gain or attenuation), an integral (low pass filter) and/or
derivative (high pass filter ). Loop parameters commonly examined for this are the loop's gain margin
and phase margin. Common concepts in control theory including the PID controller are used to
design this function.

The second common consideration is limiting the amount of reference frequency energy (ripple)
appearing at the phase detector output that is then applied to the VCO control input. This frequency
modulates the VCO and produces FM sidebands commonly called "reference spurious". The low
pass characteristic of this block can be used to attenuate this energy, but at times a band reject
"notch" may also be useful.

The design of this block can be dominated by either of these considerations, or can be a complex
process juggling the interactions of the two. Typical trade -offs are: increasing the bandwidth usually
degrades the stability or too much damping for better stability will reduce the speed and increase
settling time. Often also the phase -noise is affected.


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All phase-locked loops employ an oscillator element with variable frequency capability. This can be
an analog VCO either driven by analog circuitry in the case of an APLL or driven digitally through
the use of a digital-to-analog converter as is the case for some DPLL designs. Pure digital
oscillators such as a numerically -controlled oscillator are used in ADPLLs.

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An Example Digital Divider (by 4) for use in the Feedback Path of a Multiplying PLL

PLLs may include a divider between the oscillator and the feedback input to the phase detector to
produce a frequency synthesizer. A programmable divider is particularly useful in radio transmitter
applications, since a large number of transmit frequencies can be produced from a single stable,
accurate, but expensive, quartz crystal ±controlled reference oscillator.

Some PLLs also include a divider between the reference clock and the reference input to the phase
detector. If the divider in the feedback path divides by  and the reference input divider divides by
, it allows the PLL to mult iply the reference frequency by  / . It might seem simpler to just feed
the PLL a lower frequency, but in some cases the reference frequency may be constrained by other
issues, and then the reference divider is useful.

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