PAJ6100U6 - NonNDA Datasheet

PAJ6100U6 General Datasheet
PixArt Imaging Inc. Ultra-Low Power (ULP) Computer Vision Camera Module
PAJ6100U6: Ultra-Low Power (ULP) Computer Vision Camera Module
General Description Applications

PAJ6100U6 is an Ultra-Low Power (ULP) Computer  Imaging devices
Vision Camera with an integrated image pipeline that  Computer vision
incorporates a unique power saving architecture. With  AI Machine-Learning Devices
the low power consumption, this camera module is
suited to provide ultra-low power visual means to AI
machine-learning devices and imaging applications in Key Parameters
battery-powered and devices, when coupled with an AI
capable backend. Parameter Value
Array Size 320 x 240
This camera module incorporates a monochrome
CMOS image sensor with 320x240 QVGA resolution. Pixel Size 3 x 3 µm
The sensor uses global shutter pixel architecture Frame Rate 30 fps (Typically for burst
coupled with ROI (Region of Interest) and mode readout)
skipping/binning mode in a highly integrated design. Signal to Noise Ratio (SNR) Max 40dB
The pixel data from the camera, can be output via Dynamic Range  54dB
Parallel interface while the control command is via SPI
System Clock 6 MHz
interface.
Interface Parallel, 4-wire SPI
For ease of manufacturing, the sensor is packaged with
Supply Voltage VDD33 : 3.3V
re-flowable optics, giving it additional flexibility through
VDD18 : 1.8V
traditional SMT process.
VDDIO : 1.2V or 1.8V
Key Features Average Operating Power 1400µW@30fps QVGA
 Global shutter image module Consumption 600µW@30fps QQVGA
 Integrated ISP function Package Size (LWH) 4.1 x 3.9 x 2.2 mm
 Black-level correction
 Flexible analog pixel Region of Interest (ROI) with
binning and skipping
 Low power architecture design
 Supporting two interfaces
 Parallel: VSYNC/HSYNC/PXCLK/PXD0~PXD7
 4-wire SPI: SSN/SCK/MISO/MOSI
 Flexible image control configuration
Ordering Information
Part Number Description Package Type Packing Type MOQ
PAJ6100U6 Ultra-Low Power (ULP) Computer LGA 26-pins Module Tray TBD
Vision Camera Module
For any additional inquiries, please contact us at https://www.pixart.com
Version 0.92 | 04 Jul 2019 | C1003AEN
PixArt Imaging Inc. 1

All rights reserved. Any portion in this paper shall not be reproduced, copied, or transformed to any other forms without permission.
Table of Contents
General Description ...................................................................................................................................................... 1
Key Features.................................................................................................................................................................. 1
Applications................................................................................................................................................................... 1
Key Parameters ............................................................................................................................................................. 1
Ordering Information .................................................................................................................................................... 1
Table of Contents ............................................................................................................................................................... 2
List of Figures ..................................................................................................................................................................... 3
List of Tables ...................................................................................................................................................................... 3
1.0 Introduction ........................................................................................................................................................... 4
Overview ........................................................................................................................................................... 4
Block Diagram.................................................................................................................................................... 4
Terminology ...................................................................................................................................................... 5
Signal Description .............................................................................................................................................. 5
2.0 Operating Specifications ........................................................................................................................................ 7
Absolute Maximum Ratings ............................................................................................................................... 7
Recommended Operating Conditions ............................................................................................................... 7
DC Electrical Characteristics .............................................................................................................................. 8
AC Electrical Characteristics .............................................................................................................................. 8
Optical Specifications ........................................................................................................................................ 9
3.0 Mechanical Specifications .................................................................................................................................... 10
Package Mechanical Dimension ...................................................................................................................... 10
Package Marking Identification ....................................................................................................................... 10
4.0 Design References................................................................................................................................................ 11
General Reference Schematic ......................................................................................................................... 11
PCB & FPC Manufacturing Guidelines ............................................................................................................. 12
4.2.1 Pad Design on PCB and FPC ....................................................................................................................... 12
4.2.2 Stiffener Design of FPC .............................................................................................................................. 12
4.2.3 Stencil Design for SMT Process .................................................................................................................. 12
Recommended Reflow Profile ......................................................................................................................... 13
Document Revision History .............................................................................................................................................. 14
This product is still under product development where the product specifications are subjected to change upon product release.
Version 0.92 |4 Jul 2019 | C1003AEN
PixArt Imaging Inc. http://www.pixart.com

2
List of Figures
Figure 1. Functional Block Diagram ................................................................................................................................... 4
Figure 2. Pin Assignment (Bottom View) ........................................................................................................................... 5
Figure 3. Package Outline Diagram.................................................................................................................................. 10
Figure 4. Reference Circuit for Module Configuration .................................................................................................... 11
Figure 5. Recommend Footprint Dimension (All dimensions are mm) ............................................................................ 12
Figure 6. Recommended Reflow Profile .......................................................................................................................... 13
List of Tables
Table 1. Signal Description ................................................................................................................................................ 6
Table 2. Absolute Maximum Ratings ................................................................................................................................. 7
Table 3. Recommended Operating Conditions .................................................................................................................. 7
Table 4. DC Electrical Specifications .................................................................................................................................. 8
Table 5. AC Electrical Specifications .................................................................................................................................. 8
Table 6. Optical Specifications ........................................................................................................................................... 9
Table 7. Code Identification............................................................................................................................................. 10

3
1.0 Introduction
Overview
The architecture of PAJ6100U6 is based on CMOS image sensor technology. It uses global shutter with 320x240
resolution. It has the flexibility to configure pixel ROI (The scheme is Prefixed ROI Region), pixel binning or pixel skip
ability to disable parts of the module array for power saving purpose. The pixel data can be output via Parallel interface
while the control command is via SPI interface.
This datasheet describes the mechanical specifications, electrical characteristics, functional configuration and registers
for PAJ6100U6.
Note: Throughout this document PAJ6100U6 is referred to as the camera module.
Block Diagram
The Figure 1 shows the functional blocks of the chip. Refer to the subsequent chapters for detailed information on the
functionality of the different interface blocks.
IMAGE ARRAY VDD33

PXD0~PXD7 VDD18
VSYNC VDDIO
PARALLEL POWER
AGND
HSYNC INTERFACE SUPPLY
DGND
PXCLK VSEN28
VDDA15
SSN RSTN
SCK IMAGE SYS_CLK

SPI
SIGNAL GPIO
MOSI INTERFACE INTR
PROCESSOR
MISO LED_CNTRL
CONTROL REGISTER
Figure 1. Functional Block Diagram

4
Terminology
Term Description
ISP Image Signal Processor
SPI Serial Peripheral Interface
Min. Minimum
Typ. Typical
Max. Maximum
CIS CMOS Image Module
ROI Region of Interest
Reg. Register
BLC Black Level Correction
Signal Description
Pin1
27
Figure 2. Pin Assignment (Bottom View)

5
Table 1. Signal Description

Pin No. Signal Name Type Description
Power Supplies
Main power supply of +3.3V. (Recommend to connect
1 VDD33 PWR
10µF&0.1uF to GND)
Main power supply of +1.8V (Recommend to connect
3 VDD18 PWR
10µF&0.1uF to GND)
I/O power supply: +1.2V or +1.8V (Recommend to connect
15 VDDIO PWR
10µF&0.1uF to GND)
It is internal regulator. Only for module using, don’t supply to
2 VSEN28 PWR
other component. (It must be connected 1µF to GND.)
It is internal regulator. Only for module using, don’t supply to
4 VDDA15 PWR
other component. (It must be connected 1µF to GND.)
8 DGND GND Digital ground
5 AGND GND Analog ground
Clock
IN External clock input pin. (Sole clock input of the CIS. Shall be
7 SYS_CLK
used for all data transfer from the CIS to the digital part of
SPI Control Interface chip.)
21 SSN IN SPI chip select pin
22 SCK IN Serial communications clock
23 MISO OUT Serial data output
24 MOSI IN Serial data input
Parallel Data Interface
16 PXD0 OUT Pixel data bit[0]
10 PXD7 OUT Pixel data bit[7] of parallel interface
19 HSYNC OUT Line signal of parallel interface
20 VSYNC OUT Frame signal of parallel interface
25 PXCLK OUT Pixel clock of parallel interface
Functional I/O
26 RSTN IN Reset pin (Active low)
External LED timing control pin. The width of this pulse is equal
9 LED_CNTRL OUT
to exposure time for the frame.
6 INTR OUT Interrupt pin (Active low)
No Connection
27 NC - This pin should be left floating.

6
2.0 Operating Specifications

Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
Parameters Symbol Min. Max. Unit Notes
Main Voltage Supply 1 VDD33 -0.3 3.6 V
Main Voltage Supply 2 VDD18 -0.2 2.1 V
I/O Voltage Supply VDDIO -0.3 2.1 V
I/O Pin Voltage VIO -0.3 VDDIO+0.3 V
I/O Pin Current IIO - 4 mA
Relative Humidity RH 0 85 % Non-condensing, Non-biased
Class 2 on all pins, as per
ESD ESDHBM - 2 kV human body model. JESD22-
A114E with 15 sec zap interval.
Storage Temperature TS -25 125 °C
Lead-free Solder
TP - 245 °C
Temperature
Notes:
At room temperature.
Maximum Ratings are those values beyond which damage to the device may occur.
Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional
operation under absolute maximum-rated conditions is not implied.
Functional operation should be restricted to the Recommended Operating Conditions.
Recommended Operating Conditions

Table 3. Recommended Operating Conditions
Description Symbol Min. Typ. Max. Unit Notes
Ambient Operation
TA -30 25 85 °C
Temperature
Main Voltage Supply 1 VDD33 3.135 3.3 3.465 VInclude ripples
Main Voltage Supply 2 VDD18 1.71 1.8 1.89 VInclude ripples
Include ripples
1.71 1.8 1.89 V
For 1.8V I/O interface
I/O Voltage Supply VDDIO
Include ripples
1.14 1.2 1.26 V
For 1.2V I/O interface
Digital I/O Driving Ability IDDIODR - - 4 mA At VDDIO=1.8V
Square wave
System clock frequency fsysclk 5.82 6.00 6.18 MHz
Duty cycle = 45% ~ 55%
Note: PixArt does not guarantee the performance if the operating temperature is beyond the specified limit.

7
DC Electrical Characteristics
Table 4. DC Electrical Specifications
Parameters Symbol Min. Typ. Max. Unit Conditions
IDD33_QVGA - 180 - At QVGA image size, exposure
μA time = 10000T, 30fps
IDD18_QVGA - 455 -
DC Supply Current
IDD33_QQVGA - 88 - At QQVGA image size, exposure
μA time = 10000T, 30fps
IDD18_QQVGA - 180 -
IDD33_PD - 3 -
Power Down Current μA
IDD18_PD - 5 -
I/O Input High Voltage VIH 0.7* VDDIO - VDDIO +0.3 V
I/O Input Low Voltage VIL -0.3 - 0.3* VDDIO V
I/O Output High Voltage VOH 0.8* VDDIO - VDDIO V
I/O Output Low Voltage VOL -0.1 - 0.2* VDDIO V
Peak to peak voltage.
Power Ripple Noise VNPP - - 50 mV It is suitable for VDD33, VDD18
and VDDIO.
Note: All the parameters are tested under operating conditions: VDD33 = 3.3V, VDD18 = 1.8V, VDDIO = 1.8V, TA = 25°C
AC Electrical Characteristics
Table 5. AC Electrical Specifications
Parameters Symbol Min. Typ. Max. Unit Conditions
@ Cload = 0.5pF & Voltage Level
System Clock Rise Time tr - - 5 ns
= 10% ~ 90% & fsysclk = 6MHz.
@ Cload = 0.5pF & Voltage Level
System Clock Fall Time tf - - 5 ns
= 10% ~ 90% & fsysclk = 6MHz.
Note: All the parameters are tested under operating conditions: VDD33 = 3.3V, VDD18 = 1.8V, VDDIO = 1.8V, TA = 25°C

8
Optical Specifications
Table 6. Optical Specifications
Parameters Symbol Description Unit Conditions
Composition - 1 Element -
Barrel Material - LCP (BLACK) -
Center ≥ 50 % At 41 lp/mm
MTF
0.7 Field ≥ 50 % At 41 lp/mm
F No. F# 2.71 -
Parameters Symbol Low High Unit Conditions
87.0 93.0 Diagonal
Field of View FOV 69.9 74.7 degree Horizontal
52.7 56.3 Vertical

9
3.0 Mechanical Specifications

Package Mechanical Dimension
Figure 3. Package Outline Diagram
Package Marking Identification

Refer to Figure 2. for the code marking location on the device package.
Table 7. Code Identification
Marking Description
XX XX=Assy lot code (optional)
ABCD ABCD=Datecode

10
4.0 Design References

General Reference Schematic
Figure 4. Reference Circuit for Module Configuration

11
PCB & FPC Manufacturing Guidelines

4.2.1 Pad Design on PCB and FPC
Pad size design:
 If use solder mask defined (SMD), pad size refers to solder mask opening size.
 If use non-solder mask defined (NSMD), pad size refers copper metal size.
Recommended dimension of pad is shown in below figure. The actual pad size design will need to consider
component aside.
Figure 5. Recommend Footprint Dimension (All dimensions are mm)
4.2.2 Stiffener Design of FPC

For FPC (Flex) board, need add stiffener for FPC (Flex) back-side (at Sensor package area) to enhance the flex strength.
 Recommended stiffener type: FR4 or Stainless steel.
 Recommended stiffener thickness: minimum 0.4mm for FR4 type, minimum 0.15mm for stainless steel.
4.2.3 Stencil Design for SMT Process

 Recommend to use 0.1 ~ 0.12mm thickness stencil for SMT process.
 The stencil thickness selection will need to consider passive component size aside package.
 In case of the package is surface mounted on FPC (Flexible Printed Circuit Boards), the overall thickness of cover
layer & adhesive layer is recommended to be controlled less than 40um.

12
Recommended Reflow Profile

The typical recommended reflow profile is shown as below.
Average Ramp-up Rate (30’C to preheat zone): 1.5~ 2.5 Degree C/ Sec.
Preheat zone:
 Temp ramp from 170~ 200 degree C.
 Exposure time: 90 +/- 30 sec.
Melting zone:
 Melting area temp > 217 degree C for 60 ~ 80 sec.
 Peak temperature: 245 degree C.

Figure 6. Recommended Reflow Profile

13
Document Revision History

Revision Date Description
Number
0.92 04 Jul 2019 First creation General Datasheet (Based on DS v0.92)

14

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PAJ6100U6 General Datasheet

PAJ6100U6: Ultra-Low Power (ULP) Computer Vision Camera Module

General Description Applications

For any additional inquiries, please contact us at https://www.pixart.com

Version 0.92 | 04 Jul 2019 | C1003AEN

PixArt Imaging Inc. 1

PixArt Imaging Inc. http://www.pixart.com

PixArt Imaging Inc. http://www.pixart.com

IMAGE ARRAY VDD33

SCK IMAGE SYS_CLK

Figure 1. Functional Block Diagram

PixArt Imaging Inc. http://www.pixart.com

Figure 2. Pin Assignment (Bottom View)

PixArt Imaging Inc. http://www.pixart.com

Table 1. Signal Description

PixArt Imaging Inc. http://www.pixart.com

2.0 Operating Specifications

Recommended Operating Conditions

PixArt Imaging Inc. http://www.pixart.com

PixArt Imaging Inc. http://www.pixart.com

PixArt Imaging Inc. http://www.pixart.com

3.0 Mechanical Specifications

Figure 3. Package Outline Diagram

Package Marking Identification

PixArt Imaging Inc. http://www.pixart.com

4.0 Design References

Figure 4. Reference Circuit for Module Configuration

PixArt Imaging Inc. http://www.pixart.com

PCB & FPC Manufacturing Guidelines

Figure 5. Recommend Footprint Dimension (All dimensions are mm)

4.2.2 Stiffener Design of FPC

4.2.3 Stencil Design for SMT Process

PixArt Imaging Inc. http://www.pixart.com

Recommended Reflow Profile

Figure 6. Recommended Reflow Profile

PixArt Imaging Inc. http://www.pixart.com

Document Revision History

PixArt Imaging Inc. http://www.pixart.com

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