2012 24th International Conference on Microelectronics (ICM)

Comparative Study of Current Mode and Voltage Mode Sense

Amplifier used for 28nm SRAM
Baker Mohammad1,2, Percy Dadabhoy2,, Ken Lin2, Paul Bassett2
1
Khalifa University of Science, Technology and Research, Abu Dhabi UAE
2
Qualcomm Incorporated, Austin Tx, USA

Abstract—Increased process variation and reduced operating

voltage present two of the main challenges in using sense
amplifiers for small geometry bulk CMOS process technology.
This fact coupled with the need to increase on-chip memory to
reduce traffic on the bus and increase performance creates the
need for a robust and reliable sense amplifier - a differentiating
factor in memory area, power, and speed. We present a detailed
study of the Voltage Latched Sense Amplifier (VLSA) and the
Current Latched Sense Amplifier (CLSA) design in 28nm
industry standard process technology [1][2]. We present results
on how the two sense amplifier behave for the two design
topology for low power (LP) process technology optimized for
mobile low leakage application and the second one is high
performance High Performance (HP) applications. Detailed
Spice simulation with statistical models and Monte Carlo
simulations is utilized to compare the two designs for active
power, leakage power, speed, and area. Our study shows that
VLSA performs better than CLSA - being 67% faster, 35%
smaller area, and similar active power for the LP. The VLSA
also performed better than the CLSA is the HP technology as
well. The sensitivity to temperature for the LP technology node
was more at high voltage but for the HP process the lower voltage
perform worse.

Index Terms—Cache memory, sense amplifier, small signal

array, SRAM Array

I. INTRODUCTION

E MDEDDED memory forms an integral part of the design of

today’s processors and SOC. The main purpose of
embedded memory in general and cache in particular is to
improve the instruction and data access time. Larger caches
are favored since they can potentially reduce the number of
time-expensive external memory accesses. The propagation
delay of each cache datapath element directly contributes to
the total access time. A reduction in the propagation delay of
the datapath can aid in building larger caches, as large caches
may have several levels of multiplexing.
One of the elements of the datapath in an SRAM design is
Manuscript received February 14, 2012. This work was supported by
Qualcomm Inc.
Baker Mohammad is Assistant Professor in ECE at Khalifa University of
Science, Technology, and Research, Abu Dhabi, UAE (e-mail:
baker.mohammad@kustar.ac.ae)
Figure 1. Basic schematic of one column for small signal
memory array using 6T cell
the sense amplifier. The sense amplifier activated during a
read operation is used to sense the votlage differential on the
bitlines at its input, and generate a full-rail voltage swing at its
output (figure 1). The reduced swing on the memory bitlines
improves performance and also reduces power consumption
[3].
In this paper we explore the design robustness of sense
amplifiers for low voltage operation by comparing two sense
amplifiers designs in two variation of 28nm process
technology one is optimized for mobile application (LP) and
the other is targeted for high performance circuits (HPM)
[1][2]. We compare the two designs based on various factors
such as power, delay, sensitivity and area. The two sense

978-1-4673-5292-5/12/$31.00 ©2012 IEEE


A d d r,
e n a b le
c lk
W L
T r ig g e r V bl
BL &BLB
Ta
SA_en
dout
Figure 2 Timing relationship between main control
signals of a 6T memory array
amplifier topologies compared are the current latched sense
amplifier (CLSA), and the voltage latched sense amplifier
(VLSA). The methods used for the measurement of the
different comparison metrics is explained, along with a
presentation of the results.
The paper is organized as follows: Section II presents an
overview of the design principles of a small signal array;
Section III briefly explains the topology and operation of the
sense amplifiers; Section IV explains the measurement of the
different comparison metrics, and Section V concludes the
paper.
II. BASIC DESIGN PRINCIPLE OF SMALL SIGNAL ARRAY
Six transistor cell (6T) based memory is widely used for
embedded memory due to its small area [3] and relatively fast
access time. One important design parameter for memory
especially when using 6T, is area utilization, which compares
the actual memory cell area to the total area of the memory
Figure 3: a) CLSA sense amplifier schematic and layout showing matching transistors b) VLSA sense amplifier
schematic and layout
which includes the memory cell area, all input, output,
wordline drivers, and any other control or multiplexing
circuitry. Consider a 32KB memory design where the single
6T memory cell area is 0.2um2, then the total cell area is
If the complete design of the 32KB area is 150000 um2 then
the utilization is 33%. Typical values for level 1 (L1) caches
are 25-40% and for L2 is 60-70%. The reason for this
difference between L1 and L2 is that L1 is built for
performance with smaller capacity, while for L2 the emphasis
is on density and less on speed. Using a sense amplifier
provides the ability to have many cells in the same column
(figure 1) and hence sharing of the pre-charge, write driver,
and sense amplifier circuits which reduces the overhead. The
bitline then does not need a full voltage swing when using a
sense amplifier to transfer the data value from the cell to the
output but rather a small differential (0.2*Vdd), which
provides low power during read access.
The main timing signals and its relative trigger time are
shown in Figure 2. The access is normally triggered from a
clock edge which de-asserts the pre-charge (off) and asserts
WL signal (turn it on) to access the cell. The self time Sa_en
signal gets asserted through a tracking circuitry after enough
voltage difference gets created between BL and BLB. The
Sa_en signal enables the sense amplifier to sense the
difference in voltage which is based on the data stored in the
6T. The sense amplifier also stores the data value in the latch
to make it available for downstream logic. The time from WL
to Sa_en (Ta) is the array access time and is programmable
through a tracking circuit. This programming enables a
tradeoff between timing, power and yield.
 III. CLSA & VLSA SENSE AMPLIFIERS
TABLE I: LP TECHNOLOGY SENSE AMPLIFIER METRIC
The CLSA & VLSA sense amplifier topologies are shown
COMPARISON
in figure 3a and b respectively. Both sense amplifiers have the Metrics VLSA/CLSA
‘bit’ and ‘bitb’ inputs connected to the column bitlines of the
Area 0.65x
SRAM. The sense input is actuated once the requisite voltage
Bitline input capacitance 3.2x
differential has developed on the bitlines. Each sense amplifier
Sense enable capacitance 1.5x
has the cross-coupled inverters that convert the voltage
differential at their inputs on the bitline to a full swing at the
TABLE II: DELAY AND LEAKAGE COMPARESON
outputs. The output inverters in each sense amplifier are used
FOR CLSA AND VLSA FOR BOTH LP AND HPM
for driving the downstream logic, and also serve to isolate the
internal nodes of the sense amplifier from the external load. delay CLSA VLSA
Figure 3a shows the CLSA sense amplifier design. Since LP 3.03 1
this is a current latched design, the bitlines drive the gates of HPM 1.56 0.63
transistors M9 and M10. Transistors M1, M4, M5 and M8 are
the precharge transistors. Transistors M2,M6 and M3,M7 form Leakage CLSA VLSA
the inverter pair that resolves the bitline differential voltage. LP 0.28 1
Traditionally this topology has been used because the memory HPM 3.36 1.79
bitlines are driving high impedance (gate) and full discharge
of array bitline due to timing mismatch is not a concern. triggering of the sense amplifier, transistor M7 is off and pass
Figure 3b shows the VLSA sense amplifier design transistors M1 and M4 are on. As the differential develops on
(schematic and layout in the 28nm design rules) . M2-M5 and the bitlines, it does so too on the internal nodes of the sense
M3-M6 form the inverters that resolve the differential voltage amplifier ‘sol’ and ‘sor’. When the sense signal ‘saenb’ is
on the bitlines to a full-swing at the output. The internal nodes asserted, the cross-coupled inverters formed of M2-M5 and
of this design are precharged through the bitlines. The obvious M3-M6 amplifies this differential voltage to its full-swing
advantage of this topology over the CLSA is the lower number output.
of transistors needed which means faster access and smaller
footprint. The challenge in using this topology has been the IV. COMPARISON METRICS
race condition for isolation signal that decouples the sense
amplifier bitline (sol, sor) from the array bitline (bit, bitb). If Simulations are performed on the two sense amplifier
the sense amplifier is enabled while M1 and M4 are on, the designs using full post layout netlist and same design flow
memory bitline (bit or bitb) could be discharged to logic 0. In used to qualify production level design. Both design have
traditional designs, a different signal other than sen (isolate) is same stimuli and drive same load for comparison. The metrics
used to control M1 and M4 which makes it hard to match chosen for comparison help to describe all aspects of operation
sense and isolate operation, but for our design we used the of the sense amplifier that are useful from a design
same signal that enable the sense amplifier to isolate the array perspective. Table I shows the comparative results of these
bitlines. simulations

Operation A. Speed of Operation

1) CLSA:
The operation of this sense amplifier design is based on the
current differential produced by M9 and M10 in the two pull
down branches of the sense amplifier. At the commencement
of the read operation, either one of the ‘bit’ or ‘bitb’ inputs is
lowered depending on the data stored in the cell. When the
sense amplifier is triggered by the lowering of the input
‘saenb’, M11 turns on and the precharge transistors are
simultaneously turned off. Since the gate voltage of M9 and
M10 differs by the generated bitline differential, their channel
currents are unequal. The current thus flowing in the two
branches of the sense amplifier is unequal and the voltage at
either ‘out’ or ‘outb’ falls faster than the other node. This
difference in voltage is resolved by the cross-coupled inverters
formed of M2,M6 and M3,M7.
2) VLSA:
This design operates directly based on the voltage
differential developed on its internal nodes by the input
bitlines. When the wordline is turned on and prior to the
Spice simulation with fully extracted post layout netlist was
performed to compare the delay of both sense amplifiers. The
same waveform input for both bitlines and sense enable was
used. The speed of operation is determined by measuring the
50% delay that it takes for the internal nodes of the sense
amplifier, once the sense amplifier is triggered. In LP
technology, the VLSA is 67% faster than the CLSA.
B. Area
Figure 3 (a) and (b) show the layouts for the CLSA and
VLSA designs respectively. The transistor area for the VLS
design is 35% less as compared to the CLSA design. The
transistors that form the inverter pair in each sense-amp are
also shown in the figure. The NMOS transistors are
highlighted using red, and the PMOS transistors are shown
circled in black
C. Leakage
Contemporary aggressive low power designs continuously
 Figure 4: Normalized required offset voltage for LP process a) CLSA and b) VLSA sense amplifiers across process corners,
voltages and temperatures (VLSA requires half the offset compared to CLSA at the same PVT corner)
Figure 5: Normalized required offset voltage for HPM process a) CLSA and b) VLSA sense amplifiers across process corners,
voltages and temperatures (VLSA requires half the offset compared to CLSA at the same PVT corner)
demand increasing performance within constant or smaller
power budgets. With advancing process nodes usually
characterized by higher leakage, keeping leakage power to an
acceptable portion of the total power budget is a perpetual
challenge.
High accuracy simulations are performed using Spice to
obtain the leakage of the sense amplifiers. The simulations are
performed for a long duration in order to ensure settling time
and high accuracy results. The leakage profile of the sense
amp is also analyzed to identify transistor channel length and
threshold voltage types that can be modified to improve the
leakage power consumption of the design. These changes must
be made with minimal impact on the operation speed of the
sense amplifier. Table 2 lists the leakage ratio for the CLSA
and VLSA and shows that CLSA is less leakage due to
stacking effect compare to the VLSA. As expected HPM
exhibit higher leakage than the LP process.
D. Dynamic Energy
The energy consumed by the sense amplifier in operation is
determined by measuring the work done by the supply voltage
source. In Spice, this can be accomplished by measuring the
charge that is supplied by a voltage source during the
operation interval of the sense amplifier. The operation
interval commences once the sense amplifier is triggered, and
until the internal node of the sense-amp changes state to store
the new data present at its input. Spice was used to measure
the charge supplied by the voltage source during this operation
interval, and the corresponding energy is then computed
mathematically.
E. Input Capacitance
As mentioned earlier, the sense amplifier is one element of
the SRAM datapath and hence its compatibility with upstream
blocks is necessary. The input capacitance of the sense
amplifier is measured using a Spice AC analysis as well as
through a transient simulation
1) AC analysis: In this method a small amplitude AC source is
applied to the input of the sense amplifier and Spice is used to
measure the imaginary part of the current flowing through the
source. This is then used to mathematically compute the
impedance of the sense amplifier inputs.
2) Transient simulation: A small amplitude voltage
differential is applied to the inputs of the sense amplifier, and
the charge transferred from the source is measured. The
measured magnitude of the charge transferred is used to
mathematically determine the input capacitance of the sense
amplifier.
F. Sensitivity The function of the sense amplifier is to
resolve the voltage differential applied at its inputs to a full
swing at the output. This important characteristic of the
sense amplifier determines the minimum input voltage
differential between sa_BL and sa_BLB (as shown in figure
1.) required for ensuring reliable and proper operation of the
sense amplifier This minimum voltage will be referred to as
offset voltage (Vdiff). During a read operation, one cell of
each column in the array is turned on and it discharges a
bitline dependent on the data stored in the cell. The bitline
voltage differential thus developed is applied to the input of
the sense amplifier. A sense amplifier with low sensitivity
will require a higher voltage differential. For large cache
designs that have long bitlines with many bitcells, this
results in higher power dissipation and longer access time.
The sensitivity of the sense amplifier thus plays an important
role in determining the dynamic power dissipation of the
SRAM design While it is important to use a lower bitline
differential to improve power characteristics, it should be
sufficiently high to ensure reliable operation. Monte Carlo
simulations with full transistor spice mismatch models are
performed to determine the sensitivity in the presence of
process variation. A 1000 sample Monte Carlo simulation is
performed for different process corners. The industry
standard five corners (SS, SF, FS, TT, FF) is used. The two
letters indicate the speed of NMOS and PMOS respectively
for example SS referes to slow nMOS and slow PMOS
while SF indicate slow NMOS and fast PMOS. The
number of functional failures for a range of different bitline
differential voltages (Vdiff) is observed to determine the
sensitivity. We determined the required minimum voltage
offset (Vdiff) to be the one where we achieve zero error for
the entire 1000 samples. We simulated both design
topologies on the two technologies LP and HPM. We show
that VLSA design is more robust and less sensitive to
process and temperature variation. Figures 4 & 5 show the
variation in the minimum input offset voltage for sense-amp
operation for the CLSA and VLSA designs. Note that the Y-
axis has the normalized offset voltage for the CLSA &
VLSA designs. We used Monte Carlo simulations with full
Figure 6. Increase in offset voltage for LP tech sense amp compared to HPM (a) CLSA (b) VLSA
Figure 7. Increase in offset voltage for cold vs. hot temperature (a) LP CLSA (b) LP VLSA
mismatch models at each process corner to determine the
input offset voltage performed for four different
combinations of operating voltages and temperatures as
indicated in the figure, each line in the plot is for one
particular combination of voltage and temperature.
Simulations are done across different process corners (SS,
SF, FS, TT, &FF)[4]–[5] as also indicated in the figures. The
CLSA design shows large variation in the input offset
voltage across PVT corners as compared to the VLSA
design. Lower temperature exerts the worst performance
with the highest voltage offset required for both cases with
CLSA topology require almost twice the voltage offset
compared to VLSA at the same PVT corner.
G. Technology advantage
Advanced technology nodes enable higher transistor density
on the chip which allows the implementation of more
functions on the chip. Smaller transistors also operate faster
which enables higher operation frequencies. Simulations show
that the HPM technology CLSA sense-amp is 50% faster than
the design in LP technology. Similarly, the VLSA sense-ampis
37% faster. Monte Carlo simulations show that the advanced
process technology node also improves the minimum required
offset voltage of the sense amplifier. Lower offset voltage
requirements again translate into higher operation speed
benefits. Figure 6 shows the ratio by which the offset voltage
of each sense amplifier topology in the LP technology is
greater than that in the HPM technology. Each plot in the
figure is for a particular combination of supply voltage and
temperature, across the five different process corners. As can
be seen, the required offset voltage for the CLSA topology is
upto 30% lower in the HPM technology as compared to that in
the LP technology. Similarly, the required offset voltage is
about 45% greater in the LP technology for the VLSA design
as compared to the same design in HPM technology.

H. Temperature Sensitivity
Increased chip transistor density in advanced process
technology nodes also leads to higher chip operating
Figure 6: Percentage increase of required offset voltage
temperatures. It is thus pertinent to know the impact that
for -30C compare to same 125C PV 125C (hot)
temperature has on the required minimum offset voltage.
Temperature sensitivity
Figures 7 shows the extent to which the offset voltage
increases at cold as compared to hot temperatures for the LP
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by 15%-20% for the CLSA design. In the HPM technology, Circuit Technology, 2010, 10th IEEE International Conference on, pp.
this trend is reversed with higher increases for the offset 66–69.
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Technology withFully Functional 64Mb SRAM Using Dual/Tripe Gate
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[5] Baker Mohammad, Martin Saint-Laurent, Paul Bassett, and Jacob
Abraham. Cache Design for Low Power and High Yield, IEEE
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[6] Baker Mohammad, Jacob Abraham; A reduced Voltage Swing Circuit
This publication describes the simulation methodology used Using A single Supply to Enable Lower Voltage Operation for SRAM-
to compare the two VLSA and CLSA sense amplifier designs. based Memory; Microelectronics journal, Elsevier, December 2011
The simulations results clearly show the advantage of the
VLSA design over the CLSA design. The faster speed of
operation and lower input differential required by the VLSA
design makes it an ideal choice for high speed, low power
datapath design. Traditional design complexity arise from
using VLSA has also been addressed by using one signal to
enable the sense amplifier and to isolate the array bitline from
sense amp bitline (as shown in figure 3b).

Figure 8: Increase in offset voltage for cold vs. hot temperature for LP technology (a) CLSA design (b) VLSI