TUTORIAL

Spartan-7 SP701
FPGA Evaluation Kit
Demonstration Project
 THE FOLLOWING TABLE SHOWS THE REVISION HISTORY FOR THIS DOCUMENT.

Section Revision Summary

11/XX/2020 Version 2020.1

General updates Validated for release 2020.1

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 2

Table of Contents

- Revision History 2

- Hardware requirements 4

- Software requirements 4

- Project Objectives 4

- Introduction 5
- What is MIPI 6

- MIPI Interfacing 6

- Programmable Logic Design 7-11

- Step 1 7

- Step 2 8

- Step 3 9

- Step 4 9

- Step 5 10

- Step 6 11

- Software Development 12
- Step 7 12

- Step 8 12

- Step 9 12

- Conclusion 13

- References 13

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 3

 HARDWARE REQUIREMENTS
Once the licenses are installed, we
will need the following hardware to
create this project:
• SP701 Board
• Digilent Pcam 5C – MIPI Camera
• DSI Display
• HDMI Cable
• HDMI Display
• Digilent Pmod HYGRO

SOFTWARE REQUIREMENTS
Software development tools used
in the project:
• Xilinx Vivado Design Suite 2019.2 –
Used to develop the FPGA design
• Xilinx Vitis Unified Software
Platform – Used to develop the
software algorithms
• Xilinx Vivado Design Suite - HLS
Edition – Used to develop IP blocks
for implementation in the FPGA
design

PROJECT OBJECTIVES
This project is going to implement a CSI-2-based image-processing system
that outputs images over DSI or HDMI outputs. To demonstrate the capability
of the Spartan-7 FPGA for industrial applications, this solution will also
implement an overlay on the image displaying industrial information such as
temperature, humidity, altitude, etc.

The challenging element of this project is displaying the heads-up video

on the live feed, as the live video is stored within the external DDR. The
Xilinx MicroBlaze processor could therefore access the frame store in
the DDR memory and render the heads-up display (HUD). However, this
is computationally intensive and as such, the MicroBlaze processor is not
capable of keeping up with the 60 frames-per-second frame rate. Therefore,
a custom HLS block will be created to render the HUD. This removes the
heavy processing from the MicroBlaze processor so that it just has to the tell
the HUD what to render over the AXI interface.

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 4

 INTRODUCTION
Developing cost-effective industrial image-
processing systems requires the utilization
of high-performance cameras and flexible
image-processing systems capable of
adaption. The Xilinx SP701 Evaluation Kit
provides engineers with the ability to interface
with high-performance cameras and display
systems using the Mobile Industry Processor
Interface (MIPI) Camera Specification
Interface 2 (CSI-2) and Display Specification
Interface (DSI).

Both interfaces are connected to a Spartan-7

FPGA which is capable of directly interfacing
with the CSI-2 and DSI. Combined with DDR3L,
dual Ethernet, HDMI and FMC interfaces,
the SP701 Evaluation Kit provides everything
needed to quickly and easily prototype and
test industrial image-processing solutions.

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 5

WHAT IS MIPI?
MIPI is a high-bandwidth, point-to-point protocol used to
transfer image sensor or display information over several
differential serial lanes. Like most protocols, it works on
the OSI model with different layers of implementation.
The lowest level of the MIPI protocol is the DPHY, PPI
which defines the number of lanes, clocking, and the (Appendix)
TX Ctrl Logic
rather unique transition between differential (Scalable LP-TX
Data In Esc Encoder
Low Voltage Swing - SLVS) and single-ended signaling Data
IF
(LVCMOS). This combination of high-speed differential Logic HS-Serialize TX
Data Out
and low-speed, single-ended signaling enables the Sequences HS-TX Dp
high-bandwidth transfer of the image/display data using
a higher-level protocol such as CSI-2 or DSI. The low- Dn
Clocks-in
speed communication enables the low-level protocol HS-Deserialize
Data HS-RX RT
Sampler
information to be communicated at lower power.
Clocks-out RX

Each MIPI DPHY link may have between one and four Esc Decoder
LP-RX
high-speed serial links operating at up to 2.5 Gbps or 10 Control-in Ctrl Decoder
Gbps across all four lanes. Data transfer over these lanes
occurs at double the data rate and is synchronous to the Control-out
Ctrl State Machine
(Incl. Enables,
IF
clock lane. Logic Selects and
System Ctrl)
LP-CD

CD
Error Detect
MIPI INTERFACING Protocol
Lane Side
Side Lane Control & Interface Logic
Interfacing between the Spartan-7 FPGA and the CSI
and DSI interfaces is very simple thanks to the use of
external resistor networks that enable Spartan-7 IO to be
compatible with the MIPI DPHY standard up to 800 Mbps.

IC Supply Voltage (1.2V-3.3V+)

Low-power Signaling Level (e.g. 1.2V)

Minimum LP-RX
Low Threshold

HS Diff. Swing
(e.g. 200mV)
HS Common
Level
(e.g. 200mV)

Reference Ground

Figure 1 – MIPI DPHY TX example

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 6

PROGRAMMABLE LOGIC DESIGN

Step 1

Creating the programmable logic design (which

contains an image processing path for both the CSI-
2, DSI and HDMI) can be achieved in a few minutes.

To get started with creating this example, we first

need to create a new project targeting the SP701
board. From the IP library, add in the MIPI CSI-2 RX
subsystem.

Once this is added into the project, double click on

the MIPI IP core under the design sources. This will
enable it to be reconfigured. Leave the configuration
as it is with its default configuration and then select
the application example design.

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 7

Step 2
On the application example tab, select
the SP701 from the target board menu
before clicking OK and closing the MIPI
CSI-2 dialog box.
With the example application set for the
target board, the next step is to right
click on the MIPI CSI-2 block under the
Design Sources menu and select Open IP
Example Design.

This will prompt you to select a location to

save the example project before opening a
new Vivado project, which implements an
image-processing application (including
the CSI-2 input configured to be used
with the Pcam 5C and output images over
DSI and HDMI).

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 8

Step 3
We are going to update this image-
processing chain to create our application.
Updates to this image-processing design
include the following:
• Insertion of the Xilinx LogiCORE IP
Video Mixer to enable the Pcam 5C
video to be mixed with the heads-up
display overlay.
• Pmod HYGRO IP core
• HLS-created heads-up display IP
Starting with the Video Mixer, it will be
configured to enable one layer on top of
the master layer. This additional layer will
be supplied by the HUD IP block as an AXI
Stream and provide its pixel data as Red
Green Blue. It will also present the alpha
channel for the mixing of the layers. A
pixel-by-pixel alpha channel enables a
much more configurable HUD layer and
overall better output image.
The Video Mixer is configured as below
with its maximum size set to the 1920 by
1080, which matches the HD configuration
of the Pcam 5C.

Step 4
To be able to use the Pmod HYGRO, we
need to install the Digilent IP library.
Digilent provides a range of Pmod IPs that
can support Pmod usage in both hardware
and software development using the
Xilinx Vivado Design Suite and Software
Development Kit (SDK).
If you do not have the Pmod libraries
installed, you can install them here. Once
downloaded, add them to the Vivado
library project IP repository.

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 9

Step 5

To complete the design, we now need to create the HLS custom IP module. To create this,
we need to create a new project in Vivado HLS 2019.2
The approach taken in this project is to create an IP core that interfaces with the MicroBlaze
processor over the AXI Lite and with the image-processing system using AXI Stream.
This interfacing is easily controlled using the interfacing pragma and means each of the
interfaces can be implemented as desired. This means the information we wish to display
on the HUD is provided from the MicroBlaze processor into AXI Lite registers. Over AXI Lite,
the MicroBlaze processor can set the following parameters for the HUD:
• Control Register – Stop and start the IP core
Test Image Generated by the HUD IP
• Width – Number of pixels on a line Core and Captured by the Test Bench
• Line – Number of lines in the image
• Char 1 – First character to display on HUD
• Char 2 – Second character to display on HUD
The HUD IP core will output a bounding box around the edge of the screen and display
two characters that can be used to display the humidity or temperature read from the
Pmod HYGRO.
Drawing the text on the screen is quite simple with several small two-dimensional arrays
used. Each array of 11 lines consisting of 10 pixels contains a small representation of
numbers 0 to 9. The HUD display then outputs each pixel multiple times to scale up the
character for display. This enables a small number of block RAMS to be used when the
design is implemented on the FPGA.
To test this IP block, a test bench is created. This enables the output image to be captured
in black and white, showing the border of the image and display of the characters. This
leverages the ability of Vivado HLS to easily integrate and work with Open CV.

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 10

Step 6
With the performance of the HUD IP core as required, the module can be synthesized
and exported as an IP block to be included in our Vivado project.
This HUD IP is capable of rendering the HUD and outputting the HUD overlay using
only 10 Bram, four DSP and 1000 Flip Flops. As always with HLS, there is a trade off
between performance and resource utilization, and this HUD was designed to be able
to implement an initiation interval of one. The initiation interval is the time that is taken
between being able to start processing the next element of the HUD output. This means
the HUD can keep up with the 60 frames-per-second frame rate.
With the HLS IP available to our Vivado
design, the next step is to declare a
new IP repository and add in the new
HUD core.
This IP core needs to be connected
to the AXI Lite bus and the AXI Stream
input for the mixer layer one.
With the Vivado design updated, the
next step is to implement the design
and export the XSA for Vitis.

Resource Utilization of the

Synthesized HUD IP Block

Output Image Processing

System – Updated

Complete Updated Design

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 11

SOFTWARE DEVELOPMENT

The software development solution is also an update to

the existing reference application software.
To be able to do this, we just need to create a new
workspace and the import from the SW directory with
the following:
• HW_Description
• Embedded_System
However, we need to replace the hardware definition
with the updated design just exported from Vivado.

Step 7 Step 8

Configure the Video Mixer IP:

• Set the master layer to the correct width and height (1920 by 1080)
• Enable the master layer
• Set layer one to the correct width and height
• Enable layer one
The next step is to configure the custom HLS IP clock:
• Set the image width and height (1920 by 1080)
• Enable the HUD generation

Step 9

Updating the Hardware Specification Output Display Showing the HUD Overlaid on the Image Stream

In Vitis, right click on the SP701 platform and select

Update Hardware Specification. The final step is to read in the data from the Pmod HYGRO and then
This will allow us to update the hardware design to convert the floating-point output into two characters that can be passed
include that which has just been exported from Vivado to the HUD IP core for display. Of course, as the temperature increases or
so we can start our software development. decreases, the HUD is updated.

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 12

 CONCLUSION

This project has shown how quickly and easily a low-cost device
can be used to implement a high-performance imaging solution
interfacing with high-speed, high-bandwidth interfaces. This
application also shows how image-processing algorithms – such
as heads-up display – can be implemented in the programmable
logic quickly and easily using high-level synthesis to further
increase performance when limited processing power is available.

REFERENCE & FURTHER READING

1. HUD HLS Project - https://github.com/ATaylorCEngFIET/HUD
2. SP701 Vivado and Vitis Source https://github.com/ATaylorCEngFIET/SP701_Imaging_Vivado
3. Creating Image Processing HLS IP Cores
https://www.hackster.io/news/microzed-chronicles-creating-video-streams-with-vivado-hls-79de84de7117
4. Creating Advanced Image Processing HLS IP Cores
https://www.hackster.io/news/microzed-chronicles-hls-advanced-image-processing-ip-and-pynq-e550193efaff

Tutorial: Spartan-7 SP701 FPGA Evaluation Kit Demonstration Project 13