Application Notes

SpringSoft, Inc.

Floor Planning
Laker PnR package provides powerful editing capabilities for you to finish floor planning easily
and cost-effectively. In addition to importing design from LEF and DEF, Laker also allows you to
import design from LEF and Verlilog netlist. For importing design from LEF and Verilog netlist,
you can import LEF to create libraries first and then import Verilog design. The other way is
importing LEF and Verilog netlist simultaneously.

This document is aimed to guide you through some functions used during floor planning, such as:
Build design database by importing LEF files and Verilog netlists.
Define chip size.
IO cell planning with corner cells, power and ground cells can be inserted in a defined text
or CSV format.
Create power and ground core ring, straps and macro ring.
Connect power and ground between core ring, straps, IO cells and macro ring.
Partition design into groups.

Practice
Tutorial case, fpDemo.tar.gz, is provided under ./fpDemo/data.

Case
The case is prepared to familiar with floorplan capabilities of Laker PnR.

Steps
1 Set up the test case and working directory, and then invoke Laker with PnR license.
%tar zxvf fpDemo.tar.gz
%cd fpDemo
%mkdir work1
%cd work1
%laker –Level PnR
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2 Create database by importing LEF and Verilog netlist.
2.1 Invoke Create Database by selecting FloorplanÆCreate Database… in Main
Window.
2.2 Define the Design and Library and Configuration tabs of Create Database form.
Design and Library Tab Configuration Tab
Technology File: ../data/CHIP_32v1.tf Power and Ground: Net for 1’b0: GND
Verilog Library: fp
LEF Library: chipLef Lef1 Lef2
Verilog Design File: ../data/dualCoreIO.v
LEF Design File:
chipLef ../data/CHIP.lef
Lef1 ../data/RAMSPNL512X8.lef
Lef2 ../data/RAMSPNL256X8.lef
Reference Library for Link Verilog and LEF Library:
Check these libraries: chipLef, Lef1, Lef2.

Figure 1: Settings of Create Database->Design and Library tab & Configuration tab
2.3 Click OK to proceed.

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3 Open top design to do floor planning.
3.1 Invoke Open Cell by selecting FileÆOpen Cell in Main Window.
3.2 Select the library fp and the cell TEST.
3.3 Click OK to open the design, as illustrated below.

Figure 2: Library: fp Cell: TEST

4 Create chip boundary and core area.

4.1 Invoke Chip Size Setting by selecting FloorplanÆCreate Chip Size… in Layout
Window.
4.2 Define the Chip Setting group box as follows.
4.2.1 Choose Defined by Core AreaÆUser Assignment
4.2.2 Type 2500 for Core Width
4.2.3 Type 2500 for Core Height
4.2.4 Choose LowerLeft for Chip Origin

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 Figure 3: Settings of Chip Size Setting->Chip Setting group box
4.3 Define the Power/Ground Ring Area as follows.
4.3.1 Choose Unified Value and type 70 um for Power/Ground Area Width

Figure 4: Settings of Chip Size Setting->Power/Ground Ring Area group box

4.4 In the IO Cell Area
4.4.1 Choose Unified Value for IO Cell Height
4.4.2 Click on the arrow-down button to select io_site[chipLef] and its value will
show 211.75
4.4.3 Select R0 for Bottom IO Orientation

Figure 5: Settings of Chip Size Setting->IO Cell Area group box

4.5 Click OK to proceed.

NOTE: There are two ways to define chip size. One is defined by die size; the other is defined
by core area, which is illustrated in this case. For defined by core size, Laker also
provides Tool Estimation approach to estimate the die size according to stand cells’
utilization.

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5 Create corner cells to top design.
Sometimes, Verilog netlist does not include corner cells as they are not purposed for
connecting power and ground of IO cells. Verilog netlist may not include power and ground
cells, neither. Under this situation, you can use the Create IO Cells command to create those
cells.
5.1 Invoke Create IO Cells by selecting FloorplanÆIO PlanningÆCreate IO Cells in
Layout Window.
5.2 Type ../data/createCorner.dat in the File text box.

Figure 6: Create IO Cells

5.3 Click OK to proceed. In this case, four corner instances are created as follows.

Figure 7: Four corner instances are created

6 Place corner cells.

6.1 Invoke Place IO Cells by selecting FloorplanÆIO PlanningÆPlace IO Cells in
Layout Window.
6.2 Type ../data/cornerPlace.dat in the File text box.

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 Figure 8: Place IO Cells
6.3 Click OK to proceed. The four corner instances are placed into the cell boundary, as
illustrated below.

Figure 9: Four corner instances are placed into the cell boundary

7 Place IO cells into chip boundary

7.1 Invoke Plan IO by CSV/TEXT by selecting FloorplanÆIO PlanningÆ Plan by
CSV/TEXT Files… in Layout Window. In the CSV File group box,
7.1.1 Type ../data/ioText.csv on the File text box.
7.1.2 Type 0 on the Row Number of Field Title text box.
7.1.3 Choose Comma for Field Separator.
7.1.4 Define the field mapping of CSV file in the Field Mapping list and fill in the
mapping value as follows.

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 Figure 10: Plan IO by CSV/TEXT: CSV File settings
7.2 In the Place IO Cells group box,
7.2.1 Select Clockwise for Direction.
7.2.2 Select Spread for Style.
7.2.3 Select The Same on Each Slide for Pad Number.
7.2.4 Set the coordinate of Starting Point of X,Y as X=266.0 Y=0
You can also specify the other coordinate by mouse click on the layout window.

Figure 11: Plan IO by CSV/TEXT: Place IO Cells settings

7.3 Click OK to proceed. All IO cells are placed in the IO area, as illustrated below.

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 Figure 12: All IO cells are placed properly in IO area

8 Edit Core Area.

8.1 Change active layer to CoreBdry.
8.2 Invoke the Chop command by selecting EditÆChop in Layout Window.
8.3 Use the Rectangle option to cut the CoreBdry layer shape, as illustrated below.

Figure 13: Cut CoreBdry layer shape

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9 Create core ring.
9.1 Invoke Create Core Ring by selecting FloorplanÆPower PlanningÆCore/Power
Domain Ring… in Layout Window.
9.1.1 Net Names: VDD GND
9.1.2 Left/Right Net Layer: METAL2; Top/Bottom Net Layer: METAL1
9.1.3 Net Width: Set 20 for each.
9.1.4 Spacing of Inner Ring to Core: 10
9.1.5 Spacing between Rings: 10
9.1.6 Extend Inner Rings: On
9.1.7 Click Apply to proceed.

Figure 14: Create Core Ring

10 Connect core ring with power/ground IO cell.

10.1 Invoke Connect/Disconnect Power/Ground by selecting FloorplanÆPower
PlanningÆConnect… in Layout Window.
10.1.1 Type VDD in the Net Name text box.
10.1.2 Type VDD in the Port Pattern text box
10.1.3 Choose IO for Connection Type.
10.1.4 Choose Connect for Mode.
10.1.5 Click Apply to proceed. The net (VDD) of core ring wire will connect to IO
cells.
10.2 Change the value of Net Name and Port Pattern to GND.
10.3 Click OK to proceed. All of the nets (VDD, GND) will connect between IO cells and
core ring, as illustrated below (Max View Level).

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 Figure 15: All of the nets (VDD, GND) connect between IO cells and core ring

11 Place all macro cells in core area.

11.1 Disable Show Flight Line via Options->Preferences->Connectivity tab in Main
Window.
11.2 Use the Move command to place those macro cells, as illustrated below.

Figure 16: Place macro cells

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12 Create Macro Ring around the macro cells.
12.1 Invoke Create Macro Ring by selecting FloorplanÆPower Planning ÆMacro
Ring… in Layout Window. Set the following values in the form:
12.1.1 Specified Macros: Selected Macros
12.1.2 Net Names: VDD GND
12.1.3 Left/Right Net Layer: METAL2; Top/Bottom Net Layer: METAL1

Figure 17: Settings of Create Macro Ring

12.1.4 Net Width: Set 5 for each.
12.1.5 Spacing of Inner Ring to Macro: Set 5 for each.
12.1.6 Spacing between Rings: Set 10 for each.

Figure 18: Settings of Create Macro Ring

12.1.7 Click OK to proceed. The macro rings are created as illustrated below.

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 Figure 19: Macro rings

13 Create strap.
13.1 Invoke Create Strap by selecting FloorplanÆPower Planning ÆStrap… in Layout
Window. Set the following values in the form:
13.1.1 Net Names: VDD GND
13.1.2 Layer: METAL2 (METAL2 is available only when Vertical direction is
selected)
13.1.3 Width: 10
13.1.4 Spacing: 10
13.1.5 Direction: Vertical
13.1.6 Start X: 285

Figure 20: Settings of Create Strap

13.1.7 Configuration: Groups & Step
13.1.8 Groups: 9
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 13.1.9 Step: 300

Figure 21: Settings of Create Strap

13.1.10 Click OK to proceed. The straps are created as follows.

Figure 22: Straps

Conclusion
You have gone through most of the commonly used functions for floor planning.
For details of each function, refer to Laker Command Reference.

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