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COMP6004 Formal Design of Systems: Corina Cîrstea
COMP6004 Formal Design of Systems: Corina Cîrstea
COMP6004 Formal Design of Systems: Corina Cîrstea
Corina Cîrstea
Outline
Administrative Info
I Module team:
I Robert Walters (rjw1@ecs.soton.ac.uk)
I Corina Cîrstea (cc2@ecs.soton.ac.uk)
I Timetable:
I Lectures: Mondays (16:00-17:00, 58/1009)
Tuesdays (15:00-16:00)
I Tutorial: Tursdays (9:00-10:00)
Note: This week, only the Monday and Thursday slots will be
used (both for lectures).
Plan of Lectures
I 20 point module
I 50% exam
I Don’t copy
Reading List for the Theory Part
I advantages:
I fully automatic process (unlike theorem proving)
I can be used to perform partial verification (only certain
features are modelled, only certain properties are verified)
I terminates with yes/no answer
I error traces are informative
I logics used for specification can express a large class of
(usually temporal) correctness properties of systems
I disadvantages:
I state space explosion problem (when the system being verified
has many interacting components, or data structures with
many possible values)
I traditionally only works for finite state systems
Hardware/Software Model Checking
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Kripke Structures, Formally
4 @ABC
GFED
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GFED
@ABC / 89:;
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b c c s2
s1 H
I set of states: S = { s0 , s1 , s2 }
I set of initial states: { s0 }
I transition relation:
{ (s0 , s1 ) , (s0 , s2 ) , (s1 , s0 ) , (s1 , s2 ) , (s2 , s2 ) }
s0 −→ s2 s2 6−→ s0
I valuation V gives labelling of states with atomic propositions:
V (s0 ) = {a, b}
V (s1 ) = {b, c}
V (s2 ) = {c}
Example: Mutual Exclusion Protocol
bool turn;
P = m : cobegin P0 k P1 coend m0
P0 = n0 : while True do P1 = n1 : while True do
t0 : wait (turn = 0); t1 : wait (turn = 1);
c0 : use resource; turn := 1; c1 : use resource; turn := 0;
endwhile ; n00 endwhile ; n10
bool turn;
P = m : cobegin P0 k P1 coend m0
P0 = n0 : while True do P1 = n1 : while True do
t0 : wait (turn = 0); t1 : wait (turn = 1);
c0 : use resource; turn := 1; c1 : use resource; turn := 0;
endwhile ; n00 endwhile ; n10
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0, t0 , n1
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How would you model the possibility that a process does not
relinquish the shared resource after a finite amount of time?
Exercise
bool turn;
bool flag 0 = 0, flag 1 = 0;
P = cobegin P0 k P1 coend
P0 = while True do
flag 0, turn := 1, 1;
wait ((flag 1 = 0) || (turn = 0));
use resource; flag 0 := 0;
endwhile ;
P1 = while True do
flag 1, turn := 1, 0;
wait ((flag 0 = 0) || (turn = 1));
use resource; flag 1 := 0;
endwhile ;
Fairness Assumptions: Example
Is it fair that the second process has infinitely many possibilities to enter
the critical section, but never enters it?
Is it fair that the second process has infinitely many possibilities to enter
the critical section, but only enters it finitely many times?
Fairness Assumptions
That is, a liveness property does not rule out any finite prefix of an
execution.
Mutual Exclusion: the Specification
Correctness properties:
I mutual exclusion (safety): at most one process in critical
section at any time
I starvation freedom (liveness): whenever a process tries to
enter its critical section, it will eventually succeed
I non-blocking (liveness): a process can always, at some point
in the future, request to enter its critical section
I no strict sequencing: processes need not enter their critical
section in strict sequence
Exercise