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Verilog code:

//Verilog code
`timescale 1ns / 1ps

module RTL_FSM_VERILOG(
input clock,
input Stop,
output Out,

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output [3:0] CountOut
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//internal registers
//as we have 8 states , we need atleast 4 bits to store state value
reg [3:0] PS=4'd0; // PS => Present state, it is initialized to S0
wire [3:0] NS; //NS => Next

//D ip op for fsm

always @ (posedge clock)
PS <= NS;

//adder circuit => add's 1 to PS => PS1 = PS +1.

wire [3:0] PS1;
assign PS1 = PS + 4'd1;

//select NS based on Stop signal // 2 to 1 mux

assign NS = Stop ? PS : (PS == 4'd7) ? 4'd0: PS1;
// NS = PS when stop = 1
//else when stop = 0
// if PS = 7 then NS = 0.
// else NS = PS1

//output's
assign CountOut = PS; //state count
assign Out = ( PS == 4'b0010) ? 1'b1 : 1'b0; //Out = 1 only in state 2

endmodule
//code ends

test bench:

//Test bench
`timescale 1ns / 1ps

module TB_RTL_FSM_VERILOG();
reg clock;
reg Stop;
wire Out;
wire [3:0] CountOut;
//uut
RTL_FSM_VERILOG R1 (
.clock(clock),
.Stop(Stop),
.Out(Out),
.CountOut(CountOut)
);

//clock generation

initial begin
clock=1'b0; //50 MHz clock
forever #10 clock=!clock; //clock period=20ns
end

//stimulus

initial begin
Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
#15 Stop = 0;
#25 Stop = 1;
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#15 Stop = 0;
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#25 Stop = 1;
#15 Stop = 0;
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#20 $ nish;
end
endmodule
//test bench ends

//OUTPUT WAVEFORMS

***END

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