MICROCONTROLLER &

INTERFACING

COURSE INSTRUCTOR
ASHITOSH D. CHAVAN
 MASTER SYNCHRONOUS
SERIAL PORT MODULE
(MSSP)

1. Serial Peripheral Interface (SPI)

2. Inter-Integrated Circuit (I2C)
Master SSP (MSSP) Module Overview
• The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices.
• These peripheral devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc.
• The MSSP module can operate in one of two modes;
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
• Full Master mode
• Slave mode

• The I2C interface supports the following modes in hardware:

• Master mode
• Multi-Master mode
• Slave mode
MSSP Control Registers

• The MSSP module has three associated registers

• status register (SSPSTAT)

• Two control registers (SSPCON1 and SSPCON2)

• The use of these registers and their individual

configuration bits differ significantly depending on whether

the MSSP module is operated in SPI or I2C mode.
SPI Mode

• The SPI mode allows 8 bits of data to be synchronously transmitted

and received simultaneously.

• To accomplish communication, typically three pins are used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

• Slave Select (SS) : a fourth pin may be used when in a Slave mode of operation
SPI Mode Registers
• The MSSP module has four registers for SPI mode operation. These are:

• MSSP Control Register 1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register (SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly accessible

• SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The
SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
• SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to
which data bytes are written to or read from.
• In receive operations, SSPSR and SSPBUF together create a double-buffered receiver.
When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt
is set.
SPI Mode Registers

• During transmission, the SSPBUF is not double buffered. A write to SSPBUF will write

to both SSPBUF and SSPSR.

SPI Master/ Slave Connection
 𝟐
𝑰 C Mode & Registers
• The MSSP module in I2C mode fully implements all master and slave functions

• Two pins are used for data transfer:

• Serial clock (SCL)

• Serial data (SDA)

• The MSSP module has six registers for I2C operation. These are:

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register (SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly Accessible

• MSSP Address Register (SSPADD)

 𝟐
𝑰 C Mode & Registers
• SSPCON1, SSPCON2 and SSPSTAT are the control and status registers in I2C mode
operation.
• The SSPCON1 and SSPCON2 registers are readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the SSPSTAT are read/write.
• SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to
which data bytes are written to or read from.
• SSPADD register holds the slave device address when the MSSP is configured in I2C
Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPADD
act as the Baud Rate Generator reload value.
• In receive operations, SSPSR and SSPBUF together create a double-buffered receiver.
When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt
is set.
• During transmission, the SSPBUF is not double buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
𝟐
𝑰 C Registers