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Lab1 s2 Digt-Sys
Lab1 s2 Digt-Sys
Done by:
• TEDJANI Mohammed Ridha
• GEURGOUR Imad
Groupe: 04 subgroup 2
2. Objective:
• Get more familiar with VHDL in designing digital circuits
using buses.
• Writing different VHDL code using either WHEN-ELSE or
WITH-SELECT statement to implement the boolean functions.
• Mapping the circuit signals to the FBGA pins and
download the design onto the DE2 board.
PART 1 VHDL
Getting started:
• launch Quartus 2, then execute File/new Project Wizard
and choose the the name and the directory of the file.
• choose Cyclone 2 as the target Device Family, and from the
list of the available Devices, choose EP2C35F672C6.
• open file/new/VHD file and clikk OK to create a new
VHDL source code file.
Problem 1:
✓ with WHEN-ELSE statement
the simulation:
3. Conclusion:
In this LAB session, we wrote many diffrent codes with
VHDL under its diffrent statement in order to use it in
analysing the circuits as long as we are an electrical engineer.